1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
11
12/ {
13	compatible = "mediatek,mt8192";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	clk26m: oscillator0 {
19		compatible = "fixed-clock";
20		#clock-cells = <0>;
21		clock-frequency = <26000000>;
22		clock-output-names = "clk26m";
23	};
24
25	clk32k: oscillator1 {
26		compatible = "fixed-clock";
27		#clock-cells = <0>;
28		clock-frequency = <32768>;
29		clock-output-names = "clk32k";
30	};
31
32	cpus {
33		#address-cells = <1>;
34		#size-cells = <0>;
35
36		cpu0: cpu@0 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a55";
39			reg = <0x000>;
40			enable-method = "psci";
41			clock-frequency = <1701000000>;
42			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
43			next-level-cache = <&l2_0>;
44			capacity-dmips-mhz = <530>;
45		};
46
47		cpu1: cpu@100 {
48			device_type = "cpu";
49			compatible = "arm,cortex-a55";
50			reg = <0x100>;
51			enable-method = "psci";
52			clock-frequency = <1701000000>;
53			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
54			next-level-cache = <&l2_0>;
55			capacity-dmips-mhz = <530>;
56		};
57
58		cpu2: cpu@200 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a55";
61			reg = <0x200>;
62			enable-method = "psci";
63			clock-frequency = <1701000000>;
64			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
65			next-level-cache = <&l2_0>;
66			capacity-dmips-mhz = <530>;
67		};
68
69		cpu3: cpu@300 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a55";
72			reg = <0x300>;
73			enable-method = "psci";
74			clock-frequency = <1701000000>;
75			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
76			next-level-cache = <&l2_0>;
77			capacity-dmips-mhz = <530>;
78		};
79
80		cpu4: cpu@400 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a76";
83			reg = <0x400>;
84			enable-method = "psci";
85			clock-frequency = <2171000000>;
86			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
87			next-level-cache = <&l2_1>;
88			capacity-dmips-mhz = <1024>;
89		};
90
91		cpu5: cpu@500 {
92			device_type = "cpu";
93			compatible = "arm,cortex-a76";
94			reg = <0x500>;
95			enable-method = "psci";
96			clock-frequency = <2171000000>;
97			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
98			next-level-cache = <&l2_1>;
99			capacity-dmips-mhz = <1024>;
100		};
101
102		cpu6: cpu@600 {
103			device_type = "cpu";
104			compatible = "arm,cortex-a76";
105			reg = <0x600>;
106			enable-method = "psci";
107			clock-frequency = <2171000000>;
108			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
109			next-level-cache = <&l2_1>;
110			capacity-dmips-mhz = <1024>;
111		};
112
113		cpu7: cpu@700 {
114			device_type = "cpu";
115			compatible = "arm,cortex-a76";
116			reg = <0x700>;
117			enable-method = "psci";
118			clock-frequency = <2171000000>;
119			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
120			next-level-cache = <&l2_1>;
121			capacity-dmips-mhz = <1024>;
122		};
123
124		cpu-map {
125			cluster0 {
126				core0 {
127					cpu = <&cpu0>;
128				};
129				core1 {
130					cpu = <&cpu1>;
131				};
132				core2 {
133					cpu = <&cpu2>;
134				};
135				core3 {
136					cpu = <&cpu3>;
137				};
138			};
139
140			cluster1 {
141				core0 {
142					cpu = <&cpu4>;
143				};
144				core1 {
145					cpu = <&cpu5>;
146				};
147				core2 {
148					cpu = <&cpu6>;
149				};
150				core3 {
151					cpu = <&cpu7>;
152				};
153			};
154		};
155
156		l2_0: l2-cache0 {
157			compatible = "cache";
158			next-level-cache = <&l3_0>;
159		};
160
161		l2_1: l2-cache1 {
162			compatible = "cache";
163			next-level-cache = <&l3_0>;
164		};
165
166		l3_0: l3-cache {
167			compatible = "cache";
168		};
169
170		idle-states {
171			entry-method = "arm,psci";
172			cpuoff_l: cpuoff_l {
173				compatible = "arm,idle-state";
174				arm,psci-suspend-param = <0x00010001>;
175				local-timer-stop;
176				entry-latency-us = <55>;
177				exit-latency-us = <140>;
178				min-residency-us = <780>;
179			};
180			cpuoff_b: cpuoff_b {
181				compatible = "arm,idle-state";
182				arm,psci-suspend-param = <0x00010001>;
183				local-timer-stop;
184				entry-latency-us = <35>;
185				exit-latency-us = <145>;
186				min-residency-us = <720>;
187			};
188			clusteroff_l: clusteroff_l {
189				compatible = "arm,idle-state";
190				arm,psci-suspend-param = <0x01010002>;
191				local-timer-stop;
192				entry-latency-us = <60>;
193				exit-latency-us = <155>;
194				min-residency-us = <860>;
195			};
196			clusteroff_b: clusteroff_b {
197				compatible = "arm,idle-state";
198				arm,psci-suspend-param = <0x01010002>;
199				local-timer-stop;
200				entry-latency-us = <40>;
201				exit-latency-us = <155>;
202				min-residency-us = <780>;
203			};
204		};
205	};
206
207	pmu-a55 {
208		compatible = "arm,cortex-a55-pmu";
209		interrupt-parent = <&gic>;
210		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
211	};
212
213	pmu-a76 {
214		compatible = "arm,cortex-a76-pmu";
215		interrupt-parent = <&gic>;
216		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
217	};
218
219	psci {
220		compatible = "arm,psci-1.0";
221		method = "smc";
222	};
223
224	timer: timer {
225		compatible = "arm,armv8-timer";
226		interrupt-parent = <&gic>;
227		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
228			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
229			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
230			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
231		clock-frequency = <13000000>;
232	};
233
234	soc {
235		#address-cells = <2>;
236		#size-cells = <2>;
237		compatible = "simple-bus";
238		ranges;
239
240		gic: interrupt-controller@c000000 {
241			compatible = "arm,gic-v3";
242			#interrupt-cells = <4>;
243			#redistributor-regions = <1>;
244			interrupt-parent = <&gic>;
245			interrupt-controller;
246			reg = <0 0x0c000000 0 0x40000>,
247			      <0 0x0c040000 0 0x200000>;
248			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
249
250			ppi-partitions {
251				ppi_cluster0: interrupt-partition-0 {
252					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
253				};
254				ppi_cluster1: interrupt-partition-1 {
255					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
256				};
257			};
258		};
259
260		pio: pinctrl@10005000 {
261			compatible = "mediatek,mt8192-pinctrl";
262			reg = <0 0x10005000 0 0x1000>,
263			      <0 0x11c20000 0 0x1000>,
264			      <0 0x11d10000 0 0x1000>,
265			      <0 0x11d30000 0 0x1000>,
266			      <0 0x11d40000 0 0x1000>,
267			      <0 0x11e20000 0 0x1000>,
268			      <0 0x11e70000 0 0x1000>,
269			      <0 0x11ea0000 0 0x1000>,
270			      <0 0x11f20000 0 0x1000>,
271			      <0 0x11f30000 0 0x1000>,
272			      <0 0x1000b000 0 0x1000>;
273			reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
274				    "iocfg_bl", "iocfg_br", "iocfg_lm",
275				    "iocfg_lb", "iocfg_rt", "iocfg_lt",
276				    "iocfg_tl", "eint";
277			gpio-controller;
278			#gpio-cells = <2>;
279			gpio-ranges = <&pio 0 0 220>;
280			interrupt-controller;
281			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
282			#interrupt-cells = <2>;
283		};
284
285		systimer: timer@10017000 {
286			compatible = "mediatek,mt8192-timer",
287				     "mediatek,mt6765-timer";
288			reg = <0 0x10017000 0 0x1000>;
289			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
290			clocks = <&clk26m>;
291			clock-names = "clk13m";
292		};
293
294		uart0: serial@11002000 {
295			compatible = "mediatek,mt8192-uart",
296				     "mediatek,mt6577-uart";
297			reg = <0 0x11002000 0 0x1000>;
298			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
299			clocks = <&clk26m>, <&clk26m>;
300			clock-names = "baud", "bus";
301			status = "disabled";
302		};
303
304		uart1: serial@11003000 {
305			compatible = "mediatek,mt8192-uart",
306				     "mediatek,mt6577-uart";
307			reg = <0 0x11003000 0 0x1000>;
308			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
309			clocks = <&clk26m>, <&clk26m>;
310			clock-names = "baud", "bus";
311			status = "disabled";
312		};
313
314		spi0: spi@1100a000 {
315			compatible = "mediatek,mt8192-spi",
316				     "mediatek,mt6765-spi";
317			#address-cells = <1>;
318			#size-cells = <0>;
319			reg = <0 0x1100a000 0 0x1000>;
320			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
321			clocks = <&clk26m>,
322				 <&clk26m>,
323				 <&clk26m>;
324			clock-names = "parent-clk", "sel-clk", "spi-clk";
325			status = "disabled";
326		};
327
328		spi1: spi@11010000 {
329			compatible = "mediatek,mt8192-spi",
330				     "mediatek,mt6765-spi";
331			#address-cells = <1>;
332			#size-cells = <0>;
333			reg = <0 0x11010000 0 0x1000>;
334			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
335			clocks = <&clk26m>,
336				 <&clk26m>,
337				 <&clk26m>;
338			clock-names = "parent-clk", "sel-clk", "spi-clk";
339			status = "disabled";
340		};
341
342		spi2: spi@11012000 {
343			compatible = "mediatek,mt8192-spi",
344				     "mediatek,mt6765-spi";
345			#address-cells = <1>;
346			#size-cells = <0>;
347			reg = <0 0x11012000 0 0x1000>;
348			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
349			clocks = <&clk26m>,
350				 <&clk26m>,
351				 <&clk26m>;
352			clock-names = "parent-clk", "sel-clk", "spi-clk";
353			status = "disabled";
354		};
355
356		spi3: spi@11013000 {
357			compatible = "mediatek,mt8192-spi",
358				     "mediatek,mt6765-spi";
359			#address-cells = <1>;
360			#size-cells = <0>;
361			reg = <0 0x11013000 0 0x1000>;
362			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
363			clocks = <&clk26m>,
364				 <&clk26m>,
365				 <&clk26m>;
366			clock-names = "parent-clk", "sel-clk", "spi-clk";
367			status = "disabled";
368		};
369
370		spi4: spi@11018000 {
371			compatible = "mediatek,mt8192-spi",
372				     "mediatek,mt6765-spi";
373			#address-cells = <1>;
374			#size-cells = <0>;
375			reg = <0 0x11018000 0 0x1000>;
376			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
377			clocks = <&clk26m>,
378				 <&clk26m>,
379				 <&clk26m>;
380			clock-names = "parent-clk", "sel-clk", "spi-clk";
381			status = "disabled";
382		};
383
384		spi5: spi@11019000 {
385			compatible = "mediatek,mt8192-spi",
386				     "mediatek,mt6765-spi";
387			#address-cells = <1>;
388			#size-cells = <0>;
389			reg = <0 0x11019000 0 0x1000>;
390			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
391			clocks = <&clk26m>,
392				 <&clk26m>,
393				 <&clk26m>;
394			clock-names = "parent-clk", "sel-clk", "spi-clk";
395			status = "disabled";
396		};
397
398		spi6: spi@1101d000 {
399			compatible = "mediatek,mt8192-spi",
400				     "mediatek,mt6765-spi";
401			#address-cells = <1>;
402			#size-cells = <0>;
403			reg = <0 0x1101d000 0 0x1000>;
404			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
405			clocks = <&clk26m>,
406				 <&clk26m>,
407				 <&clk26m>;
408			clock-names = "parent-clk", "sel-clk", "spi-clk";
409			status = "disabled";
410		};
411
412		spi7: spi@1101e000 {
413			compatible = "mediatek,mt8192-spi",
414				     "mediatek,mt6765-spi";
415			#address-cells = <1>;
416			#size-cells = <0>;
417			reg = <0 0x1101e000 0 0x1000>;
418			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
419			clocks = <&clk26m>,
420				 <&clk26m>,
421				 <&clk26m>;
422			clock-names = "parent-clk", "sel-clk", "spi-clk";
423			status = "disabled";
424		};
425
426		nor_flash: spi@11234000 {
427			compatible = "mediatek,mt8192-nor";
428			reg = <0 0x11234000 0 0xe0>;
429			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
430			clocks = <&clk26m>,
431				 <&clk26m>,
432				 <&clk26m>;
433			clock-names = "spi", "sf", "axi";
434			#address-cells = <1>;
435			#size-cells = <0>;
436			status = "disable";
437		};
438
439		i2c3: i2c3@11cb0000 {
440			compatible = "mediatek,mt8192-i2c";
441			reg = <0 0x11cb0000 0 0x1000>,
442			      <0 0x10217300 0 0x80>;
443			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
444			clocks = <&clk26m>, <&clk26m>;
445			clock-names = "main", "dma";
446			clock-div = <1>;
447			#address-cells = <1>;
448			#size-cells = <0>;
449			status = "disabled";
450		};
451
452		i2c7: i2c7@11d00000 {
453			compatible = "mediatek,mt8192-i2c";
454			reg = <0 0x11d00000 0 0x1000>,
455			      <0 0x10217600 0 0x180>;
456			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
457			clocks = <&clk26m>, <&clk26m>;
458			clock-names = "main", "dma";
459			clock-div = <1>;
460			#address-cells = <1>;
461			#size-cells = <0>;
462			status = "disabled";
463		};
464
465		i2c8: i2c8@11d01000 {
466			compatible = "mediatek,mt8192-i2c";
467			reg = <0 0x11d01000 0 0x1000>,
468			      <0 0x10217780 0 0x180>;
469			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
470			clocks = <&clk26m>, <&clk26m>;
471			clock-names = "main", "dma";
472			clock-div = <1>;
473			#address-cells = <1>;
474			#size-cells = <0>;
475			status = "disabled";
476		};
477
478		i2c9: i2c9@11d02000 {
479			compatible = "mediatek,mt8192-i2c";
480			reg = <0 0x11d02000 0 0x1000>,
481			      <0 0x10217900 0 0x180>;
482			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
483			clocks = <&clk26m>, <&clk26m>;
484			clock-names = "main", "dma";
485			clock-div = <1>;
486			#address-cells = <1>;
487			#size-cells = <0>;
488			status = "disabled";
489		};
490
491		i2c1: i2c1@11d20000 {
492			compatible = "mediatek,mt8192-i2c";
493			reg = <0 0x11d20000 0 0x1000>,
494			      <0 0x10217100 0 0x80>;
495			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
496			clocks = <&clk26m>, <&clk26m>;
497			clock-names = "main", "dma";
498			clock-div = <1>;
499			#address-cells = <1>;
500			#size-cells = <0>;
501			status = "disabled";
502		};
503
504		i2c2: i2c2@11d21000 {
505			compatible = "mediatek,mt8192-i2c";
506			reg = <0 0x11d21000 0 0x1000>,
507			      <0 0x10217180 0 0x180>;
508			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
509			clocks = <&clk26m>, <&clk26m>;
510			clock-names = "main", "dma";
511			clock-div = <1>;
512			#address-cells = <1>;
513			#size-cells = <0>;
514			status = "disabled";
515		};
516
517		i2c4: i2c4@11d22000 {
518			compatible = "mediatek,mt8192-i2c";
519			reg = <0 0x11d22000 0 0x1000>,
520			      <0 0x10217380 0 0x180>;
521			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
522			clocks = <&clk26m>, <&clk26m>;
523			clock-names = "main", "dma";
524			clock-div = <1>;
525			#address-cells = <1>;
526			#size-cells = <0>;
527			status = "disabled";
528		};
529
530		i2c5: i2c5@11e00000 {
531			compatible = "mediatek,mt8192-i2c";
532			reg = <0 0x11e00000 0 0x1000>,
533			      <0 0x10217500 0 0x80>;
534			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
535			clocks = <&clk26m>, <&clk26m>;
536			clock-names = "main", "dma";
537			clock-div = <1>;
538			#address-cells = <1>;
539			#size-cells = <0>;
540			status = "disabled";
541		};
542
543		i2c0: i2c0@11f00000 {
544			compatible = "mediatek,mt8192-i2c";
545			reg = <0 0x11f00000 0 0x1000>,
546			      <0 0x10217080 0 0x80>;
547			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
548			clocks = <&clk26m>, <&clk26m>;
549			clock-names = "main", "dma";
550			clock-div = <1>;
551			#address-cells = <1>;
552			#size-cells = <0>;
553			status = "disabled";
554		};
555
556		i2c6: i2c6@11f01000 {
557			compatible = "mediatek,mt8192-i2c";
558			reg = <0 0x11f01000 0 0x1000>,
559			      <0 0x10217580 0 0x80>;
560			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
561			clocks = <&clk26m>, <&clk26m>;
562			clock-names = "main", "dma";
563			clock-div = <1>;
564			#address-cells = <1>;
565			#size-cells = <0>;
566			status = "disabled";
567		};
568	};
569};
570