1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 11#include <dt-bindings/power/mt8186-power.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/reset/mt8186-resets.h> 14 15/ { 16 compatible = "mediatek,mt8186"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 35 core2 { 36 cpu = <&cpu2>; 37 }; 38 39 core3 { 40 cpu = <&cpu3>; 41 }; 42 43 core4 { 44 cpu = <&cpu4>; 45 }; 46 47 core5 { 48 cpu = <&cpu5>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&cpu6>; 55 }; 56 57 core1 { 58 cpu = <&cpu7>; 59 }; 60 }; 61 }; 62 63 cpu0: cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a55"; 66 reg = <0x000>; 67 enable-method = "psci"; 68 clock-frequency = <2000000000>; 69 capacity-dmips-mhz = <382>; 70 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 71 next-level-cache = <&l2_0>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x100>; 79 enable-method = "psci"; 80 clock-frequency = <2000000000>; 81 capacity-dmips-mhz = <382>; 82 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 83 next-level-cache = <&l2_0>; 84 #cooling-cells = <2>; 85 }; 86 87 cpu2: cpu@200 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a55"; 90 reg = <0x200>; 91 enable-method = "psci"; 92 clock-frequency = <2000000000>; 93 capacity-dmips-mhz = <382>; 94 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 95 next-level-cache = <&l2_0>; 96 #cooling-cells = <2>; 97 }; 98 99 cpu3: cpu@300 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x300>; 103 enable-method = "psci"; 104 clock-frequency = <2000000000>; 105 capacity-dmips-mhz = <382>; 106 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 107 next-level-cache = <&l2_0>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x400>; 115 enable-method = "psci"; 116 clock-frequency = <2000000000>; 117 capacity-dmips-mhz = <382>; 118 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 119 next-level-cache = <&l2_0>; 120 #cooling-cells = <2>; 121 }; 122 123 cpu5: cpu@500 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a55"; 126 reg = <0x500>; 127 enable-method = "psci"; 128 clock-frequency = <2000000000>; 129 capacity-dmips-mhz = <382>; 130 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 131 next-level-cache = <&l2_0>; 132 #cooling-cells = <2>; 133 }; 134 135 cpu6: cpu@600 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a76"; 138 reg = <0x600>; 139 enable-method = "psci"; 140 clock-frequency = <2050000000>; 141 capacity-dmips-mhz = <1024>; 142 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 143 next-level-cache = <&l2_1>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu7: cpu@700 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a76"; 150 reg = <0x700>; 151 enable-method = "psci"; 152 clock-frequency = <2050000000>; 153 capacity-dmips-mhz = <1024>; 154 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 155 next-level-cache = <&l2_1>; 156 #cooling-cells = <2>; 157 }; 158 159 idle-states { 160 entry-method = "psci"; 161 162 cpu_off_l: cpu-off-l { 163 compatible = "arm,idle-state"; 164 arm,psci-suspend-param = <0x00010001>; 165 local-timer-stop; 166 entry-latency-us = <50>; 167 exit-latency-us = <100>; 168 min-residency-us = <1600>; 169 }; 170 171 cpu_off_b: cpu-off-b { 172 compatible = "arm,idle-state"; 173 arm,psci-suspend-param = <0x00010001>; 174 local-timer-stop; 175 entry-latency-us = <50>; 176 exit-latency-us = <100>; 177 min-residency-us = <1400>; 178 }; 179 180 cluster_off_l: cluster-off-l { 181 compatible = "arm,idle-state"; 182 arm,psci-suspend-param = <0x01010001>; 183 local-timer-stop; 184 entry-latency-us = <100>; 185 exit-latency-us = <250>; 186 min-residency-us = <2100>; 187 }; 188 189 cluster_off_b: cluster-off-b { 190 compatible = "arm,idle-state"; 191 arm,psci-suspend-param = <0x01010001>; 192 local-timer-stop; 193 entry-latency-us = <100>; 194 exit-latency-us = <250>; 195 min-residency-us = <1900>; 196 }; 197 }; 198 199 l2_0: l2-cache0 { 200 compatible = "cache"; 201 next-level-cache = <&l3_0>; 202 }; 203 204 l2_1: l2-cache1 { 205 compatible = "cache"; 206 next-level-cache = <&l3_0>; 207 }; 208 209 l3_0: l3-cache { 210 compatible = "cache"; 211 }; 212 }; 213 214 clk13m: oscillator-13m { 215 compatible = "fixed-clock"; 216 #clock-cells = <0>; 217 clock-frequency = <13000000>; 218 clock-output-names = "clk13m"; 219 }; 220 221 clk26m: oscillator-26m { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <26000000>; 225 clock-output-names = "clk26m"; 226 }; 227 228 clk32k: oscillator-32k { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <32768>; 232 clock-output-names = "clk32k"; 233 }; 234 235 pmu-a55 { 236 compatible = "arm,cortex-a55-pmu"; 237 interrupt-parent = <&gic>; 238 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 239 }; 240 241 pmu-a76 { 242 compatible = "arm,cortex-a76-pmu"; 243 interrupt-parent = <&gic>; 244 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 245 }; 246 247 psci { 248 compatible = "arm,psci-1.0"; 249 method = "smc"; 250 }; 251 252 timer { 253 compatible = "arm,armv8-timer"; 254 interrupt-parent = <&gic>; 255 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 256 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 257 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 258 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 259 }; 260 261 soc { 262 #address-cells = <2>; 263 #size-cells = <2>; 264 compatible = "simple-bus"; 265 ranges; 266 267 gic: interrupt-controller@c000000 { 268 compatible = "arm,gic-v3"; 269 #interrupt-cells = <4>; 270 #redistributor-regions = <1>; 271 interrupt-parent = <&gic>; 272 interrupt-controller; 273 reg = <0 0x0c000000 0 0x40000>, 274 <0 0x0c040000 0 0x200000>; 275 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 276 277 ppi-partitions { 278 ppi_cluster0: interrupt-partition-0 { 279 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 280 }; 281 282 ppi_cluster1: interrupt-partition-1 { 283 affinity = <&cpu6 &cpu7>; 284 }; 285 }; 286 }; 287 288 mcusys: syscon@c53a000 { 289 compatible = "mediatek,mt8186-mcusys", "syscon"; 290 reg = <0 0xc53a000 0 0x1000>; 291 #clock-cells = <1>; 292 }; 293 294 topckgen: syscon@10000000 { 295 compatible = "mediatek,mt8186-topckgen", "syscon"; 296 reg = <0 0x10000000 0 0x1000>; 297 #clock-cells = <1>; 298 }; 299 300 infracfg_ao: syscon@10001000 { 301 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 302 reg = <0 0x10001000 0 0x1000>; 303 #clock-cells = <1>; 304 #reset-cells = <1>; 305 }; 306 307 pericfg: syscon@10003000 { 308 compatible = "mediatek,mt8186-pericfg", "syscon"; 309 reg = <0 0x10003000 0 0x1000>; 310 }; 311 312 pio: pinctrl@10005000 { 313 compatible = "mediatek,mt8186-pinctrl"; 314 reg = <0 0x10005000 0 0x1000>, 315 <0 0x10002000 0 0x0200>, 316 <0 0x10002200 0 0x0200>, 317 <0 0x10002400 0 0x0200>, 318 <0 0x10002600 0 0x0200>, 319 <0 0x10002a00 0 0x0200>, 320 <0 0x10002c00 0 0x0200>, 321 <0 0x1000b000 0 0x1000>; 322 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 323 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 324 gpio-controller; 325 #gpio-cells = <2>; 326 gpio-ranges = <&pio 0 0 185>; 327 interrupt-controller; 328 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 329 #interrupt-cells = <2>; 330 }; 331 332 watchdog: watchdog@10007000 { 333 compatible = "mediatek,mt8186-wdt", 334 "mediatek,mt6589-wdt"; 335 mediatek,disable-extrst; 336 reg = <0 0x10007000 0 0x1000>; 337 #reset-cells = <1>; 338 }; 339 340 apmixedsys: syscon@1000c000 { 341 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 342 reg = <0 0x1000c000 0 0x1000>; 343 #clock-cells = <1>; 344 }; 345 346 pwrap: pwrap@1000d000 { 347 compatible = "mediatek,mt8186-pwrap", "syscon"; 348 reg = <0 0x1000d000 0 0x1000>; 349 reg-names = "pwrap"; 350 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 351 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 352 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 353 clock-names = "spi", "wrap"; 354 }; 355 356 systimer: timer@10017000 { 357 compatible = "mediatek,mt8186-timer", 358 "mediatek,mt6765-timer"; 359 reg = <0 0x10017000 0 0x1000>; 360 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 361 clocks = <&clk13m>; 362 }; 363 364 scp: scp@10500000 { 365 compatible = "mediatek,mt8186-scp"; 366 reg = <0 0x10500000 0 0x40000>, 367 <0 0x105c0000 0 0x19080>; 368 reg-names = "sram", "cfg"; 369 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 370 }; 371 372 nor_flash: spi@11000000 { 373 compatible = "mediatek,mt8186-nor"; 374 reg = <0 0x11000000 0 0x1000>; 375 clocks = <&topckgen CLK_TOP_SPINOR>, 376 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 377 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 378 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 379 clock-names = "spi", "sf", "axi", "axi_s"; 380 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 381 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 382 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 383 status = "disabled"; 384 }; 385 386 auxadc: adc@11001000 { 387 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 388 reg = <0 0x11001000 0 0x1000>; 389 #io-channel-cells = <1>; 390 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 391 clock-names = "main"; 392 }; 393 394 uart0: serial@11002000 { 395 compatible = "mediatek,mt8186-uart", 396 "mediatek,mt6577-uart"; 397 reg = <0 0x11002000 0 0x1000>; 398 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 399 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 400 clock-names = "baud", "bus"; 401 status = "disabled"; 402 }; 403 404 uart1: serial@11003000 { 405 compatible = "mediatek,mt8186-uart", 406 "mediatek,mt6577-uart"; 407 reg = <0 0x11003000 0 0x1000>; 408 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 409 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 410 clock-names = "baud", "bus"; 411 status = "disabled"; 412 }; 413 414 i2c0: i2c@11007000 { 415 compatible = "mediatek,mt8186-i2c"; 416 reg = <0 0x11007000 0 0x1000>, 417 <0 0x10200100 0 0x100>; 418 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 419 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 420 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 421 clock-names = "main", "dma"; 422 clock-div = <1>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 i2c1: i2c@11008000 { 429 compatible = "mediatek,mt8186-i2c"; 430 reg = <0 0x11008000 0 0x1000>, 431 <0 0x10200200 0 0x100>; 432 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 433 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 434 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 435 clock-names = "main", "dma"; 436 clock-div = <1>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 status = "disabled"; 440 }; 441 442 i2c2: i2c@11009000 { 443 compatible = "mediatek,mt8186-i2c"; 444 reg = <0 0x11009000 0 0x1000>, 445 <0 0x10200300 0 0x180>; 446 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 447 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 448 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 449 clock-names = "main", "dma"; 450 clock-div = <1>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 status = "disabled"; 454 }; 455 456 i2c3: i2c@1100f000 { 457 compatible = "mediatek,mt8186-i2c"; 458 reg = <0 0x1100f000 0 0x1000>, 459 <0 0x10200480 0 0x100>; 460 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 461 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 462 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 463 clock-names = "main", "dma"; 464 clock-div = <1>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 status = "disabled"; 468 }; 469 470 i2c4: i2c@11011000 { 471 compatible = "mediatek,mt8186-i2c"; 472 reg = <0 0x11011000 0 0x1000>, 473 <0 0x10200580 0 0x180>; 474 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 475 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 476 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 477 clock-names = "main", "dma"; 478 clock-div = <1>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 status = "disabled"; 482 }; 483 484 i2c5: i2c@11016000 { 485 compatible = "mediatek,mt8186-i2c"; 486 reg = <0 0x11016000 0 0x1000>, 487 <0 0x10200700 0 0x100>; 488 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 489 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 490 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 491 clock-names = "main", "dma"; 492 clock-div = <1>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 status = "disabled"; 496 }; 497 498 i2c6: i2c@1100d000 { 499 compatible = "mediatek,mt8186-i2c"; 500 reg = <0 0x1100d000 0 0x1000>, 501 <0 0x10200800 0 0x100>; 502 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 503 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 504 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 505 clock-names = "main", "dma"; 506 clock-div = <1>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 status = "disabled"; 510 }; 511 512 i2c7: i2c@11004000 { 513 compatible = "mediatek,mt8186-i2c"; 514 reg = <0 0x11004000 0 0x1000>, 515 <0 0x10200900 0 0x180>; 516 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 517 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 518 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 519 clock-names = "main", "dma"; 520 clock-div = <1>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 status = "disabled"; 524 }; 525 526 i2c8: i2c@11005000 { 527 compatible = "mediatek,mt8186-i2c"; 528 reg = <0 0x11005000 0 0x1000>, 529 <0 0x10200A80 0 0x180>; 530 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 531 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 532 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 533 clock-names = "main", "dma"; 534 clock-div = <1>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 spi0: spi@1100a000 { 541 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 reg = <0 0x1100a000 0 0x1000>; 545 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 546 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 547 <&topckgen CLK_TOP_SPI>, 548 <&infracfg_ao CLK_INFRA_AO_SPI0>; 549 clock-names = "parent-clk", "sel-clk", "spi-clk"; 550 status = "disabled"; 551 }; 552 553 pwm0: pwm@1100e000 { 554 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 555 reg = <0 0x1100e000 0 0x1000>; 556 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 557 #pwm-cells = <2>; 558 clocks = <&topckgen CLK_TOP_DISP_PWM>, 559 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 560 clock-names = "main", "mm"; 561 status = "disabled"; 562 }; 563 564 spi1: spi@11010000 { 565 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 reg = <0 0x11010000 0 0x1000>; 569 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 570 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 571 <&topckgen CLK_TOP_SPI>, 572 <&infracfg_ao CLK_INFRA_AO_SPI1>; 573 clock-names = "parent-clk", "sel-clk", "spi-clk"; 574 status = "disabled"; 575 }; 576 577 spi2: spi@11012000 { 578 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 reg = <0 0x11012000 0 0x1000>; 582 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 583 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 584 <&topckgen CLK_TOP_SPI>, 585 <&infracfg_ao CLK_INFRA_AO_SPI2>; 586 clock-names = "parent-clk", "sel-clk", "spi-clk"; 587 status = "disabled"; 588 }; 589 590 spi3: spi@11013000 { 591 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 reg = <0 0x11013000 0 0x1000>; 595 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 596 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 597 <&topckgen CLK_TOP_SPI>, 598 <&infracfg_ao CLK_INFRA_AO_SPI3>; 599 clock-names = "parent-clk", "sel-clk", "spi-clk"; 600 status = "disabled"; 601 }; 602 603 spi4: spi@11014000 { 604 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 reg = <0 0x11014000 0 0x1000>; 608 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 609 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 610 <&topckgen CLK_TOP_SPI>, 611 <&infracfg_ao CLK_INFRA_AO_SPI4>; 612 clock-names = "parent-clk", "sel-clk", "spi-clk"; 613 status = "disabled"; 614 }; 615 616 spi5: spi@11015000 { 617 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 reg = <0 0x11015000 0 0x1000>; 621 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 622 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 623 <&topckgen CLK_TOP_SPI>, 624 <&infracfg_ao CLK_INFRA_AO_SPI5>; 625 clock-names = "parent-clk", "sel-clk", "spi-clk"; 626 status = "disabled"; 627 }; 628 629 imp_iic_wrap: clock-controller@11017000 { 630 compatible = "mediatek,mt8186-imp_iic_wrap"; 631 reg = <0 0x11017000 0 0x1000>; 632 #clock-cells = <1>; 633 }; 634 635 uart2: serial@11018000 { 636 compatible = "mediatek,mt8186-uart", 637 "mediatek,mt6577-uart"; 638 reg = <0 0x11018000 0 0x1000>; 639 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 640 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 641 clock-names = "baud", "bus"; 642 status = "disabled"; 643 }; 644 645 i2c9: i2c@11019000 { 646 compatible = "mediatek,mt8186-i2c"; 647 reg = <0 0x11019000 0 0x1000>, 648 <0 0x10200c00 0 0x180>; 649 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 650 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 651 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 652 clock-names = "main", "dma"; 653 clock-div = <1>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 status = "disabled"; 657 }; 658 659 mmc0: mmc@11230000 { 660 compatible = "mediatek,mt8186-mmc", 661 "mediatek,mt8183-mmc"; 662 reg = <0 0x11230000 0 0x1000>, 663 <0 0x11cd0000 0 0x1000>; 664 clocks = <&topckgen CLK_TOP_MSDC50_0>, 665 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 666 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 667 clock-names = "source", "hclk", "source_cg"; 668 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 669 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 670 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 671 status = "disabled"; 672 }; 673 674 mmc1: mmc@11240000 { 675 compatible = "mediatek,mt8186-mmc", 676 "mediatek,mt8183-mmc"; 677 reg = <0 0x11240000 0 0x1000>, 678 <0 0x11c90000 0 0x1000>; 679 clocks = <&topckgen CLK_TOP_MSDC30_1>, 680 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 681 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 682 clock-names = "source", "hclk", "source_cg"; 683 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 684 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 685 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 686 status = "disabled"; 687 }; 688 689 u3phy0: t-phy@11c80000 { 690 compatible = "mediatek,mt8186-tphy", 691 "mediatek,generic-tphy-v2"; 692 #address-cells = <1>; 693 #size-cells = <1>; 694 ranges = <0x0 0x0 0x11c80000 0x1000>; 695 status = "disabled"; 696 697 u2port1: usb-phy@0 { 698 reg = <0x0 0x700>; 699 clocks = <&clk26m>; 700 clock-names = "ref"; 701 #phy-cells = <1>; 702 }; 703 704 u3port1: usb-phy@700 { 705 reg = <0x700 0x900>; 706 clocks = <&clk26m>; 707 clock-names = "ref"; 708 #phy-cells = <1>; 709 }; 710 }; 711 712 u3phy1: t-phy@11ca0000 { 713 compatible = "mediatek,mt8186-tphy", 714 "mediatek,generic-tphy-v2"; 715 #address-cells = <1>; 716 #size-cells = <1>; 717 ranges = <0x0 0x0 0x11ca0000 0x1000>; 718 status = "disabled"; 719 720 u2port0: usb-phy@0 { 721 reg = <0x0 0x700>; 722 clocks = <&clk26m>; 723 clock-names = "ref"; 724 #phy-cells = <1>; 725 mediatek,discth = <0x8>; 726 }; 727 }; 728 729 efuse: efuse@11cb0000 { 730 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 731 reg = <0 0x11cb0000 0 0x1000>; 732 #address-cells = <1>; 733 #size-cells = <1>; 734 }; 735 736 mipi_tx0: dsi-phy@11cc0000 { 737 compatible = "mediatek,mt8183-mipi-tx"; 738 reg = <0 0x11cc0000 0 0x1000>; 739 clocks = <&clk26m>; 740 #clock-cells = <0>; 741 #phy-cells = <0>; 742 clock-output-names = "mipi_tx0_pll"; 743 status = "disabled"; 744 }; 745 746 mfgsys: clock-controller@13000000 { 747 compatible = "mediatek,mt8186-mfgsys"; 748 reg = <0 0x13000000 0 0x1000>; 749 #clock-cells = <1>; 750 }; 751 752 mmsys: syscon@14000000 { 753 compatible = "mediatek,mt8186-mmsys", "syscon"; 754 reg = <0 0x14000000 0 0x1000>; 755 #clock-cells = <1>; 756 #reset-cells = <1>; 757 }; 758 759 wpesys: clock-controller@14020000 { 760 compatible = "mediatek,mt8186-wpesys"; 761 reg = <0 0x14020000 0 0x1000>; 762 #clock-cells = <1>; 763 }; 764 765 imgsys1: clock-controller@15020000 { 766 compatible = "mediatek,mt8186-imgsys1"; 767 reg = <0 0x15020000 0 0x1000>; 768 #clock-cells = <1>; 769 }; 770 771 imgsys2: clock-controller@15820000 { 772 compatible = "mediatek,mt8186-imgsys2"; 773 reg = <0 0x15820000 0 0x1000>; 774 #clock-cells = <1>; 775 }; 776 777 vdecsys: clock-controller@1602f000 { 778 compatible = "mediatek,mt8186-vdecsys"; 779 reg = <0 0x1602f000 0 0x1000>; 780 #clock-cells = <1>; 781 }; 782 783 vencsys: clock-controller@17000000 { 784 compatible = "mediatek,mt8186-vencsys"; 785 reg = <0 0x17000000 0 0x1000>; 786 #clock-cells = <1>; 787 }; 788 789 camsys: clock-controller@1a000000 { 790 compatible = "mediatek,mt8186-camsys"; 791 reg = <0 0x1a000000 0 0x1000>; 792 #clock-cells = <1>; 793 }; 794 795 camsys_rawa: clock-controller@1a04f000 { 796 compatible = "mediatek,mt8186-camsys_rawa"; 797 reg = <0 0x1a04f000 0 0x1000>; 798 #clock-cells = <1>; 799 }; 800 801 camsys_rawb: clock-controller@1a06f000 { 802 compatible = "mediatek,mt8186-camsys_rawb"; 803 reg = <0 0x1a06f000 0 0x1000>; 804 #clock-cells = <1>; 805 }; 806 807 mdpsys: clock-controller@1b000000 { 808 compatible = "mediatek,mt8186-mdpsys"; 809 reg = <0 0x1b000000 0 0x1000>; 810 #clock-cells = <1>; 811 }; 812 813 ipesys: clock-controller@1c000000 { 814 compatible = "mediatek,mt8186-ipesys"; 815 reg = <0 0x1c000000 0 0x1000>; 816 #clock-cells = <1>; 817 }; 818 }; 819}; 820