1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/gce/mt8186-gce.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8186-memory-port.h> 12#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13#include <dt-bindings/power/mt8186-power.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/reset/mt8186-resets.h> 16 17/ { 18 compatible = "mediatek,mt8186"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ovl0 = &ovl0; 25 ovl-2l0 = &ovl_2l0; 26 rdma0 = &rdma0; 27 rdma1 = &rdma1; 28 }; 29 30 cci: cci { 31 compatible = "mediatek,mt8186-cci"; 32 clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, 33 <&apmixedsys CLK_APMIXED_MAINPLL>; 34 clock-names = "cci", "intermediate"; 35 operating-points-v2 = <&cci_opp>; 36 }; 37 38 cci_opp: opp-table-cci { 39 compatible = "operating-points-v2"; 40 opp-shared; 41 42 cci_opp_0: opp-500000000 { 43 opp-hz = /bits/ 64 <500000000>; 44 opp-microvolt = <600000>; 45 }; 46 47 cci_opp_1: opp-560000000 { 48 opp-hz = /bits/ 64 <560000000>; 49 opp-microvolt = <675000>; 50 }; 51 52 cci_opp_2: opp-612000000 { 53 opp-hz = /bits/ 64 <612000000>; 54 opp-microvolt = <693750>; 55 }; 56 57 cci_opp_3: opp-682000000 { 58 opp-hz = /bits/ 64 <682000000>; 59 opp-microvolt = <718750>; 60 }; 61 62 cci_opp_4: opp-752000000 { 63 opp-hz = /bits/ 64 <752000000>; 64 opp-microvolt = <743750>; 65 }; 66 67 cci_opp_5: opp-822000000 { 68 opp-hz = /bits/ 64 <822000000>; 69 opp-microvolt = <768750>; 70 }; 71 72 cci_opp_6: opp-875000000 { 73 opp-hz = /bits/ 64 <875000000>; 74 opp-microvolt = <781250>; 75 }; 76 77 cci_opp_7: opp-927000000 { 78 opp-hz = /bits/ 64 <927000000>; 79 opp-microvolt = <800000>; 80 }; 81 82 cci_opp_8: opp-980000000 { 83 opp-hz = /bits/ 64 <980000000>; 84 opp-microvolt = <818750>; 85 }; 86 87 cci_opp_9: opp-1050000000 { 88 opp-hz = /bits/ 64 <1050000000>; 89 opp-microvolt = <843750>; 90 }; 91 92 cci_opp_10: opp-1120000000 { 93 opp-hz = /bits/ 64 <1120000000>; 94 opp-microvolt = <862500>; 95 }; 96 97 cci_opp_11: opp-1155000000 { 98 opp-hz = /bits/ 64 <1155000000>; 99 opp-microvolt = <887500>; 100 }; 101 102 cci_opp_12: opp-1190000000 { 103 opp-hz = /bits/ 64 <1190000000>; 104 opp-microvolt = <906250>; 105 }; 106 107 cci_opp_13: opp-1260000000 { 108 opp-hz = /bits/ 64 <1260000000>; 109 opp-microvolt = <950000>; 110 }; 111 112 cci_opp_14: opp-1330000000 { 113 opp-hz = /bits/ 64 <1330000000>; 114 opp-microvolt = <993750>; 115 }; 116 117 cci_opp_15: opp-1400000000 { 118 opp-hz = /bits/ 64 <1400000000>; 119 opp-microvolt = <1031250>; 120 }; 121 }; 122 123 cluster0_opp: opp-table-cluster0 { 124 compatible = "operating-points-v2"; 125 opp-shared; 126 127 opp-500000000 { 128 opp-hz = /bits/ 64 <500000000>; 129 opp-microvolt = <600000>; 130 required-opps = <&cci_opp_0>; 131 }; 132 133 opp-774000000 { 134 opp-hz = /bits/ 64 <774000000>; 135 opp-microvolt = <675000>; 136 required-opps = <&cci_opp_1>; 137 }; 138 139 opp-875000000 { 140 opp-hz = /bits/ 64 <875000000>; 141 opp-microvolt = <700000>; 142 required-opps = <&cci_opp_2>; 143 }; 144 145 opp-975000000 { 146 opp-hz = /bits/ 64 <975000000>; 147 opp-microvolt = <725000>; 148 required-opps = <&cci_opp_3>; 149 }; 150 151 opp-1075000000 { 152 opp-hz = /bits/ 64 <1075000000>; 153 opp-microvolt = <750000>; 154 required-opps = <&cci_opp_4>; 155 }; 156 157 opp-1175000000 { 158 opp-hz = /bits/ 64 <1175000000>; 159 opp-microvolt = <775000>; 160 required-opps = <&cci_opp_5>; 161 }; 162 163 opp-1275000000 { 164 opp-hz = /bits/ 64 <1275000000>; 165 opp-microvolt = <800000>; 166 required-opps = <&cci_opp_6>; 167 }; 168 169 opp-1375000000 { 170 opp-hz = /bits/ 64 <1375000000>; 171 opp-microvolt = <825000>; 172 required-opps = <&cci_opp_7>; 173 }; 174 175 opp-1500000000 { 176 opp-hz = /bits/ 64 <1500000000>; 177 opp-microvolt = <856250>; 178 required-opps = <&cci_opp_8>; 179 }; 180 181 opp-1618000000 { 182 opp-hz = /bits/ 64 <1618000000>; 183 opp-microvolt = <875000>; 184 required-opps = <&cci_opp_9>; 185 }; 186 187 opp-1666000000 { 188 opp-hz = /bits/ 64 <1666000000>; 189 opp-microvolt = <900000>; 190 required-opps = <&cci_opp_10>; 191 }; 192 193 opp-1733000000 { 194 opp-hz = /bits/ 64 <1733000000>; 195 opp-microvolt = <925000>; 196 required-opps = <&cci_opp_11>; 197 }; 198 199 opp-1800000000 { 200 opp-hz = /bits/ 64 <1800000000>; 201 opp-microvolt = <950000>; 202 required-opps = <&cci_opp_12>; 203 }; 204 205 opp-1866000000 { 206 opp-hz = /bits/ 64 <1866000000>; 207 opp-microvolt = <981250>; 208 required-opps = <&cci_opp_13>; 209 }; 210 211 opp-1933000000 { 212 opp-hz = /bits/ 64 <1933000000>; 213 opp-microvolt = <1006250>; 214 required-opps = <&cci_opp_14>; 215 }; 216 217 opp-2000000000 { 218 opp-hz = /bits/ 64 <2000000000>; 219 opp-microvolt = <1031250>; 220 required-opps = <&cci_opp_15>; 221 }; 222 }; 223 224 cluster1_opp: opp-table-cluster1 { 225 compatible = "operating-points-v2"; 226 opp-shared; 227 228 opp-774000000 { 229 opp-hz = /bits/ 64 <774000000>; 230 opp-microvolt = <675000>; 231 required-opps = <&cci_opp_0>; 232 }; 233 234 opp-835000000 { 235 opp-hz = /bits/ 64 <835000000>; 236 opp-microvolt = <693750>; 237 required-opps = <&cci_opp_1>; 238 }; 239 240 opp-919000000 { 241 opp-hz = /bits/ 64 <919000000>; 242 opp-microvolt = <718750>; 243 required-opps = <&cci_opp_2>; 244 }; 245 246 opp-1002000000 { 247 opp-hz = /bits/ 64 <1002000000>; 248 opp-microvolt = <743750>; 249 required-opps = <&cci_opp_3>; 250 }; 251 252 opp-1085000000 { 253 opp-hz = /bits/ 64 <1085000000>; 254 opp-microvolt = <775000>; 255 required-opps = <&cci_opp_4>; 256 }; 257 258 opp-1169000000 { 259 opp-hz = /bits/ 64 <1169000000>; 260 opp-microvolt = <800000>; 261 required-opps = <&cci_opp_5>; 262 }; 263 264 opp-1308000000 { 265 opp-hz = /bits/ 64 <1308000000>; 266 opp-microvolt = <843750>; 267 required-opps = <&cci_opp_6>; 268 }; 269 270 opp-1419000000 { 271 opp-hz = /bits/ 64 <1419000000>; 272 opp-microvolt = <875000>; 273 required-opps = <&cci_opp_7>; 274 }; 275 276 opp-1530000000 { 277 opp-hz = /bits/ 64 <1530000000>; 278 opp-microvolt = <912500>; 279 required-opps = <&cci_opp_8>; 280 }; 281 282 opp-1670000000 { 283 opp-hz = /bits/ 64 <1670000000>; 284 opp-microvolt = <956250>; 285 required-opps = <&cci_opp_9>; 286 }; 287 288 opp-1733000000 { 289 opp-hz = /bits/ 64 <1733000000>; 290 opp-microvolt = <981250>; 291 required-opps = <&cci_opp_10>; 292 }; 293 294 opp-1796000000 { 295 opp-hz = /bits/ 64 <1796000000>; 296 opp-microvolt = <1012500>; 297 required-opps = <&cci_opp_11>; 298 }; 299 300 opp-1860000000 { 301 opp-hz = /bits/ 64 <1860000000>; 302 opp-microvolt = <1037500>; 303 required-opps = <&cci_opp_12>; 304 }; 305 306 opp-1923000000 { 307 opp-hz = /bits/ 64 <1923000000>; 308 opp-microvolt = <1062500>; 309 required-opps = <&cci_opp_13>; 310 }; 311 312 cluster1_opp_14: opp-1986000000 { 313 opp-hz = /bits/ 64 <1986000000>; 314 opp-microvolt = <1093750>; 315 required-opps = <&cci_opp_14>; 316 }; 317 318 cluster1_opp_15: opp-2050000000 { 319 opp-hz = /bits/ 64 <2050000000>; 320 opp-microvolt = <1118750>; 321 required-opps = <&cci_opp_15>; 322 }; 323 }; 324 325 cpus { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 329 cpu-map { 330 cluster0 { 331 core0 { 332 cpu = <&cpu0>; 333 }; 334 335 core1 { 336 cpu = <&cpu1>; 337 }; 338 339 core2 { 340 cpu = <&cpu2>; 341 }; 342 343 core3 { 344 cpu = <&cpu3>; 345 }; 346 347 core4 { 348 cpu = <&cpu4>; 349 }; 350 351 core5 { 352 cpu = <&cpu5>; 353 }; 354 355 core6 { 356 cpu = <&cpu6>; 357 }; 358 359 core7 { 360 cpu = <&cpu7>; 361 }; 362 }; 363 }; 364 365 cpu0: cpu@0 { 366 device_type = "cpu"; 367 compatible = "arm,cortex-a55"; 368 reg = <0x000>; 369 enable-method = "psci"; 370 clock-frequency = <2000000000>; 371 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 372 <&apmixedsys CLK_APMIXED_MAINPLL>; 373 clock-names = "cpu", "intermediate"; 374 operating-points-v2 = <&cluster0_opp>; 375 dynamic-power-coefficient = <84>; 376 capacity-dmips-mhz = <382>; 377 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 378 i-cache-size = <32768>; 379 i-cache-line-size = <64>; 380 i-cache-sets = <128>; 381 d-cache-size = <32768>; 382 d-cache-line-size = <64>; 383 d-cache-sets = <128>; 384 next-level-cache = <&l2_0>; 385 #cooling-cells = <2>; 386 mediatek,cci = <&cci>; 387 }; 388 389 cpu1: cpu@100 { 390 device_type = "cpu"; 391 compatible = "arm,cortex-a55"; 392 reg = <0x100>; 393 enable-method = "psci"; 394 clock-frequency = <2000000000>; 395 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 396 <&apmixedsys CLK_APMIXED_MAINPLL>; 397 clock-names = "cpu", "intermediate"; 398 operating-points-v2 = <&cluster0_opp>; 399 dynamic-power-coefficient = <84>; 400 capacity-dmips-mhz = <382>; 401 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 402 i-cache-size = <32768>; 403 i-cache-line-size = <64>; 404 i-cache-sets = <128>; 405 d-cache-size = <32768>; 406 d-cache-line-size = <64>; 407 d-cache-sets = <128>; 408 next-level-cache = <&l2_0>; 409 #cooling-cells = <2>; 410 mediatek,cci = <&cci>; 411 }; 412 413 cpu2: cpu@200 { 414 device_type = "cpu"; 415 compatible = "arm,cortex-a55"; 416 reg = <0x200>; 417 enable-method = "psci"; 418 clock-frequency = <2000000000>; 419 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 420 <&apmixedsys CLK_APMIXED_MAINPLL>; 421 clock-names = "cpu", "intermediate"; 422 operating-points-v2 = <&cluster0_opp>; 423 dynamic-power-coefficient = <84>; 424 capacity-dmips-mhz = <382>; 425 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 426 i-cache-size = <32768>; 427 i-cache-line-size = <64>; 428 i-cache-sets = <128>; 429 d-cache-size = <32768>; 430 d-cache-line-size = <64>; 431 d-cache-sets = <128>; 432 next-level-cache = <&l2_0>; 433 #cooling-cells = <2>; 434 mediatek,cci = <&cci>; 435 }; 436 437 cpu3: cpu@300 { 438 device_type = "cpu"; 439 compatible = "arm,cortex-a55"; 440 reg = <0x300>; 441 enable-method = "psci"; 442 clock-frequency = <2000000000>; 443 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 444 <&apmixedsys CLK_APMIXED_MAINPLL>; 445 clock-names = "cpu", "intermediate"; 446 operating-points-v2 = <&cluster0_opp>; 447 dynamic-power-coefficient = <84>; 448 capacity-dmips-mhz = <382>; 449 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 450 i-cache-size = <32768>; 451 i-cache-line-size = <64>; 452 i-cache-sets = <128>; 453 d-cache-size = <32768>; 454 d-cache-line-size = <64>; 455 d-cache-sets = <128>; 456 next-level-cache = <&l2_0>; 457 #cooling-cells = <2>; 458 mediatek,cci = <&cci>; 459 }; 460 461 cpu4: cpu@400 { 462 device_type = "cpu"; 463 compatible = "arm,cortex-a55"; 464 reg = <0x400>; 465 enable-method = "psci"; 466 clock-frequency = <2000000000>; 467 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 468 <&apmixedsys CLK_APMIXED_MAINPLL>; 469 clock-names = "cpu", "intermediate"; 470 operating-points-v2 = <&cluster0_opp>; 471 dynamic-power-coefficient = <84>; 472 capacity-dmips-mhz = <382>; 473 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 474 i-cache-size = <32768>; 475 i-cache-line-size = <64>; 476 i-cache-sets = <128>; 477 d-cache-size = <32768>; 478 d-cache-line-size = <64>; 479 d-cache-sets = <128>; 480 next-level-cache = <&l2_0>; 481 #cooling-cells = <2>; 482 mediatek,cci = <&cci>; 483 }; 484 485 cpu5: cpu@500 { 486 device_type = "cpu"; 487 compatible = "arm,cortex-a55"; 488 reg = <0x500>; 489 enable-method = "psci"; 490 clock-frequency = <2000000000>; 491 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 492 <&apmixedsys CLK_APMIXED_MAINPLL>; 493 clock-names = "cpu", "intermediate"; 494 operating-points-v2 = <&cluster0_opp>; 495 dynamic-power-coefficient = <84>; 496 capacity-dmips-mhz = <382>; 497 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 498 i-cache-size = <32768>; 499 i-cache-line-size = <64>; 500 i-cache-sets = <128>; 501 d-cache-size = <32768>; 502 d-cache-line-size = <64>; 503 d-cache-sets = <128>; 504 next-level-cache = <&l2_0>; 505 #cooling-cells = <2>; 506 mediatek,cci = <&cci>; 507 }; 508 509 cpu6: cpu@600 { 510 device_type = "cpu"; 511 compatible = "arm,cortex-a76"; 512 reg = <0x600>; 513 enable-method = "psci"; 514 clock-frequency = <2050000000>; 515 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 516 <&apmixedsys CLK_APMIXED_MAINPLL>; 517 clock-names = "cpu", "intermediate"; 518 operating-points-v2 = <&cluster1_opp>; 519 dynamic-power-coefficient = <335>; 520 capacity-dmips-mhz = <1024>; 521 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 522 i-cache-size = <65536>; 523 i-cache-line-size = <64>; 524 i-cache-sets = <256>; 525 d-cache-size = <65536>; 526 d-cache-line-size = <64>; 527 d-cache-sets = <256>; 528 next-level-cache = <&l2_1>; 529 #cooling-cells = <2>; 530 mediatek,cci = <&cci>; 531 }; 532 533 cpu7: cpu@700 { 534 device_type = "cpu"; 535 compatible = "arm,cortex-a76"; 536 reg = <0x700>; 537 enable-method = "psci"; 538 clock-frequency = <2050000000>; 539 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 540 <&apmixedsys CLK_APMIXED_MAINPLL>; 541 clock-names = "cpu", "intermediate"; 542 operating-points-v2 = <&cluster1_opp>; 543 dynamic-power-coefficient = <335>; 544 capacity-dmips-mhz = <1024>; 545 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 546 i-cache-size = <65536>; 547 i-cache-line-size = <64>; 548 i-cache-sets = <256>; 549 d-cache-size = <65536>; 550 d-cache-line-size = <64>; 551 d-cache-sets = <256>; 552 next-level-cache = <&l2_1>; 553 #cooling-cells = <2>; 554 mediatek,cci = <&cci>; 555 }; 556 557 idle-states { 558 entry-method = "psci"; 559 560 cpu_ret_l: cpu-retention-l { 561 compatible = "arm,idle-state"; 562 arm,psci-suspend-param = <0x00010001>; 563 local-timer-stop; 564 entry-latency-us = <50>; 565 exit-latency-us = <100>; 566 min-residency-us = <1600>; 567 }; 568 569 cpu_ret_b: cpu-retention-b { 570 compatible = "arm,idle-state"; 571 arm,psci-suspend-param = <0x00010001>; 572 local-timer-stop; 573 entry-latency-us = <50>; 574 exit-latency-us = <100>; 575 min-residency-us = <1400>; 576 }; 577 578 cpu_off_l: cpu-off-l { 579 compatible = "arm,idle-state"; 580 arm,psci-suspend-param = <0x01010001>; 581 local-timer-stop; 582 entry-latency-us = <100>; 583 exit-latency-us = <250>; 584 min-residency-us = <2100>; 585 }; 586 587 cpu_off_b: cpu-off-b { 588 compatible = "arm,idle-state"; 589 arm,psci-suspend-param = <0x01010001>; 590 local-timer-stop; 591 entry-latency-us = <100>; 592 exit-latency-us = <250>; 593 min-residency-us = <1900>; 594 }; 595 }; 596 597 l2_0: l2-cache0 { 598 compatible = "cache"; 599 cache-level = <2>; 600 cache-size = <131072>; 601 cache-line-size = <64>; 602 cache-sets = <512>; 603 next-level-cache = <&l3_0>; 604 cache-unified; 605 }; 606 607 l2_1: l2-cache1 { 608 compatible = "cache"; 609 cache-level = <2>; 610 cache-size = <262144>; 611 cache-line-size = <64>; 612 cache-sets = <512>; 613 next-level-cache = <&l3_0>; 614 cache-unified; 615 }; 616 617 l3_0: l3-cache { 618 compatible = "cache"; 619 cache-level = <3>; 620 cache-size = <1048576>; 621 cache-line-size = <64>; 622 cache-sets = <1024>; 623 cache-unified; 624 }; 625 }; 626 627 clk13m: fixed-factor-clock-13m { 628 compatible = "fixed-factor-clock"; 629 #clock-cells = <0>; 630 clocks = <&clk26m>; 631 clock-div = <2>; 632 clock-mult = <1>; 633 clock-output-names = "clk13m"; 634 }; 635 636 clk26m: oscillator-26m { 637 compatible = "fixed-clock"; 638 #clock-cells = <0>; 639 clock-frequency = <26000000>; 640 clock-output-names = "clk26m"; 641 }; 642 643 clk32k: oscillator-32k { 644 compatible = "fixed-clock"; 645 #clock-cells = <0>; 646 clock-frequency = <32768>; 647 clock-output-names = "clk32k"; 648 }; 649 650 gpu_opp_table: opp-table-gpu { 651 compatible = "operating-points-v2"; 652 653 opp-299000000 { 654 opp-hz = /bits/ 64 <299000000>; 655 opp-microvolt = <612500>; 656 opp-supported-hw = <0xff>; 657 }; 658 659 opp-332000000 { 660 opp-hz = /bits/ 64 <332000000>; 661 opp-microvolt = <625000>; 662 opp-supported-hw = <0xff>; 663 }; 664 665 opp-366000000 { 666 opp-hz = /bits/ 64 <366000000>; 667 opp-microvolt = <637500>; 668 opp-supported-hw = <0xff>; 669 }; 670 671 opp-400000000 { 672 opp-hz = /bits/ 64 <400000000>; 673 opp-microvolt = <643750>; 674 opp-supported-hw = <0xff>; 675 }; 676 677 opp-434000000 { 678 opp-hz = /bits/ 64 <434000000>; 679 opp-microvolt = <656250>; 680 opp-supported-hw = <0xff>; 681 }; 682 683 opp-484000000 { 684 opp-hz = /bits/ 64 <484000000>; 685 opp-microvolt = <668750>; 686 opp-supported-hw = <0xff>; 687 }; 688 689 opp-535000000 { 690 opp-hz = /bits/ 64 <535000000>; 691 opp-microvolt = <687500>; 692 opp-supported-hw = <0xff>; 693 }; 694 695 opp-586000000 { 696 opp-hz = /bits/ 64 <586000000>; 697 opp-microvolt = <700000>; 698 opp-supported-hw = <0xff>; 699 }; 700 701 opp-637000000 { 702 opp-hz = /bits/ 64 <637000000>; 703 opp-microvolt = <712500>; 704 opp-supported-hw = <0xff>; 705 }; 706 707 opp-690000000 { 708 opp-hz = /bits/ 64 <690000000>; 709 opp-microvolt = <737500>; 710 opp-supported-hw = <0xff>; 711 }; 712 713 opp-743000000 { 714 opp-hz = /bits/ 64 <743000000>; 715 opp-microvolt = <756250>; 716 opp-supported-hw = <0xff>; 717 }; 718 719 opp-796000000 { 720 opp-hz = /bits/ 64 <796000000>; 721 opp-microvolt = <781250>; 722 opp-supported-hw = <0xff>; 723 }; 724 725 opp-850000000 { 726 opp-hz = /bits/ 64 <850000000>; 727 opp-microvolt = <800000>; 728 opp-supported-hw = <0xff>; 729 }; 730 731 opp-900000000-3 { 732 opp-hz = /bits/ 64 <900000000>; 733 opp-microvolt = <850000>; 734 opp-supported-hw = <0xcf>; 735 }; 736 737 opp-900000000-4 { 738 opp-hz = /bits/ 64 <900000000>; 739 opp-microvolt = <837500>; 740 opp-supported-hw = <0x10>; 741 }; 742 743 opp-900000000-5 { 744 opp-hz = /bits/ 64 <900000000>; 745 opp-microvolt = <825000>; 746 opp-supported-hw = <0x20>; 747 }; 748 749 opp-950000000-3 { 750 opp-hz = /bits/ 64 <950000000>; 751 opp-microvolt = <900000>; 752 opp-supported-hw = <0xcf>; 753 }; 754 755 opp-950000000-4 { 756 opp-hz = /bits/ 64 <950000000>; 757 opp-microvolt = <875000>; 758 opp-supported-hw = <0x10>; 759 }; 760 761 opp-950000000-5 { 762 opp-hz = /bits/ 64 <950000000>; 763 opp-microvolt = <850000>; 764 opp-supported-hw = <0x20>; 765 }; 766 767 opp-1000000000-3 { 768 opp-hz = /bits/ 64 <1000000000>; 769 opp-microvolt = <950000>; 770 opp-supported-hw = <0xcf>; 771 }; 772 773 opp-1000000000-4 { 774 opp-hz = /bits/ 64 <1000000000>; 775 opp-microvolt = <912500>; 776 opp-supported-hw = <0x10>; 777 }; 778 779 opp-1000000000-5 { 780 opp-hz = /bits/ 64 <1000000000>; 781 opp-microvolt = <875000>; 782 opp-supported-hw = <0x20>; 783 }; 784 }; 785 786 pmu-a55 { 787 compatible = "arm,cortex-a55-pmu"; 788 interrupt-parent = <&gic>; 789 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 790 }; 791 792 pmu-a76 { 793 compatible = "arm,cortex-a76-pmu"; 794 interrupt-parent = <&gic>; 795 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 796 }; 797 798 psci { 799 compatible = "arm,psci-1.0"; 800 method = "smc"; 801 }; 802 803 timer { 804 compatible = "arm,armv8-timer"; 805 interrupt-parent = <&gic>; 806 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 807 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 808 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 809 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 810 }; 811 812 soc { 813 #address-cells = <2>; 814 #size-cells = <2>; 815 compatible = "simple-bus"; 816 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 817 ranges; 818 819 gic: interrupt-controller@c000000 { 820 compatible = "arm,gic-v3"; 821 #interrupt-cells = <4>; 822 #redistributor-regions = <1>; 823 interrupt-parent = <&gic>; 824 interrupt-controller; 825 reg = <0 0x0c000000 0 0x40000>, 826 <0 0x0c040000 0 0x200000>; 827 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 828 829 ppi-partitions { 830 ppi_cluster0: interrupt-partition-0 { 831 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 832 }; 833 834 ppi_cluster1: interrupt-partition-1 { 835 affinity = <&cpu6 &cpu7>; 836 }; 837 }; 838 }; 839 840 mcusys: syscon@c53a000 { 841 compatible = "mediatek,mt8186-mcusys", "syscon"; 842 reg = <0 0xc53a000 0 0x1000>; 843 #clock-cells = <1>; 844 }; 845 846 topckgen: syscon@10000000 { 847 compatible = "mediatek,mt8186-topckgen", "syscon"; 848 reg = <0 0x10000000 0 0x1000>; 849 #clock-cells = <1>; 850 }; 851 852 infracfg_ao: syscon@10001000 { 853 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 854 reg = <0 0x10001000 0 0x1000>; 855 #clock-cells = <1>; 856 #reset-cells = <1>; 857 }; 858 859 pericfg: syscon@10003000 { 860 compatible = "mediatek,mt8186-pericfg", "syscon"; 861 reg = <0 0x10003000 0 0x1000>; 862 }; 863 864 pio: pinctrl@10005000 { 865 compatible = "mediatek,mt8186-pinctrl"; 866 reg = <0 0x10005000 0 0x1000>, 867 <0 0x10002000 0 0x0200>, 868 <0 0x10002200 0 0x0200>, 869 <0 0x10002400 0 0x0200>, 870 <0 0x10002600 0 0x0200>, 871 <0 0x10002a00 0 0x0200>, 872 <0 0x10002c00 0 0x0200>, 873 <0 0x1000b000 0 0x1000>; 874 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 875 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 876 gpio-controller; 877 #gpio-cells = <2>; 878 gpio-ranges = <&pio 0 0 185>; 879 interrupt-controller; 880 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 881 #interrupt-cells = <2>; 882 }; 883 884 scpsys: syscon@10006000 { 885 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 886 reg = <0 0x10006000 0 0x1000>; 887 888 /* System Power Manager */ 889 spm: power-controller { 890 compatible = "mediatek,mt8186-power-controller"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 #power-domain-cells = <1>; 894 895 /* power domain of the SoC */ 896 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 897 reg = <MT8186_POWER_DOMAIN_MFG0>; 898 clocks = <&topckgen CLK_TOP_MFG>; 899 clock-names = "mfg00"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 #power-domain-cells = <1>; 903 904 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 { 905 reg = <MT8186_POWER_DOMAIN_MFG1>; 906 mediatek,infracfg = <&infracfg_ao>; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 #power-domain-cells = <1>; 910 911 power-domain@MT8186_POWER_DOMAIN_MFG2 { 912 reg = <MT8186_POWER_DOMAIN_MFG2>; 913 #power-domain-cells = <0>; 914 }; 915 916 power-domain@MT8186_POWER_DOMAIN_MFG3 { 917 reg = <MT8186_POWER_DOMAIN_MFG3>; 918 #power-domain-cells = <0>; 919 }; 920 }; 921 }; 922 923 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 924 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 925 clocks = <&topckgen CLK_TOP_SENINF>, 926 <&topckgen CLK_TOP_SENINF1>; 927 clock-names = "subsys-csirx-top0", 928 "subsys-csirx-top1"; 929 #power-domain-cells = <0>; 930 }; 931 932 power-domain@MT8186_POWER_DOMAIN_SSUSB { 933 reg = <MT8186_POWER_DOMAIN_SSUSB>; 934 clocks = <&topckgen CLK_TOP_USB_TOP>, 935 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>; 936 clock-names = "sys_ck", "ref_ck"; 937 #power-domain-cells = <0>; 938 }; 939 940 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 941 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 942 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 943 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>; 944 clock-names = "sys_ck", "ref_ck"; 945 #power-domain-cells = <0>; 946 }; 947 948 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 949 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 950 clocks = <&topckgen CLK_TOP_AUDIODSP>, 951 <&topckgen CLK_TOP_ADSP_BUS>; 952 clock-names = "audioadsp", 953 "subsys-adsp-bus"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 #power-domain-cells = <1>; 957 958 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 959 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 #power-domain-cells = <1>; 963 964 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 965 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 966 mediatek,infracfg = <&infracfg_ao>; 967 #power-domain-cells = <0>; 968 }; 969 }; 970 }; 971 972 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 973 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 974 mediatek,infracfg = <&infracfg_ao>; 975 #power-domain-cells = <0>; 976 }; 977 978 power-domain@MT8186_POWER_DOMAIN_DIS { 979 reg = <MT8186_POWER_DOMAIN_DIS>; 980 clocks = <&topckgen CLK_TOP_DISP>, 981 <&topckgen CLK_TOP_MDP>, 982 <&mmsys CLK_MM_SMI_INFRA>, 983 <&mmsys CLK_MM_SMI_COMMON>, 984 <&mmsys CLK_MM_SMI_GALS>, 985 <&mmsys CLK_MM_SMI_IOMMU>; 986 clock-names = "disp", "mdp", 987 "subsys-smi-infra", 988 "subsys-smi-common", 989 "subsys-smi-gals", 990 "subsys-smi-iommu"; 991 mediatek,infracfg = <&infracfg_ao>; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 #power-domain-cells = <1>; 995 996 power-domain@MT8186_POWER_DOMAIN_VDEC { 997 reg = <MT8186_POWER_DOMAIN_VDEC>; 998 clocks = <&topckgen CLK_TOP_VDEC>, 999 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1000 clock-names = "vdec0", "larb"; 1001 mediatek,infracfg = <&infracfg_ao>; 1002 #power-domain-cells = <0>; 1003 }; 1004 1005 power-domain@MT8186_POWER_DOMAIN_CAM { 1006 reg = <MT8186_POWER_DOMAIN_CAM>; 1007 clocks = <&topckgen CLK_TOP_SENINF>, 1008 <&topckgen CLK_TOP_SENINF1>, 1009 <&topckgen CLK_TOP_SENINF2>, 1010 <&topckgen CLK_TOP_SENINF3>, 1011 <&camsys CLK_CAM2MM_GALS>, 1012 <&topckgen CLK_TOP_CAMTM>, 1013 <&topckgen CLK_TOP_CAM>; 1014 clock-names = "cam0", "cam1", "cam2", 1015 "cam3", "gals", 1016 "subsys-cam-tm", 1017 "subsys-cam-top"; 1018 mediatek,infracfg = <&infracfg_ao>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 #power-domain-cells = <1>; 1022 1023 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 1024 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 1025 #power-domain-cells = <0>; 1026 }; 1027 1028 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 1029 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 1030 #power-domain-cells = <0>; 1031 }; 1032 }; 1033 1034 power-domain@MT8186_POWER_DOMAIN_IMG { 1035 reg = <MT8186_POWER_DOMAIN_IMG>; 1036 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1037 <&topckgen CLK_TOP_IMG1>; 1038 clock-names = "gals", "subsys-img-top"; 1039 mediatek,infracfg = <&infracfg_ao>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 #power-domain-cells = <1>; 1043 1044 power-domain@MT8186_POWER_DOMAIN_IMG2 { 1045 reg = <MT8186_POWER_DOMAIN_IMG2>; 1046 #power-domain-cells = <0>; 1047 }; 1048 }; 1049 1050 power-domain@MT8186_POWER_DOMAIN_IPE { 1051 reg = <MT8186_POWER_DOMAIN_IPE>; 1052 clocks = <&topckgen CLK_TOP_IPE>, 1053 <&ipesys CLK_IPE_LARB19>, 1054 <&ipesys CLK_IPE_LARB20>, 1055 <&ipesys CLK_IPE_SMI_SUBCOM>, 1056 <&ipesys CLK_IPE_GALS_IPE>; 1057 clock-names = "subsys-ipe-top", 1058 "subsys-ipe-larb0", 1059 "subsys-ipe-larb1", 1060 "subsys-ipe-smi", 1061 "subsys-ipe-gals"; 1062 mediatek,infracfg = <&infracfg_ao>; 1063 #power-domain-cells = <0>; 1064 }; 1065 1066 power-domain@MT8186_POWER_DOMAIN_VENC { 1067 reg = <MT8186_POWER_DOMAIN_VENC>; 1068 clocks = <&topckgen CLK_TOP_VENC>, 1069 <&vencsys CLK_VENC_CKE1_VENC>; 1070 clock-names = "venc0", "subsys-larb"; 1071 mediatek,infracfg = <&infracfg_ao>; 1072 #power-domain-cells = <0>; 1073 }; 1074 1075 power-domain@MT8186_POWER_DOMAIN_WPE { 1076 reg = <MT8186_POWER_DOMAIN_WPE>; 1077 clocks = <&topckgen CLK_TOP_WPE>, 1078 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1079 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 1080 clock-names = "wpe0", 1081 "subsys-larb-ck", 1082 "subsys-larb-pclk"; 1083 mediatek,infracfg = <&infracfg_ao>; 1084 #power-domain-cells = <0>; 1085 }; 1086 }; 1087 }; 1088 }; 1089 1090 watchdog: watchdog@10007000 { 1091 compatible = "mediatek,mt8186-wdt"; 1092 mediatek,disable-extrst; 1093 reg = <0 0x10007000 0 0x1000>; 1094 #reset-cells = <1>; 1095 }; 1096 1097 apmixedsys: syscon@1000c000 { 1098 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 1099 reg = <0 0x1000c000 0 0x1000>; 1100 #clock-cells = <1>; 1101 }; 1102 1103 pwrap: pwrap@1000d000 { 1104 compatible = "mediatek,mt8186-pwrap", "syscon"; 1105 reg = <0 0x1000d000 0 0x1000>; 1106 reg-names = "pwrap"; 1107 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1108 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1109 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 1110 clock-names = "spi", "wrap"; 1111 }; 1112 1113 spmi: spmi@10015000 { 1114 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 1115 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 1116 reg-names = "pmif", "spmimst"; 1117 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1118 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 1119 <&topckgen CLK_TOP_SPMI_MST>; 1120 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 1121 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 1122 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 1123 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 1124 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 1125 status = "disabled"; 1126 }; 1127 1128 systimer: timer@10017000 { 1129 compatible = "mediatek,mt8186-timer", 1130 "mediatek,mt6765-timer"; 1131 reg = <0 0x10017000 0 0x1000>; 1132 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 1133 clocks = <&clk13m>; 1134 }; 1135 1136 gce: mailbox@1022c000 { 1137 compatible = "mediatek,mt8186-gce"; 1138 reg = <0 0X1022c000 0 0x4000>; 1139 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 1140 clock-names = "gce"; 1141 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1142 #mbox-cells = <2>; 1143 }; 1144 1145 scp: scp@10500000 { 1146 compatible = "mediatek,mt8186-scp"; 1147 reg = <0 0x10500000 0 0x40000>, 1148 <0 0x105c0000 0 0x19080>; 1149 reg-names = "sram", "cfg"; 1150 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1151 }; 1152 1153 adsp: adsp@10680000 { 1154 compatible = "mediatek,mt8186-dsp"; 1155 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 1156 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 1157 reg-names = "cfg", "sram", "sec", "bus"; 1158 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 1159 clock-names = "audiodsp", "adsp_bus"; 1160 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 1161 <&topckgen CLK_TOP_ADSP_BUS>; 1162 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 1163 mbox-names = "rx", "tx"; 1164 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 1165 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 1166 status = "disabled"; 1167 }; 1168 1169 adsp_mailbox0: mailbox@10686100 { 1170 compatible = "mediatek,mt8186-adsp-mbox"; 1171 #mbox-cells = <0>; 1172 reg = <0 0x10686100 0 0x1000>; 1173 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 1174 }; 1175 1176 adsp_mailbox1: mailbox@10687100 { 1177 compatible = "mediatek,mt8186-adsp-mbox"; 1178 #mbox-cells = <0>; 1179 reg = <0 0x10687100 0 0x1000>; 1180 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 1181 }; 1182 1183 nor_flash: spi@11000000 { 1184 compatible = "mediatek,mt8186-nor"; 1185 reg = <0 0x11000000 0 0x1000>; 1186 clocks = <&topckgen CLK_TOP_SPINOR>, 1187 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 1188 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 1189 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 1190 clock-names = "spi", "sf", "axi", "axi_s"; 1191 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 1192 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 1193 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 1194 status = "disabled"; 1195 }; 1196 1197 auxadc: adc@11001000 { 1198 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 1199 reg = <0 0x11001000 0 0x1000>; 1200 #io-channel-cells = <1>; 1201 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1202 clock-names = "main"; 1203 }; 1204 1205 uart0: serial@11002000 { 1206 compatible = "mediatek,mt8186-uart", 1207 "mediatek,mt6577-uart"; 1208 reg = <0 0x11002000 0 0x1000>; 1209 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1210 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1211 clock-names = "baud", "bus"; 1212 status = "disabled"; 1213 }; 1214 1215 uart1: serial@11003000 { 1216 compatible = "mediatek,mt8186-uart", 1217 "mediatek,mt6577-uart"; 1218 reg = <0 0x11003000 0 0x1000>; 1219 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1220 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1221 clock-names = "baud", "bus"; 1222 status = "disabled"; 1223 }; 1224 1225 i2c0: i2c@11007000 { 1226 compatible = "mediatek,mt8186-i2c"; 1227 reg = <0 0x11007000 0 0x1000>, 1228 <0 0x10200100 0 0x100>; 1229 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 1230 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 1231 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1232 clock-names = "main", "dma"; 1233 clock-div = <1>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 status = "disabled"; 1237 }; 1238 1239 i2c1: i2c@11008000 { 1240 compatible = "mediatek,mt8186-i2c"; 1241 reg = <0 0x11008000 0 0x1000>, 1242 <0 0x10200200 0 0x100>; 1243 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1244 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 1245 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1246 clock-names = "main", "dma"; 1247 clock-div = <1>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 i2c2: i2c@11009000 { 1254 compatible = "mediatek,mt8186-i2c"; 1255 reg = <0 0x11009000 0 0x1000>, 1256 <0 0x10200300 0 0x180>; 1257 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 1258 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 1259 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1260 clock-names = "main", "dma"; 1261 clock-div = <1>; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 status = "disabled"; 1265 }; 1266 1267 i2c3: i2c@1100f000 { 1268 compatible = "mediatek,mt8186-i2c"; 1269 reg = <0 0x1100f000 0 0x1000>, 1270 <0 0x10200480 0 0x100>; 1271 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1272 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 1273 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1274 clock-names = "main", "dma"; 1275 clock-div = <1>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 status = "disabled"; 1279 }; 1280 1281 i2c4: i2c@11011000 { 1282 compatible = "mediatek,mt8186-i2c"; 1283 reg = <0 0x11011000 0 0x1000>, 1284 <0 0x10200580 0 0x180>; 1285 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 1286 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 1287 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1288 clock-names = "main", "dma"; 1289 clock-div = <1>; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 status = "disabled"; 1293 }; 1294 1295 i2c5: i2c@11016000 { 1296 compatible = "mediatek,mt8186-i2c"; 1297 reg = <0 0x11016000 0 0x1000>, 1298 <0 0x10200700 0 0x100>; 1299 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1300 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 1301 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1302 clock-names = "main", "dma"; 1303 clock-div = <1>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 i2c6: i2c@1100d000 { 1310 compatible = "mediatek,mt8186-i2c"; 1311 reg = <0 0x1100d000 0 0x1000>, 1312 <0 0x10200800 0 0x100>; 1313 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1314 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 1315 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1316 clock-names = "main", "dma"; 1317 clock-div = <1>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 status = "disabled"; 1321 }; 1322 1323 i2c7: i2c@11004000 { 1324 compatible = "mediatek,mt8186-i2c"; 1325 reg = <0 0x11004000 0 0x1000>, 1326 <0 0x10200900 0 0x180>; 1327 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 1328 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 1329 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1330 clock-names = "main", "dma"; 1331 clock-div = <1>; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 i2c8: i2c@11005000 { 1338 compatible = "mediatek,mt8186-i2c"; 1339 reg = <0 0x11005000 0 0x1000>, 1340 <0 0x10200A80 0 0x180>; 1341 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1342 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 1343 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1344 clock-names = "main", "dma"; 1345 clock-div = <1>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 spi0: spi@1100a000 { 1352 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 reg = <0 0x1100a000 0 0x1000>; 1356 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 1357 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1358 <&topckgen CLK_TOP_SPI>, 1359 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1360 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1361 status = "disabled"; 1362 }; 1363 1364 pwm0: pwm@1100e000 { 1365 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 1366 reg = <0 0x1100e000 0 0x1000>; 1367 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1368 #pwm-cells = <2>; 1369 clocks = <&topckgen CLK_TOP_DISP_PWM>, 1370 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1371 clock-names = "main", "mm"; 1372 status = "disabled"; 1373 }; 1374 1375 spi1: spi@11010000 { 1376 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 reg = <0 0x11010000 0 0x1000>; 1380 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 1381 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1382 <&topckgen CLK_TOP_SPI>, 1383 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1384 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1385 status = "disabled"; 1386 }; 1387 1388 spi2: spi@11012000 { 1389 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 reg = <0 0x11012000 0 0x1000>; 1393 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 1394 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1395 <&topckgen CLK_TOP_SPI>, 1396 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1397 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1398 status = "disabled"; 1399 }; 1400 1401 spi3: spi@11013000 { 1402 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 reg = <0 0x11013000 0 0x1000>; 1406 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1407 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1408 <&topckgen CLK_TOP_SPI>, 1409 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1410 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1411 status = "disabled"; 1412 }; 1413 1414 spi4: spi@11014000 { 1415 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 reg = <0 0x11014000 0 0x1000>; 1419 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1420 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1421 <&topckgen CLK_TOP_SPI>, 1422 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1423 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1424 status = "disabled"; 1425 }; 1426 1427 spi5: spi@11015000 { 1428 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 reg = <0 0x11015000 0 0x1000>; 1432 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1433 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1434 <&topckgen CLK_TOP_SPI>, 1435 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1436 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1437 status = "disabled"; 1438 }; 1439 1440 imp_iic_wrap: clock-controller@11017000 { 1441 compatible = "mediatek,mt8186-imp_iic_wrap"; 1442 reg = <0 0x11017000 0 0x1000>; 1443 #clock-cells = <1>; 1444 }; 1445 1446 uart2: serial@11018000 { 1447 compatible = "mediatek,mt8186-uart", 1448 "mediatek,mt6577-uart"; 1449 reg = <0 0x11018000 0 0x1000>; 1450 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 1451 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1452 clock-names = "baud", "bus"; 1453 status = "disabled"; 1454 }; 1455 1456 i2c9: i2c@11019000 { 1457 compatible = "mediatek,mt8186-i2c"; 1458 reg = <0 0x11019000 0 0x1000>, 1459 <0 0x10200c00 0 0x180>; 1460 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1461 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 1462 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1463 clock-names = "main", "dma"; 1464 clock-div = <1>; 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 status = "disabled"; 1468 }; 1469 1470 afe: audio-controller@11210000 { 1471 compatible = "mediatek,mt8186-sound"; 1472 reg = <0 0x11210000 0 0x2000>; 1473 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 1474 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 1475 <&topckgen CLK_TOP_AUDIO>, 1476 <&topckgen CLK_TOP_AUD_INTBUS>, 1477 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 1478 <&topckgen CLK_TOP_AUD_1>, 1479 <&apmixedsys CLK_APMIXED_APLL1>, 1480 <&topckgen CLK_TOP_AUD_2>, 1481 <&apmixedsys CLK_APMIXED_APLL2>, 1482 <&topckgen CLK_TOP_AUD_ENGEN1>, 1483 <&topckgen CLK_TOP_APLL1_D8>, 1484 <&topckgen CLK_TOP_AUD_ENGEN2>, 1485 <&topckgen CLK_TOP_APLL2_D8>, 1486 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 1487 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 1488 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 1489 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 1490 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 1491 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 1492 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 1493 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 1494 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 1495 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 1496 <&topckgen CLK_TOP_AUDIO_H>, 1497 <&clk26m>; 1498 clock-names = "aud_infra_clk", 1499 "mtkaif_26m_clk", 1500 "top_mux_audio", 1501 "top_mux_audio_int", 1502 "top_mainpll_d2_d4", 1503 "top_mux_aud_1", 1504 "top_apll1_ck", 1505 "top_mux_aud_2", 1506 "top_apll2_ck", 1507 "top_mux_aud_eng1", 1508 "top_apll1_d8", 1509 "top_mux_aud_eng2", 1510 "top_apll2_d8", 1511 "top_i2s0_m_sel", 1512 "top_i2s1_m_sel", 1513 "top_i2s2_m_sel", 1514 "top_i2s4_m_sel", 1515 "top_tdm_m_sel", 1516 "top_apll12_div0", 1517 "top_apll12_div1", 1518 "top_apll12_div2", 1519 "top_apll12_div4", 1520 "top_apll12_div_tdm", 1521 "top_mux_audio_h", 1522 "top_clk26m_clk"; 1523 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1524 mediatek,apmixedsys = <&apmixedsys>; 1525 mediatek,infracfg = <&infracfg_ao>; 1526 mediatek,topckgen = <&topckgen>; 1527 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 1528 reset-names = "audiosys"; 1529 status = "disabled"; 1530 }; 1531 1532 ssusb0: usb@11201000 { 1533 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1534 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1535 reg-names = "mac", "ippc"; 1536 clocks = <&topckgen CLK_TOP_USB_TOP>, 1537 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1538 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1539 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1540 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1541 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1542 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1543 phys = <&u2port0 PHY_TYPE_USB2>; 1544 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1545 #address-cells = <2>; 1546 #size-cells = <2>; 1547 ranges; 1548 status = "disabled"; 1549 1550 usb_host0: usb@11200000 { 1551 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1552 reg = <0 0x11200000 0 0x1000>; 1553 reg-names = "mac"; 1554 clocks = <&topckgen CLK_TOP_USB_TOP>, 1555 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1556 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1557 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1558 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1559 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1560 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1561 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1562 wakeup-source; 1563 status = "disabled"; 1564 }; 1565 }; 1566 1567 mmc0: mmc@11230000 { 1568 compatible = "mediatek,mt8186-mmc", 1569 "mediatek,mt8183-mmc"; 1570 reg = <0 0x11230000 0 0x10000>, 1571 <0 0x11cd0000 0 0x1000>; 1572 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1573 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1574 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1575 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1576 clock-names = "source", "hclk", "source_cg", "crypto"; 1577 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1578 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1579 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1580 status = "disabled"; 1581 }; 1582 1583 mmc1: mmc@11240000 { 1584 compatible = "mediatek,mt8186-mmc", 1585 "mediatek,mt8183-mmc"; 1586 reg = <0 0x11240000 0 0x1000>, 1587 <0 0x11c90000 0 0x1000>; 1588 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1589 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1590 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1591 clock-names = "source", "hclk", "source_cg"; 1592 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1593 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1594 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1595 status = "disabled"; 1596 }; 1597 1598 ssusb1: usb@11281000 { 1599 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1600 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1601 reg-names = "mac", "ippc"; 1602 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1603 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1604 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1605 <&clk26m>, 1606 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1607 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1608 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1609 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1610 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1611 #address-cells = <2>; 1612 #size-cells = <2>; 1613 ranges; 1614 status = "disabled"; 1615 1616 usb_host1: usb@11280000 { 1617 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1618 reg = <0 0x11280000 0 0x1000>; 1619 reg-names = "mac"; 1620 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1621 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1622 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1623 <&clk26m>, 1624 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1625 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1626 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1627 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1628 wakeup-source; 1629 status = "disabled"; 1630 }; 1631 }; 1632 1633 u3phy0: t-phy@11c80000 { 1634 compatible = "mediatek,mt8186-tphy", 1635 "mediatek,generic-tphy-v2"; 1636 #address-cells = <1>; 1637 #size-cells = <1>; 1638 ranges = <0x0 0x0 0x11c80000 0x1000>; 1639 status = "disabled"; 1640 1641 u2port1: usb-phy@0 { 1642 reg = <0x0 0x700>; 1643 clocks = <&clk26m>; 1644 clock-names = "ref"; 1645 #phy-cells = <1>; 1646 }; 1647 1648 u3port1: usb-phy@700 { 1649 reg = <0x700 0x900>; 1650 clocks = <&clk26m>; 1651 clock-names = "ref"; 1652 #phy-cells = <1>; 1653 }; 1654 }; 1655 1656 u3phy1: t-phy@11ca0000 { 1657 compatible = "mediatek,mt8186-tphy", 1658 "mediatek,generic-tphy-v2"; 1659 #address-cells = <1>; 1660 #size-cells = <1>; 1661 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1662 status = "disabled"; 1663 1664 u2port0: usb-phy@0 { 1665 reg = <0x0 0x700>; 1666 clocks = <&clk26m>; 1667 clock-names = "ref"; 1668 #phy-cells = <1>; 1669 mediatek,discth = <0x8>; 1670 }; 1671 }; 1672 1673 efuse: efuse@11cb0000 { 1674 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1675 reg = <0 0x11cb0000 0 0x1000>; 1676 #address-cells = <1>; 1677 #size-cells = <1>; 1678 1679 gpu_speedbin: gpu-speedbin@59c { 1680 reg = <0x59c 0x4>; 1681 bits = <0 3>; 1682 }; 1683 }; 1684 1685 mipi_tx0: dsi-phy@11cc0000 { 1686 compatible = "mediatek,mt8183-mipi-tx"; 1687 reg = <0 0x11cc0000 0 0x1000>; 1688 clocks = <&clk26m>; 1689 #clock-cells = <0>; 1690 #phy-cells = <0>; 1691 clock-output-names = "mipi_tx0_pll"; 1692 status = "disabled"; 1693 }; 1694 1695 mfgsys: clock-controller@13000000 { 1696 compatible = "mediatek,mt8186-mfgsys"; 1697 reg = <0 0x13000000 0 0x1000>; 1698 #clock-cells = <1>; 1699 }; 1700 1701 gpu: gpu@13040000 { 1702 compatible = "mediatek,mt8186-mali", 1703 "arm,mali-bifrost"; 1704 reg = <0 0x13040000 0 0x4000>; 1705 1706 clocks = <&mfgsys CLK_MFG_BG3D>; 1707 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1708 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1709 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1710 interrupt-names = "job", "mmu", "gpu"; 1711 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1712 <&spm MT8186_POWER_DOMAIN_MFG3>; 1713 power-domain-names = "core0", "core1"; 1714 #cooling-cells = <2>; 1715 nvmem-cells = <&gpu_speedbin>; 1716 nvmem-cell-names = "speed-bin"; 1717 operating-points-v2 = <&gpu_opp_table>; 1718 dynamic-power-coefficient = <4687>; 1719 status = "disabled"; 1720 }; 1721 1722 mmsys: syscon@14000000 { 1723 compatible = "mediatek,mt8186-mmsys", "syscon"; 1724 reg = <0 0x14000000 0 0x1000>; 1725 #clock-cells = <1>; 1726 #reset-cells = <1>; 1727 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1728 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1729 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1730 }; 1731 1732 mutex: mutex@14001000 { 1733 compatible = "mediatek,mt8186-disp-mutex"; 1734 reg = <0 0x14001000 0 0x1000>; 1735 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1736 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 1737 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1738 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1739 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1740 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1741 }; 1742 1743 smi_common: smi@14002000 { 1744 compatible = "mediatek,mt8186-smi-common"; 1745 reg = <0 0x14002000 0 0x1000>; 1746 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1747 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1748 clock-names = "apb", "smi", "gals0", "gals1"; 1749 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1750 }; 1751 1752 larb0: smi@14003000 { 1753 compatible = "mediatek,mt8186-smi-larb"; 1754 reg = <0 0x14003000 0 0x1000>; 1755 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1756 <&mmsys CLK_MM_SMI_COMMON>; 1757 clock-names = "apb", "smi"; 1758 mediatek,larb-id = <0>; 1759 mediatek,smi = <&smi_common>; 1760 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1761 }; 1762 1763 larb1: smi@14004000 { 1764 compatible = "mediatek,mt8186-smi-larb"; 1765 reg = <0 0x14004000 0 0x1000>; 1766 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1767 <&mmsys CLK_MM_SMI_COMMON>; 1768 clock-names = "apb", "smi"; 1769 mediatek,larb-id = <1>; 1770 mediatek,smi = <&smi_common>; 1771 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1772 }; 1773 1774 ovl0: ovl@14005000 { 1775 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; 1776 reg = <0 0x14005000 0 0x1000>; 1777 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1778 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 1779 iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; 1780 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1781 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1782 }; 1783 1784 ovl_2l0: ovl@14006000 { 1785 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; 1786 reg = <0 0x14006000 0 0x1000>; 1787 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1788 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1789 iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; 1790 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1791 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1792 }; 1793 1794 rdma0: rdma@14007000 { 1795 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1796 reg = <0 0x14007000 0 0x1000>; 1797 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1798 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 1799 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; 1800 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1801 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1802 }; 1803 1804 color: color@14009000 { 1805 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; 1806 reg = <0 0x14009000 0 0x1000>; 1807 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1808 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 1809 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1810 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1811 }; 1812 1813 dpi: dpi@1400a000 { 1814 compatible = "mediatek,mt8186-dpi"; 1815 reg = <0 0x1400a000 0 0x1000>; 1816 clocks = <&topckgen CLK_TOP_DPI>, 1817 <&mmsys CLK_MM_DISP_DPI>, 1818 <&apmixedsys CLK_APMIXED_TVDPLL>; 1819 clock-names = "pixel", "engine", "pll"; 1820 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1821 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1822 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1823 status = "disabled"; 1824 1825 port { 1826 dpi_out: endpoint { }; 1827 }; 1828 }; 1829 1830 ccorr: ccorr@1400b000 { 1831 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 1832 reg = <0 0x1400b000 0 0x1000>; 1833 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1834 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; 1835 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1836 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1837 }; 1838 1839 aal: aal@1400c000 { 1840 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; 1841 reg = <0 0x1400c000 0 0x1000>; 1842 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1843 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 1844 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1845 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1846 }; 1847 1848 gamma: gamma@1400d000 { 1849 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; 1850 reg = <0 0x1400d000 0 0x1000>; 1851 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1852 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 1853 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1854 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1855 }; 1856 1857 postmask: postmask@1400e000 { 1858 compatible = "mediatek,mt8186-disp-postmask", 1859 "mediatek,mt8192-disp-postmask"; 1860 reg = <0 0x1400e000 0 0x1000>; 1861 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1862 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 1863 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1864 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1865 }; 1866 1867 dither: dither@1400f000 { 1868 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; 1869 reg = <0 0x1400f000 0 0x1000>; 1870 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1871 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 1872 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1873 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1874 }; 1875 1876 dsi0: dsi@14013000 { 1877 compatible = "mediatek,mt8186-dsi"; 1878 reg = <0 0x14013000 0 0x1000>; 1879 clocks = <&mmsys CLK_MM_DSI0>, 1880 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1881 <&mipi_tx0>; 1882 clock-names = "engine", "digital", "hs"; 1883 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1884 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1885 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1886 phys = <&mipi_tx0>; 1887 phy-names = "dphy"; 1888 status = "disabled"; 1889 1890 port { 1891 dsi_out: endpoint { }; 1892 }; 1893 }; 1894 1895 iommu_mm: iommu@14016000 { 1896 compatible = "mediatek,mt8186-iommu-mm"; 1897 reg = <0 0x14016000 0 0x1000>; 1898 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1899 clock-names = "bclk"; 1900 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1901 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1902 &larb7 &larb8 &larb9 &larb11 1903 &larb13 &larb14 &larb16 &larb17 1904 &larb19 &larb20>; 1905 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1906 #iommu-cells = <1>; 1907 }; 1908 1909 rdma1: rdma@1401f000 { 1910 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1911 reg = <0 0x1401f000 0 0x1000>; 1912 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1913 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; 1914 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; 1915 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; 1916 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1917 }; 1918 1919 wpesys: clock-controller@14020000 { 1920 compatible = "mediatek,mt8186-wpesys"; 1921 reg = <0 0x14020000 0 0x1000>; 1922 #clock-cells = <1>; 1923 }; 1924 1925 larb8: smi@14023000 { 1926 compatible = "mediatek,mt8186-smi-larb"; 1927 reg = <0 0x14023000 0 0x1000>; 1928 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1929 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1930 clock-names = "apb", "smi"; 1931 mediatek,larb-id = <8>; 1932 mediatek,smi = <&smi_common>; 1933 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1934 }; 1935 1936 imgsys1: clock-controller@15020000 { 1937 compatible = "mediatek,mt8186-imgsys1"; 1938 reg = <0 0x15020000 0 0x1000>; 1939 #clock-cells = <1>; 1940 }; 1941 1942 larb9: smi@1502e000 { 1943 compatible = "mediatek,mt8186-smi-larb"; 1944 reg = <0 0x1502e000 0 0x1000>; 1945 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1946 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1947 clock-names = "apb", "smi"; 1948 mediatek,larb-id = <9>; 1949 mediatek,smi = <&smi_common>; 1950 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1951 }; 1952 1953 imgsys2: clock-controller@15820000 { 1954 compatible = "mediatek,mt8186-imgsys2"; 1955 reg = <0 0x15820000 0 0x1000>; 1956 #clock-cells = <1>; 1957 }; 1958 1959 larb11: smi@1582e000 { 1960 compatible = "mediatek,mt8186-smi-larb"; 1961 reg = <0 0x1582e000 0 0x1000>; 1962 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1963 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1964 clock-names = "apb", "smi"; 1965 mediatek,larb-id = <11>; 1966 mediatek,smi = <&smi_common>; 1967 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1968 }; 1969 1970 larb4: smi@1602e000 { 1971 compatible = "mediatek,mt8186-smi-larb"; 1972 reg = <0 0x1602e000 0 0x1000>; 1973 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1974 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1975 clock-names = "apb", "smi"; 1976 mediatek,larb-id = <4>; 1977 mediatek,smi = <&smi_common>; 1978 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1979 }; 1980 1981 vdecsys: clock-controller@1602f000 { 1982 compatible = "mediatek,mt8186-vdecsys"; 1983 reg = <0 0x1602f000 0 0x1000>; 1984 #clock-cells = <1>; 1985 }; 1986 1987 vencsys: clock-controller@17000000 { 1988 compatible = "mediatek,mt8186-vencsys"; 1989 reg = <0 0x17000000 0 0x1000>; 1990 #clock-cells = <1>; 1991 }; 1992 1993 larb7: smi@17010000 { 1994 compatible = "mediatek,mt8186-smi-larb"; 1995 reg = <0 0x17010000 0 0x1000>; 1996 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1997 <&vencsys CLK_VENC_CKE1_VENC>; 1998 clock-names = "apb", "smi"; 1999 mediatek,larb-id = <7>; 2000 mediatek,smi = <&smi_common>; 2001 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 2002 }; 2003 2004 camsys: clock-controller@1a000000 { 2005 compatible = "mediatek,mt8186-camsys"; 2006 reg = <0 0x1a000000 0 0x1000>; 2007 #clock-cells = <1>; 2008 }; 2009 2010 larb13: smi@1a001000 { 2011 compatible = "mediatek,mt8186-smi-larb"; 2012 reg = <0 0x1a001000 0 0x1000>; 2013 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 2014 clock-names = "apb", "smi"; 2015 mediatek,larb-id = <13>; 2016 mediatek,smi = <&smi_common>; 2017 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 2018 }; 2019 2020 larb14: smi@1a002000 { 2021 compatible = "mediatek,mt8186-smi-larb"; 2022 reg = <0 0x1a002000 0 0x1000>; 2023 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 2024 clock-names = "apb", "smi"; 2025 mediatek,larb-id = <14>; 2026 mediatek,smi = <&smi_common>; 2027 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 2028 }; 2029 2030 larb16: smi@1a00f000 { 2031 compatible = "mediatek,mt8186-smi-larb"; 2032 reg = <0 0x1a00f000 0 0x1000>; 2033 clocks = <&camsys CLK_CAM_LARB14>, 2034 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 2035 clock-names = "apb", "smi"; 2036 mediatek,larb-id = <16>; 2037 mediatek,smi = <&smi_common>; 2038 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 2039 }; 2040 2041 larb17: smi@1a010000 { 2042 compatible = "mediatek,mt8186-smi-larb"; 2043 reg = <0 0x1a010000 0 0x1000>; 2044 clocks = <&camsys CLK_CAM_LARB13>, 2045 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 2046 clock-names = "apb", "smi"; 2047 mediatek,larb-id = <17>; 2048 mediatek,smi = <&smi_common>; 2049 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 2050 }; 2051 2052 camsys_rawa: clock-controller@1a04f000 { 2053 compatible = "mediatek,mt8186-camsys_rawa"; 2054 reg = <0 0x1a04f000 0 0x1000>; 2055 #clock-cells = <1>; 2056 }; 2057 2058 camsys_rawb: clock-controller@1a06f000 { 2059 compatible = "mediatek,mt8186-camsys_rawb"; 2060 reg = <0 0x1a06f000 0 0x1000>; 2061 #clock-cells = <1>; 2062 }; 2063 2064 mdpsys: clock-controller@1b000000 { 2065 compatible = "mediatek,mt8186-mdpsys"; 2066 reg = <0 0x1b000000 0 0x1000>; 2067 #clock-cells = <1>; 2068 }; 2069 2070 larb2: smi@1b002000 { 2071 compatible = "mediatek,mt8186-smi-larb"; 2072 reg = <0 0x1b002000 0 0x1000>; 2073 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 2074 clock-names = "apb", "smi"; 2075 mediatek,larb-id = <2>; 2076 mediatek,smi = <&smi_common>; 2077 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 2078 }; 2079 2080 ipesys: clock-controller@1c000000 { 2081 compatible = "mediatek,mt8186-ipesys"; 2082 reg = <0 0x1c000000 0 0x1000>; 2083 #clock-cells = <1>; 2084 }; 2085 2086 larb20: smi@1c00f000 { 2087 compatible = "mediatek,mt8186-smi-larb"; 2088 reg = <0 0x1c00f000 0 0x1000>; 2089 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 2090 clock-names = "apb", "smi"; 2091 mediatek,larb-id = <20>; 2092 mediatek,smi = <&smi_common>; 2093 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 2094 }; 2095 2096 larb19: smi@1c10f000 { 2097 compatible = "mediatek,mt8186-smi-larb"; 2098 reg = <0 0x1c10f000 0 0x1000>; 2099 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 2100 clock-names = "apb", "smi"; 2101 mediatek,larb-id = <19>; 2102 mediatek,smi = <&smi_common>; 2103 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 2104 }; 2105 }; 2106}; 2107