12e78620bSAllen-KH Cheng// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 22e78620bSAllen-KH Cheng/* 32e78620bSAllen-KH Cheng * Copyright (C) 2022 MediaTek Inc. 42e78620bSAllen-KH Cheng * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 52e78620bSAllen-KH Cheng */ 62e78620bSAllen-KH Cheng/dts-v1/; 72e78620bSAllen-KH Cheng#include <dt-bindings/clock/mt8186-clk.h> 841218847SAllen-KH Cheng#include <dt-bindings/gce/mt8186-gce.h> 92e78620bSAllen-KH Cheng#include <dt-bindings/interrupt-controller/arm-gic.h> 102e78620bSAllen-KH Cheng#include <dt-bindings/interrupt-controller/irq.h> 11d4a65162SAllen-KH Cheng#include <dt-bindings/memory/mt8186-memory-port.h> 122e78620bSAllen-KH Cheng#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 132e78620bSAllen-KH Cheng#include <dt-bindings/power/mt8186-power.h> 142e78620bSAllen-KH Cheng#include <dt-bindings/phy/phy.h> 152e78620bSAllen-KH Cheng#include <dt-bindings/reset/mt8186-resets.h> 162e78620bSAllen-KH Cheng 172e78620bSAllen-KH Cheng/ { 182e78620bSAllen-KH Cheng compatible = "mediatek,mt8186"; 192e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 202e78620bSAllen-KH Cheng #address-cells = <2>; 212e78620bSAllen-KH Cheng #size-cells = <2>; 222e78620bSAllen-KH Cheng 23*7e07d332SAllen-KH Cheng aliases { 24*7e07d332SAllen-KH Cheng ovl0 = &ovl0; 25*7e07d332SAllen-KH Cheng ovl_2l0 = &ovl_2l0; 26*7e07d332SAllen-KH Cheng rdma0 = &rdma0; 27*7e07d332SAllen-KH Cheng rdma1 = &rdma1; 28*7e07d332SAllen-KH Cheng }; 29*7e07d332SAllen-KH Cheng 302e78620bSAllen-KH Cheng cpus { 312e78620bSAllen-KH Cheng #address-cells = <1>; 322e78620bSAllen-KH Cheng #size-cells = <0>; 332e78620bSAllen-KH Cheng 342e78620bSAllen-KH Cheng cpu-map { 352e78620bSAllen-KH Cheng cluster0 { 362e78620bSAllen-KH Cheng core0 { 372e78620bSAllen-KH Cheng cpu = <&cpu0>; 382e78620bSAllen-KH Cheng }; 392e78620bSAllen-KH Cheng 402e78620bSAllen-KH Cheng core1 { 412e78620bSAllen-KH Cheng cpu = <&cpu1>; 422e78620bSAllen-KH Cheng }; 432e78620bSAllen-KH Cheng 442e78620bSAllen-KH Cheng core2 { 452e78620bSAllen-KH Cheng cpu = <&cpu2>; 462e78620bSAllen-KH Cheng }; 472e78620bSAllen-KH Cheng 482e78620bSAllen-KH Cheng core3 { 492e78620bSAllen-KH Cheng cpu = <&cpu3>; 502e78620bSAllen-KH Cheng }; 512e78620bSAllen-KH Cheng 522e78620bSAllen-KH Cheng core4 { 532e78620bSAllen-KH Cheng cpu = <&cpu4>; 542e78620bSAllen-KH Cheng }; 552e78620bSAllen-KH Cheng 562e78620bSAllen-KH Cheng core5 { 572e78620bSAllen-KH Cheng cpu = <&cpu5>; 582e78620bSAllen-KH Cheng }; 592e78620bSAllen-KH Cheng 601c473804SAngeloGioacchino Del Regno core6 { 612e78620bSAllen-KH Cheng cpu = <&cpu6>; 622e78620bSAllen-KH Cheng }; 632e78620bSAllen-KH Cheng 641c473804SAngeloGioacchino Del Regno core7 { 652e78620bSAllen-KH Cheng cpu = <&cpu7>; 662e78620bSAllen-KH Cheng }; 672e78620bSAllen-KH Cheng }; 682e78620bSAllen-KH Cheng }; 692e78620bSAllen-KH Cheng 702e78620bSAllen-KH Cheng cpu0: cpu@0 { 712e78620bSAllen-KH Cheng device_type = "cpu"; 722e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 732e78620bSAllen-KH Cheng reg = <0x000>; 742e78620bSAllen-KH Cheng enable-method = "psci"; 752e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 762e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 77f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 7870282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 7970282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 8070282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 8170282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 8270282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 8370282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 842e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 852e78620bSAllen-KH Cheng #cooling-cells = <2>; 862e78620bSAllen-KH Cheng }; 872e78620bSAllen-KH Cheng 882e78620bSAllen-KH Cheng cpu1: cpu@100 { 892e78620bSAllen-KH Cheng device_type = "cpu"; 902e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 912e78620bSAllen-KH Cheng reg = <0x100>; 922e78620bSAllen-KH Cheng enable-method = "psci"; 932e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 942e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 95f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 9670282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 9770282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 9870282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 9970282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 10070282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 10170282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 1022e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 1032e78620bSAllen-KH Cheng #cooling-cells = <2>; 1042e78620bSAllen-KH Cheng }; 1052e78620bSAllen-KH Cheng 1062e78620bSAllen-KH Cheng cpu2: cpu@200 { 1072e78620bSAllen-KH Cheng device_type = "cpu"; 1082e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 1092e78620bSAllen-KH Cheng reg = <0x200>; 1102e78620bSAllen-KH Cheng enable-method = "psci"; 1112e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 1122e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 113f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 11470282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 11570282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 11670282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 11770282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 11870282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 11970282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 1202e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 1212e78620bSAllen-KH Cheng #cooling-cells = <2>; 1222e78620bSAllen-KH Cheng }; 1232e78620bSAllen-KH Cheng 1242e78620bSAllen-KH Cheng cpu3: cpu@300 { 1252e78620bSAllen-KH Cheng device_type = "cpu"; 1262e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 1272e78620bSAllen-KH Cheng reg = <0x300>; 1282e78620bSAllen-KH Cheng enable-method = "psci"; 1292e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 1302e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 131f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 13270282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 13370282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 13470282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 13570282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 13670282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 13770282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 1382e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 1392e78620bSAllen-KH Cheng #cooling-cells = <2>; 1402e78620bSAllen-KH Cheng }; 1412e78620bSAllen-KH Cheng 1422e78620bSAllen-KH Cheng cpu4: cpu@400 { 1432e78620bSAllen-KH Cheng device_type = "cpu"; 1442e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 1452e78620bSAllen-KH Cheng reg = <0x400>; 1462e78620bSAllen-KH Cheng enable-method = "psci"; 1472e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 1482e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 149f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 15070282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 15170282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 15270282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 15370282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 15470282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 15570282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 1562e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 1572e78620bSAllen-KH Cheng #cooling-cells = <2>; 1582e78620bSAllen-KH Cheng }; 1592e78620bSAllen-KH Cheng 1602e78620bSAllen-KH Cheng cpu5: cpu@500 { 1612e78620bSAllen-KH Cheng device_type = "cpu"; 1622e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 1632e78620bSAllen-KH Cheng reg = <0x500>; 1642e78620bSAllen-KH Cheng enable-method = "psci"; 1652e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 1662e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 167f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 16870282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 16970282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 17070282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 17170282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 17270282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 17370282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 1742e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 1752e78620bSAllen-KH Cheng #cooling-cells = <2>; 1762e78620bSAllen-KH Cheng }; 1772e78620bSAllen-KH Cheng 1782e78620bSAllen-KH Cheng cpu6: cpu@600 { 1792e78620bSAllen-KH Cheng device_type = "cpu"; 1802e78620bSAllen-KH Cheng compatible = "arm,cortex-a76"; 1812e78620bSAllen-KH Cheng reg = <0x600>; 1822e78620bSAllen-KH Cheng enable-method = "psci"; 1832e78620bSAllen-KH Cheng clock-frequency = <2050000000>; 1842e78620bSAllen-KH Cheng capacity-dmips-mhz = <1024>; 185f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 18670282f31SAngeloGioacchino Del Regno i-cache-size = <65536>; 18770282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 18870282f31SAngeloGioacchino Del Regno i-cache-sets = <256>; 18970282f31SAngeloGioacchino Del Regno d-cache-size = <65536>; 19070282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 19170282f31SAngeloGioacchino Del Regno d-cache-sets = <256>; 1922e78620bSAllen-KH Cheng next-level-cache = <&l2_1>; 1932e78620bSAllen-KH Cheng #cooling-cells = <2>; 1942e78620bSAllen-KH Cheng }; 1952e78620bSAllen-KH Cheng 1962e78620bSAllen-KH Cheng cpu7: cpu@700 { 1972e78620bSAllen-KH Cheng device_type = "cpu"; 1982e78620bSAllen-KH Cheng compatible = "arm,cortex-a76"; 1992e78620bSAllen-KH Cheng reg = <0x700>; 2002e78620bSAllen-KH Cheng enable-method = "psci"; 2012e78620bSAllen-KH Cheng clock-frequency = <2050000000>; 2022e78620bSAllen-KH Cheng capacity-dmips-mhz = <1024>; 203f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 20470282f31SAngeloGioacchino Del Regno i-cache-size = <65536>; 20570282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 20670282f31SAngeloGioacchino Del Regno i-cache-sets = <256>; 20770282f31SAngeloGioacchino Del Regno d-cache-size = <65536>; 20870282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 20970282f31SAngeloGioacchino Del Regno d-cache-sets = <256>; 2102e78620bSAllen-KH Cheng next-level-cache = <&l2_1>; 2112e78620bSAllen-KH Cheng #cooling-cells = <2>; 2122e78620bSAllen-KH Cheng }; 2132e78620bSAllen-KH Cheng 2142e78620bSAllen-KH Cheng idle-states { 2152e78620bSAllen-KH Cheng entry-method = "psci"; 2162e78620bSAllen-KH Cheng 217f3ca1580SAngeloGioacchino Del Regno cpu_ret_l: cpu-retention-l { 2182e78620bSAllen-KH Cheng compatible = "arm,idle-state"; 2192e78620bSAllen-KH Cheng arm,psci-suspend-param = <0x00010001>; 2202e78620bSAllen-KH Cheng local-timer-stop; 2212e78620bSAllen-KH Cheng entry-latency-us = <50>; 2222e78620bSAllen-KH Cheng exit-latency-us = <100>; 2232e78620bSAllen-KH Cheng min-residency-us = <1600>; 2242e78620bSAllen-KH Cheng }; 2252e78620bSAllen-KH Cheng 226f3ca1580SAngeloGioacchino Del Regno cpu_ret_b: cpu-retention-b { 2272e78620bSAllen-KH Cheng compatible = "arm,idle-state"; 2282e78620bSAllen-KH Cheng arm,psci-suspend-param = <0x00010001>; 2292e78620bSAllen-KH Cheng local-timer-stop; 2302e78620bSAllen-KH Cheng entry-latency-us = <50>; 2312e78620bSAllen-KH Cheng exit-latency-us = <100>; 2322e78620bSAllen-KH Cheng min-residency-us = <1400>; 2332e78620bSAllen-KH Cheng }; 2342e78620bSAllen-KH Cheng 235f3ca1580SAngeloGioacchino Del Regno cpu_off_l: cpu-off-l { 2362e78620bSAllen-KH Cheng compatible = "arm,idle-state"; 2372e78620bSAllen-KH Cheng arm,psci-suspend-param = <0x01010001>; 2382e78620bSAllen-KH Cheng local-timer-stop; 2392e78620bSAllen-KH Cheng entry-latency-us = <100>; 2402e78620bSAllen-KH Cheng exit-latency-us = <250>; 2412e78620bSAllen-KH Cheng min-residency-us = <2100>; 2422e78620bSAllen-KH Cheng }; 2432e78620bSAllen-KH Cheng 244f3ca1580SAngeloGioacchino Del Regno cpu_off_b: cpu-off-b { 2452e78620bSAllen-KH Cheng compatible = "arm,idle-state"; 2462e78620bSAllen-KH Cheng arm,psci-suspend-param = <0x01010001>; 2472e78620bSAllen-KH Cheng local-timer-stop; 2482e78620bSAllen-KH Cheng entry-latency-us = <100>; 2492e78620bSAllen-KH Cheng exit-latency-us = <250>; 2502e78620bSAllen-KH Cheng min-residency-us = <1900>; 2512e78620bSAllen-KH Cheng }; 2522e78620bSAllen-KH Cheng }; 2532e78620bSAllen-KH Cheng 2542e78620bSAllen-KH Cheng l2_0: l2-cache0 { 2552e78620bSAllen-KH Cheng compatible = "cache"; 256ce459b1dSPierre Gondois cache-level = <2>; 25770282f31SAngeloGioacchino Del Regno cache-size = <131072>; 25870282f31SAngeloGioacchino Del Regno cache-line-size = <64>; 25970282f31SAngeloGioacchino Del Regno cache-sets = <512>; 2602e78620bSAllen-KH Cheng next-level-cache = <&l3_0>; 2612e78620bSAllen-KH Cheng }; 2622e78620bSAllen-KH Cheng 2632e78620bSAllen-KH Cheng l2_1: l2-cache1 { 2642e78620bSAllen-KH Cheng compatible = "cache"; 265ce459b1dSPierre Gondois cache-level = <2>; 26670282f31SAngeloGioacchino Del Regno cache-size = <262144>; 26770282f31SAngeloGioacchino Del Regno cache-line-size = <64>; 26870282f31SAngeloGioacchino Del Regno cache-sets = <512>; 2692e78620bSAllen-KH Cheng next-level-cache = <&l3_0>; 2702e78620bSAllen-KH Cheng }; 2712e78620bSAllen-KH Cheng 2722e78620bSAllen-KH Cheng l3_0: l3-cache { 2732e78620bSAllen-KH Cheng compatible = "cache"; 274ce459b1dSPierre Gondois cache-level = <3>; 27570282f31SAngeloGioacchino Del Regno cache-size = <1048576>; 27670282f31SAngeloGioacchino Del Regno cache-line-size = <64>; 27770282f31SAngeloGioacchino Del Regno cache-sets = <1024>; 27870282f31SAngeloGioacchino Del Regno cache-unified; 2792e78620bSAllen-KH Cheng }; 2802e78620bSAllen-KH Cheng }; 2812e78620bSAllen-KH Cheng 282b391efbaSChen-Yu Tsai clk13m: fixed-factor-clock-13m { 283b391efbaSChen-Yu Tsai compatible = "fixed-factor-clock"; 2842e78620bSAllen-KH Cheng #clock-cells = <0>; 285b391efbaSChen-Yu Tsai clocks = <&clk26m>; 286b391efbaSChen-Yu Tsai clock-div = <2>; 287b391efbaSChen-Yu Tsai clock-mult = <1>; 2882e78620bSAllen-KH Cheng clock-output-names = "clk13m"; 2892e78620bSAllen-KH Cheng }; 2902e78620bSAllen-KH Cheng 2912e78620bSAllen-KH Cheng clk26m: oscillator-26m { 2922e78620bSAllen-KH Cheng compatible = "fixed-clock"; 2932e78620bSAllen-KH Cheng #clock-cells = <0>; 2942e78620bSAllen-KH Cheng clock-frequency = <26000000>; 2952e78620bSAllen-KH Cheng clock-output-names = "clk26m"; 2962e78620bSAllen-KH Cheng }; 2972e78620bSAllen-KH Cheng 2982e78620bSAllen-KH Cheng clk32k: oscillator-32k { 2992e78620bSAllen-KH Cheng compatible = "fixed-clock"; 3002e78620bSAllen-KH Cheng #clock-cells = <0>; 3012e78620bSAllen-KH Cheng clock-frequency = <32768>; 3022e78620bSAllen-KH Cheng clock-output-names = "clk32k"; 3032e78620bSAllen-KH Cheng }; 3042e78620bSAllen-KH Cheng 3052e78620bSAllen-KH Cheng pmu-a55 { 3062e78620bSAllen-KH Cheng compatible = "arm,cortex-a55-pmu"; 3072e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 3082e78620bSAllen-KH Cheng interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 3092e78620bSAllen-KH Cheng }; 3102e78620bSAllen-KH Cheng 3112e78620bSAllen-KH Cheng pmu-a76 { 3122e78620bSAllen-KH Cheng compatible = "arm,cortex-a76-pmu"; 3132e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 3142e78620bSAllen-KH Cheng interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 3152e78620bSAllen-KH Cheng }; 3162e78620bSAllen-KH Cheng 3172e78620bSAllen-KH Cheng psci { 3182e78620bSAllen-KH Cheng compatible = "arm,psci-1.0"; 3192e78620bSAllen-KH Cheng method = "smc"; 3202e78620bSAllen-KH Cheng }; 3212e78620bSAllen-KH Cheng 3222e78620bSAllen-KH Cheng timer { 3232e78620bSAllen-KH Cheng compatible = "arm,armv8-timer"; 3242e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 3252e78620bSAllen-KH Cheng interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 3262e78620bSAllen-KH Cheng <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 3272e78620bSAllen-KH Cheng <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 3282e78620bSAllen-KH Cheng <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 3292e78620bSAllen-KH Cheng }; 3302e78620bSAllen-KH Cheng 3312e78620bSAllen-KH Cheng soc { 3322e78620bSAllen-KH Cheng #address-cells = <2>; 3332e78620bSAllen-KH Cheng #size-cells = <2>; 3342e78620bSAllen-KH Cheng compatible = "simple-bus"; 335f5430284SYong Wu dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 3362e78620bSAllen-KH Cheng ranges; 3372e78620bSAllen-KH Cheng 3382e78620bSAllen-KH Cheng gic: interrupt-controller@c000000 { 3392e78620bSAllen-KH Cheng compatible = "arm,gic-v3"; 3402e78620bSAllen-KH Cheng #interrupt-cells = <4>; 3412e78620bSAllen-KH Cheng #redistributor-regions = <1>; 3422e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 3432e78620bSAllen-KH Cheng interrupt-controller; 3442e78620bSAllen-KH Cheng reg = <0 0x0c000000 0 0x40000>, 3452e78620bSAllen-KH Cheng <0 0x0c040000 0 0x200000>; 3462e78620bSAllen-KH Cheng interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 3472e78620bSAllen-KH Cheng 3482e78620bSAllen-KH Cheng ppi-partitions { 3492e78620bSAllen-KH Cheng ppi_cluster0: interrupt-partition-0 { 3502e78620bSAllen-KH Cheng affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 3512e78620bSAllen-KH Cheng }; 3522e78620bSAllen-KH Cheng 3532e78620bSAllen-KH Cheng ppi_cluster1: interrupt-partition-1 { 3542e78620bSAllen-KH Cheng affinity = <&cpu6 &cpu7>; 3552e78620bSAllen-KH Cheng }; 3562e78620bSAllen-KH Cheng }; 3572e78620bSAllen-KH Cheng }; 3582e78620bSAllen-KH Cheng 3592e78620bSAllen-KH Cheng mcusys: syscon@c53a000 { 3602e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mcusys", "syscon"; 3612e78620bSAllen-KH Cheng reg = <0 0xc53a000 0 0x1000>; 3622e78620bSAllen-KH Cheng #clock-cells = <1>; 3632e78620bSAllen-KH Cheng }; 3642e78620bSAllen-KH Cheng 3652e78620bSAllen-KH Cheng topckgen: syscon@10000000 { 3662e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-topckgen", "syscon"; 3672e78620bSAllen-KH Cheng reg = <0 0x10000000 0 0x1000>; 3682e78620bSAllen-KH Cheng #clock-cells = <1>; 3692e78620bSAllen-KH Cheng }; 3702e78620bSAllen-KH Cheng 3712e78620bSAllen-KH Cheng infracfg_ao: syscon@10001000 { 3722e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 3732e78620bSAllen-KH Cheng reg = <0 0x10001000 0 0x1000>; 3742e78620bSAllen-KH Cheng #clock-cells = <1>; 3752e78620bSAllen-KH Cheng #reset-cells = <1>; 3762e78620bSAllen-KH Cheng }; 3772e78620bSAllen-KH Cheng 3782e78620bSAllen-KH Cheng pericfg: syscon@10003000 { 3792e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-pericfg", "syscon"; 3802e78620bSAllen-KH Cheng reg = <0 0x10003000 0 0x1000>; 3812e78620bSAllen-KH Cheng }; 3822e78620bSAllen-KH Cheng 3832e78620bSAllen-KH Cheng pio: pinctrl@10005000 { 3842e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-pinctrl"; 3852e78620bSAllen-KH Cheng reg = <0 0x10005000 0 0x1000>, 3862e78620bSAllen-KH Cheng <0 0x10002000 0 0x0200>, 3872e78620bSAllen-KH Cheng <0 0x10002200 0 0x0200>, 3882e78620bSAllen-KH Cheng <0 0x10002400 0 0x0200>, 3892e78620bSAllen-KH Cheng <0 0x10002600 0 0x0200>, 3902e78620bSAllen-KH Cheng <0 0x10002a00 0 0x0200>, 3912e78620bSAllen-KH Cheng <0 0x10002c00 0 0x0200>, 3922e78620bSAllen-KH Cheng <0 0x1000b000 0 0x1000>; 3932e78620bSAllen-KH Cheng reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 3942e78620bSAllen-KH Cheng "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 3952e78620bSAllen-KH Cheng gpio-controller; 3962e78620bSAllen-KH Cheng #gpio-cells = <2>; 3972e78620bSAllen-KH Cheng gpio-ranges = <&pio 0 0 185>; 3982e78620bSAllen-KH Cheng interrupt-controller; 3992e78620bSAllen-KH Cheng interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 4002e78620bSAllen-KH Cheng #interrupt-cells = <2>; 4012e78620bSAllen-KH Cheng }; 4022e78620bSAllen-KH Cheng 403d9e43c1eSAllen-KH Cheng scpsys: syscon@10006000 { 404d9e43c1eSAllen-KH Cheng compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 405d9e43c1eSAllen-KH Cheng reg = <0 0x10006000 0 0x1000>; 406d9e43c1eSAllen-KH Cheng 407d9e43c1eSAllen-KH Cheng /* System Power Manager */ 408d9e43c1eSAllen-KH Cheng spm: power-controller { 409d9e43c1eSAllen-KH Cheng compatible = "mediatek,mt8186-power-controller"; 410d9e43c1eSAllen-KH Cheng #address-cells = <1>; 411d9e43c1eSAllen-KH Cheng #size-cells = <0>; 412d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 413d9e43c1eSAllen-KH Cheng 414d9e43c1eSAllen-KH Cheng /* power domain of the SoC */ 415d9e43c1eSAllen-KH Cheng mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 416d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_MFG0>; 417d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MFG>; 418d9e43c1eSAllen-KH Cheng clock-names = "mfg00"; 419d9e43c1eSAllen-KH Cheng #address-cells = <1>; 420d9e43c1eSAllen-KH Cheng #size-cells = <0>; 421d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 422d9e43c1eSAllen-KH Cheng 423d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_MFG1 { 424d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_MFG1>; 425d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 426d9e43c1eSAllen-KH Cheng #address-cells = <1>; 427d9e43c1eSAllen-KH Cheng #size-cells = <0>; 428d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 429d9e43c1eSAllen-KH Cheng 430d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_MFG2 { 431d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_MFG2>; 432d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 433d9e43c1eSAllen-KH Cheng }; 434d9e43c1eSAllen-KH Cheng 435d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_MFG3 { 436d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_MFG3>; 437d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 438d9e43c1eSAllen-KH Cheng }; 439d9e43c1eSAllen-KH Cheng }; 440d9e43c1eSAllen-KH Cheng }; 441d9e43c1eSAllen-KH Cheng 442d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 443d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 444d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_SENINF>, 445d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_SENINF1>; 446d9e43c1eSAllen-KH Cheng clock-names = "csirx_top0", "csirx_top1"; 447d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 448d9e43c1eSAllen-KH Cheng }; 449d9e43c1eSAllen-KH Cheng 450d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_SSUSB { 451d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_SSUSB>; 452d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 453d9e43c1eSAllen-KH Cheng }; 454d9e43c1eSAllen-KH Cheng 455d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 456d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 457d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 458d9e43c1eSAllen-KH Cheng }; 459d9e43c1eSAllen-KH Cheng 460d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 461d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 462d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_AUDIODSP>, 463d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_ADSP_BUS>; 464d9e43c1eSAllen-KH Cheng clock-names = "audioadsp", "adsp_bus"; 465d9e43c1eSAllen-KH Cheng #address-cells = <1>; 466d9e43c1eSAllen-KH Cheng #size-cells = <0>; 467d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 468d9e43c1eSAllen-KH Cheng 469d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 470d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 471d9e43c1eSAllen-KH Cheng #address-cells = <1>; 472d9e43c1eSAllen-KH Cheng #size-cells = <0>; 473d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 474d9e43c1eSAllen-KH Cheng 475d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 476d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 477d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 478d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 479d9e43c1eSAllen-KH Cheng }; 480d9e43c1eSAllen-KH Cheng }; 481d9e43c1eSAllen-KH Cheng }; 482d9e43c1eSAllen-KH Cheng 483d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CONN_ON { 484d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CONN_ON>; 485d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 486d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 487d9e43c1eSAllen-KH Cheng }; 488d9e43c1eSAllen-KH Cheng 489d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_DIS { 490d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_DIS>; 491d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP>, 492d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_MDP>, 493d9e43c1eSAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 494d9e43c1eSAllen-KH Cheng <&mmsys CLK_MM_SMI_COMMON>, 495d9e43c1eSAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 496d9e43c1eSAllen-KH Cheng <&mmsys CLK_MM_SMI_IOMMU>; 497d9e43c1eSAllen-KH Cheng clock-names = "disp", "mdp", "smi_infra", "smi_common", 498d9e43c1eSAllen-KH Cheng "smi_gals", "smi_iommu"; 499d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 500d9e43c1eSAllen-KH Cheng #address-cells = <1>; 501d9e43c1eSAllen-KH Cheng #size-cells = <0>; 502d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 503d9e43c1eSAllen-KH Cheng 504d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_VDEC { 505d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_VDEC>; 506d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_VDEC>, 507d9e43c1eSAllen-KH Cheng <&vdecsys CLK_VDEC_LARB1_CKEN>; 508d9e43c1eSAllen-KH Cheng clock-names = "vdec0", "larb"; 509d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 510d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 511d9e43c1eSAllen-KH Cheng }; 512d9e43c1eSAllen-KH Cheng 513d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CAM { 514d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CAM>; 515d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_CAM>, 516d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_SENINF>, 517d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_SENINF1>, 518d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_SENINF2>, 519d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_SENINF3>, 520d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_CAMTM>, 521d9e43c1eSAllen-KH Cheng <&camsys CLK_CAM2MM_GALS>; 522d9e43c1eSAllen-KH Cheng clock-names = "cam-top", "cam0", "cam1", "cam2", 523d9e43c1eSAllen-KH Cheng "cam3", "cam-tm", "gals"; 524d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 525d9e43c1eSAllen-KH Cheng #address-cells = <1>; 526d9e43c1eSAllen-KH Cheng #size-cells = <0>; 527d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 528d9e43c1eSAllen-KH Cheng 529d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 530d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 531d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 532d9e43c1eSAllen-KH Cheng }; 533d9e43c1eSAllen-KH Cheng 534d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 535d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 536d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 537d9e43c1eSAllen-KH Cheng }; 538d9e43c1eSAllen-KH Cheng }; 539d9e43c1eSAllen-KH Cheng 540d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_IMG { 541d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_IMG>; 542d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_IMG1>, 543d9e43c1eSAllen-KH Cheng <&imgsys1 CLK_IMG1_GALS_IMG1>; 544d9e43c1eSAllen-KH Cheng clock-names = "img-top", "gals"; 545d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 546d9e43c1eSAllen-KH Cheng #address-cells = <1>; 547d9e43c1eSAllen-KH Cheng #size-cells = <0>; 548d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 549d9e43c1eSAllen-KH Cheng 550d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_IMG2 { 551d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_IMG2>; 552d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 553d9e43c1eSAllen-KH Cheng }; 554d9e43c1eSAllen-KH Cheng }; 555d9e43c1eSAllen-KH Cheng 556d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_IPE { 557d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_IPE>; 558d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_IPE>, 559d9e43c1eSAllen-KH Cheng <&ipesys CLK_IPE_LARB19>, 560d9e43c1eSAllen-KH Cheng <&ipesys CLK_IPE_LARB20>, 561d9e43c1eSAllen-KH Cheng <&ipesys CLK_IPE_SMI_SUBCOM>, 562d9e43c1eSAllen-KH Cheng <&ipesys CLK_IPE_GALS_IPE>; 563d9e43c1eSAllen-KH Cheng clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 564d9e43c1eSAllen-KH Cheng "ipe-smi", "ipe-gals"; 565d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 566d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 567d9e43c1eSAllen-KH Cheng }; 568d9e43c1eSAllen-KH Cheng 569d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_VENC { 570d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_VENC>; 571d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_VENC>, 572d9e43c1eSAllen-KH Cheng <&vencsys CLK_VENC_CKE1_VENC>; 573d9e43c1eSAllen-KH Cheng clock-names = "venc0", "larb"; 574d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 575d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 576d9e43c1eSAllen-KH Cheng }; 577d9e43c1eSAllen-KH Cheng 578d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_WPE { 579d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_WPE>; 580d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_WPE>, 581d9e43c1eSAllen-KH Cheng <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 582d9e43c1eSAllen-KH Cheng <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 583d9e43c1eSAllen-KH Cheng clock-names = "wpe0", "larb-ck", "larb-pclk"; 584d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 585d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 586d9e43c1eSAllen-KH Cheng }; 587d9e43c1eSAllen-KH Cheng }; 588d9e43c1eSAllen-KH Cheng }; 589d9e43c1eSAllen-KH Cheng }; 590d9e43c1eSAllen-KH Cheng 5912e78620bSAllen-KH Cheng watchdog: watchdog@10007000 { 592e5e96162SAngeloGioacchino Del Regno compatible = "mediatek,mt8186-wdt"; 5932e78620bSAllen-KH Cheng mediatek,disable-extrst; 5942e78620bSAllen-KH Cheng reg = <0 0x10007000 0 0x1000>; 5952e78620bSAllen-KH Cheng #reset-cells = <1>; 5962e78620bSAllen-KH Cheng }; 5972e78620bSAllen-KH Cheng 5982e78620bSAllen-KH Cheng apmixedsys: syscon@1000c000 { 5992e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-apmixedsys", "syscon"; 6002e78620bSAllen-KH Cheng reg = <0 0x1000c000 0 0x1000>; 6012e78620bSAllen-KH Cheng #clock-cells = <1>; 6022e78620bSAllen-KH Cheng }; 6032e78620bSAllen-KH Cheng 6042e78620bSAllen-KH Cheng pwrap: pwrap@1000d000 { 6052e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-pwrap", "syscon"; 6062e78620bSAllen-KH Cheng reg = <0 0x1000d000 0 0x1000>; 6072e78620bSAllen-KH Cheng reg-names = "pwrap"; 6082e78620bSAllen-KH Cheng interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 6092e78620bSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 6102e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 6112e78620bSAllen-KH Cheng clock-names = "spi", "wrap"; 6122e78620bSAllen-KH Cheng }; 6132e78620bSAllen-KH Cheng 61436cfc08fSAllen-KH Cheng spmi: spmi@10015000 { 61536cfc08fSAllen-KH Cheng compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 61636cfc08fSAllen-KH Cheng reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 61736cfc08fSAllen-KH Cheng reg-names = "pmif", "spmimst"; 61836cfc08fSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 61936cfc08fSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 62036cfc08fSAllen-KH Cheng <&topckgen CLK_TOP_SPMI_MST>; 62136cfc08fSAllen-KH Cheng clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 62236cfc08fSAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 62336cfc08fSAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 62436cfc08fSAllen-KH Cheng interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 62536cfc08fSAllen-KH Cheng <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 62636cfc08fSAllen-KH Cheng status = "disabled"; 62736cfc08fSAllen-KH Cheng }; 62836cfc08fSAllen-KH Cheng 6292e78620bSAllen-KH Cheng systimer: timer@10017000 { 6302e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-timer", 6312e78620bSAllen-KH Cheng "mediatek,mt6765-timer"; 6322e78620bSAllen-KH Cheng reg = <0 0x10017000 0 0x1000>; 6332e78620bSAllen-KH Cheng interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 6342e78620bSAllen-KH Cheng clocks = <&clk13m>; 6352e78620bSAllen-KH Cheng }; 6362e78620bSAllen-KH Cheng 63741218847SAllen-KH Cheng gce: mailbox@1022c000 { 63841218847SAllen-KH Cheng compatible = "mediatek,mt8186-gce"; 63941218847SAllen-KH Cheng reg = <0 0X1022c000 0 0x4000>; 64041218847SAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 64141218847SAllen-KH Cheng clock-names = "gce"; 64241218847SAllen-KH Cheng interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 64341218847SAllen-KH Cheng #mbox-cells = <2>; 64441218847SAllen-KH Cheng }; 64541218847SAllen-KH Cheng 6462e78620bSAllen-KH Cheng scp: scp@10500000 { 6472e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-scp"; 6482e78620bSAllen-KH Cheng reg = <0 0x10500000 0 0x40000>, 6492e78620bSAllen-KH Cheng <0 0x105c0000 0 0x19080>; 6502e78620bSAllen-KH Cheng reg-names = "sram", "cfg"; 6512e78620bSAllen-KH Cheng interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 6522e78620bSAllen-KH Cheng }; 6532e78620bSAllen-KH Cheng 6544dad4f32SAllen-KH Cheng adsp: adsp@10680000 { 6554dad4f32SAllen-KH Cheng compatible = "mediatek,mt8186-dsp"; 6564dad4f32SAllen-KH Cheng reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 6574dad4f32SAllen-KH Cheng <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 6584dad4f32SAllen-KH Cheng reg-names = "cfg", "sram", "sec", "bus"; 6594dad4f32SAllen-KH Cheng clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 6604dad4f32SAllen-KH Cheng clock-names = "audiodsp", "adsp_bus"; 6614dad4f32SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 6624dad4f32SAllen-KH Cheng <&topckgen CLK_TOP_ADSP_BUS>; 6634dad4f32SAllen-KH Cheng assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 6644dad4f32SAllen-KH Cheng mbox-names = "rx", "tx"; 6654dad4f32SAllen-KH Cheng mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 6664dad4f32SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 6674dad4f32SAllen-KH Cheng status = "disabled"; 6684dad4f32SAllen-KH Cheng }; 6694dad4f32SAllen-KH Cheng 670379cf0e6SAllen-KH Cheng adsp_mailbox0: mailbox@10686000 { 671379cf0e6SAllen-KH Cheng compatible = "mediatek,mt8186-adsp-mbox"; 672379cf0e6SAllen-KH Cheng #mbox-cells = <0>; 673379cf0e6SAllen-KH Cheng reg = <0 0x10686100 0 0x1000>; 674379cf0e6SAllen-KH Cheng interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 675379cf0e6SAllen-KH Cheng }; 676379cf0e6SAllen-KH Cheng 677379cf0e6SAllen-KH Cheng adsp_mailbox1: mailbox@10687000 { 678379cf0e6SAllen-KH Cheng compatible = "mediatek,mt8186-adsp-mbox"; 679379cf0e6SAllen-KH Cheng #mbox-cells = <0>; 680379cf0e6SAllen-KH Cheng reg = <0 0x10687100 0 0x1000>; 681379cf0e6SAllen-KH Cheng interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 682379cf0e6SAllen-KH Cheng }; 683379cf0e6SAllen-KH Cheng 6842e78620bSAllen-KH Cheng nor_flash: spi@11000000 { 6852e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-nor"; 6862e78620bSAllen-KH Cheng reg = <0 0x11000000 0 0x1000>; 6872e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_SPINOR>, 6882e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPINOR>, 6892e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 6902e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 6912e78620bSAllen-KH Cheng clock-names = "spi", "sf", "axi", "axi_s"; 6922e78620bSAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 6932e78620bSAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 6942e78620bSAllen-KH Cheng interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 6952e78620bSAllen-KH Cheng status = "disabled"; 6962e78620bSAllen-KH Cheng }; 6972e78620bSAllen-KH Cheng 6982e78620bSAllen-KH Cheng auxadc: adc@11001000 { 6992e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 7002e78620bSAllen-KH Cheng reg = <0 0x11001000 0 0x1000>; 7012e78620bSAllen-KH Cheng #io-channel-cells = <1>; 7022e78620bSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 7032e78620bSAllen-KH Cheng clock-names = "main"; 7042e78620bSAllen-KH Cheng }; 7052e78620bSAllen-KH Cheng 7062e78620bSAllen-KH Cheng uart0: serial@11002000 { 7072e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-uart", 7082e78620bSAllen-KH Cheng "mediatek,mt6577-uart"; 7092e78620bSAllen-KH Cheng reg = <0 0x11002000 0 0x1000>; 7102e78620bSAllen-KH Cheng interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 7112e78620bSAllen-KH Cheng clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 7122e78620bSAllen-KH Cheng clock-names = "baud", "bus"; 7132e78620bSAllen-KH Cheng status = "disabled"; 7142e78620bSAllen-KH Cheng }; 7152e78620bSAllen-KH Cheng 7162e78620bSAllen-KH Cheng uart1: serial@11003000 { 7172e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-uart", 7182e78620bSAllen-KH Cheng "mediatek,mt6577-uart"; 7192e78620bSAllen-KH Cheng reg = <0 0x11003000 0 0x1000>; 7202e78620bSAllen-KH Cheng interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 7212e78620bSAllen-KH Cheng clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 7222e78620bSAllen-KH Cheng clock-names = "baud", "bus"; 7232e78620bSAllen-KH Cheng status = "disabled"; 7242e78620bSAllen-KH Cheng }; 7252e78620bSAllen-KH Cheng 7262e78620bSAllen-KH Cheng i2c0: i2c@11007000 { 7272e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 7282e78620bSAllen-KH Cheng reg = <0 0x11007000 0 0x1000>, 7292e78620bSAllen-KH Cheng <0 0x10200100 0 0x100>; 7302e78620bSAllen-KH Cheng interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 7312e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 7322e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 7332e78620bSAllen-KH Cheng clock-names = "main", "dma"; 7342e78620bSAllen-KH Cheng clock-div = <1>; 7352e78620bSAllen-KH Cheng #address-cells = <1>; 7362e78620bSAllen-KH Cheng #size-cells = <0>; 7372e78620bSAllen-KH Cheng status = "disabled"; 7382e78620bSAllen-KH Cheng }; 7392e78620bSAllen-KH Cheng 7402e78620bSAllen-KH Cheng i2c1: i2c@11008000 { 7412e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 7422e78620bSAllen-KH Cheng reg = <0 0x11008000 0 0x1000>, 7432e78620bSAllen-KH Cheng <0 0x10200200 0 0x100>; 7442e78620bSAllen-KH Cheng interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 7452e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 7462e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 7472e78620bSAllen-KH Cheng clock-names = "main", "dma"; 7482e78620bSAllen-KH Cheng clock-div = <1>; 7492e78620bSAllen-KH Cheng #address-cells = <1>; 7502e78620bSAllen-KH Cheng #size-cells = <0>; 7512e78620bSAllen-KH Cheng status = "disabled"; 7522e78620bSAllen-KH Cheng }; 7532e78620bSAllen-KH Cheng 7542e78620bSAllen-KH Cheng i2c2: i2c@11009000 { 7552e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 7562e78620bSAllen-KH Cheng reg = <0 0x11009000 0 0x1000>, 7572e78620bSAllen-KH Cheng <0 0x10200300 0 0x180>; 7582e78620bSAllen-KH Cheng interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 7592e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 7602e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 7612e78620bSAllen-KH Cheng clock-names = "main", "dma"; 7622e78620bSAllen-KH Cheng clock-div = <1>; 7632e78620bSAllen-KH Cheng #address-cells = <1>; 7642e78620bSAllen-KH Cheng #size-cells = <0>; 7652e78620bSAllen-KH Cheng status = "disabled"; 7662e78620bSAllen-KH Cheng }; 7672e78620bSAllen-KH Cheng 7682e78620bSAllen-KH Cheng i2c3: i2c@1100f000 { 7692e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 7702e78620bSAllen-KH Cheng reg = <0 0x1100f000 0 0x1000>, 7712e78620bSAllen-KH Cheng <0 0x10200480 0 0x100>; 7722e78620bSAllen-KH Cheng interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 7732e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 7742e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 7752e78620bSAllen-KH Cheng clock-names = "main", "dma"; 7762e78620bSAllen-KH Cheng clock-div = <1>; 7772e78620bSAllen-KH Cheng #address-cells = <1>; 7782e78620bSAllen-KH Cheng #size-cells = <0>; 7792e78620bSAllen-KH Cheng status = "disabled"; 7802e78620bSAllen-KH Cheng }; 7812e78620bSAllen-KH Cheng 7822e78620bSAllen-KH Cheng i2c4: i2c@11011000 { 7832e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 7842e78620bSAllen-KH Cheng reg = <0 0x11011000 0 0x1000>, 7852e78620bSAllen-KH Cheng <0 0x10200580 0 0x180>; 7862e78620bSAllen-KH Cheng interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 7872e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 7882e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 7892e78620bSAllen-KH Cheng clock-names = "main", "dma"; 7902e78620bSAllen-KH Cheng clock-div = <1>; 7912e78620bSAllen-KH Cheng #address-cells = <1>; 7922e78620bSAllen-KH Cheng #size-cells = <0>; 7932e78620bSAllen-KH Cheng status = "disabled"; 7942e78620bSAllen-KH Cheng }; 7952e78620bSAllen-KH Cheng 7962e78620bSAllen-KH Cheng i2c5: i2c@11016000 { 7972e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 7982e78620bSAllen-KH Cheng reg = <0 0x11016000 0 0x1000>, 7992e78620bSAllen-KH Cheng <0 0x10200700 0 0x100>; 8002e78620bSAllen-KH Cheng interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 8012e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 8022e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 8032e78620bSAllen-KH Cheng clock-names = "main", "dma"; 8042e78620bSAllen-KH Cheng clock-div = <1>; 8052e78620bSAllen-KH Cheng #address-cells = <1>; 8062e78620bSAllen-KH Cheng #size-cells = <0>; 8072e78620bSAllen-KH Cheng status = "disabled"; 8082e78620bSAllen-KH Cheng }; 8092e78620bSAllen-KH Cheng 8102e78620bSAllen-KH Cheng i2c6: i2c@1100d000 { 8112e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 8122e78620bSAllen-KH Cheng reg = <0 0x1100d000 0 0x1000>, 8132e78620bSAllen-KH Cheng <0 0x10200800 0 0x100>; 8142e78620bSAllen-KH Cheng interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 8152e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 8162e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 8172e78620bSAllen-KH Cheng clock-names = "main", "dma"; 8182e78620bSAllen-KH Cheng clock-div = <1>; 8192e78620bSAllen-KH Cheng #address-cells = <1>; 8202e78620bSAllen-KH Cheng #size-cells = <0>; 8212e78620bSAllen-KH Cheng status = "disabled"; 8222e78620bSAllen-KH Cheng }; 8232e78620bSAllen-KH Cheng 8242e78620bSAllen-KH Cheng i2c7: i2c@11004000 { 8252e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 8262e78620bSAllen-KH Cheng reg = <0 0x11004000 0 0x1000>, 8272e78620bSAllen-KH Cheng <0 0x10200900 0 0x180>; 8282e78620bSAllen-KH Cheng interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 8292e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 8302e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 8312e78620bSAllen-KH Cheng clock-names = "main", "dma"; 8322e78620bSAllen-KH Cheng clock-div = <1>; 8332e78620bSAllen-KH Cheng #address-cells = <1>; 8342e78620bSAllen-KH Cheng #size-cells = <0>; 8352e78620bSAllen-KH Cheng status = "disabled"; 8362e78620bSAllen-KH Cheng }; 8372e78620bSAllen-KH Cheng 8382e78620bSAllen-KH Cheng i2c8: i2c@11005000 { 8392e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 8402e78620bSAllen-KH Cheng reg = <0 0x11005000 0 0x1000>, 8412e78620bSAllen-KH Cheng <0 0x10200A80 0 0x180>; 8422e78620bSAllen-KH Cheng interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 8432e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 8442e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 8452e78620bSAllen-KH Cheng clock-names = "main", "dma"; 8462e78620bSAllen-KH Cheng clock-div = <1>; 8472e78620bSAllen-KH Cheng #address-cells = <1>; 8482e78620bSAllen-KH Cheng #size-cells = <0>; 8492e78620bSAllen-KH Cheng status = "disabled"; 8502e78620bSAllen-KH Cheng }; 8512e78620bSAllen-KH Cheng 8522e78620bSAllen-KH Cheng spi0: spi@1100a000 { 8532e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 8542e78620bSAllen-KH Cheng #address-cells = <1>; 8552e78620bSAllen-KH Cheng #size-cells = <0>; 8562e78620bSAllen-KH Cheng reg = <0 0x1100a000 0 0x1000>; 8572e78620bSAllen-KH Cheng interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 8582e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 8592e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 8602e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI0>; 8612e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 8622e78620bSAllen-KH Cheng status = "disabled"; 8632e78620bSAllen-KH Cheng }; 8642e78620bSAllen-KH Cheng 8652e78620bSAllen-KH Cheng pwm0: pwm@1100e000 { 8662e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 8672e78620bSAllen-KH Cheng reg = <0 0x1100e000 0 0x1000>; 8682e78620bSAllen-KH Cheng interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 8692e78620bSAllen-KH Cheng #pwm-cells = <2>; 8702e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP_PWM>, 8712e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 8722e78620bSAllen-KH Cheng clock-names = "main", "mm"; 8732e78620bSAllen-KH Cheng status = "disabled"; 8742e78620bSAllen-KH Cheng }; 8752e78620bSAllen-KH Cheng 8762e78620bSAllen-KH Cheng spi1: spi@11010000 { 8772e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 8782e78620bSAllen-KH Cheng #address-cells = <1>; 8792e78620bSAllen-KH Cheng #size-cells = <0>; 8802e78620bSAllen-KH Cheng reg = <0 0x11010000 0 0x1000>; 8812e78620bSAllen-KH Cheng interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 8822e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 8832e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 8842e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI1>; 8852e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 8862e78620bSAllen-KH Cheng status = "disabled"; 8872e78620bSAllen-KH Cheng }; 8882e78620bSAllen-KH Cheng 8892e78620bSAllen-KH Cheng spi2: spi@11012000 { 8902e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 8912e78620bSAllen-KH Cheng #address-cells = <1>; 8922e78620bSAllen-KH Cheng #size-cells = <0>; 8932e78620bSAllen-KH Cheng reg = <0 0x11012000 0 0x1000>; 8942e78620bSAllen-KH Cheng interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 8952e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 8962e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 8972e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI2>; 8982e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 8992e78620bSAllen-KH Cheng status = "disabled"; 9002e78620bSAllen-KH Cheng }; 9012e78620bSAllen-KH Cheng 9022e78620bSAllen-KH Cheng spi3: spi@11013000 { 9032e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 9042e78620bSAllen-KH Cheng #address-cells = <1>; 9052e78620bSAllen-KH Cheng #size-cells = <0>; 9062e78620bSAllen-KH Cheng reg = <0 0x11013000 0 0x1000>; 9072e78620bSAllen-KH Cheng interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 9082e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 9092e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 9102e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI3>; 9112e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 9122e78620bSAllen-KH Cheng status = "disabled"; 9132e78620bSAllen-KH Cheng }; 9142e78620bSAllen-KH Cheng 9152e78620bSAllen-KH Cheng spi4: spi@11014000 { 9162e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 9172e78620bSAllen-KH Cheng #address-cells = <1>; 9182e78620bSAllen-KH Cheng #size-cells = <0>; 9192e78620bSAllen-KH Cheng reg = <0 0x11014000 0 0x1000>; 9202e78620bSAllen-KH Cheng interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 9212e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 9222e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 9232e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI4>; 9242e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 9252e78620bSAllen-KH Cheng status = "disabled"; 9262e78620bSAllen-KH Cheng }; 9272e78620bSAllen-KH Cheng 9282e78620bSAllen-KH Cheng spi5: spi@11015000 { 9292e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 9302e78620bSAllen-KH Cheng #address-cells = <1>; 9312e78620bSAllen-KH Cheng #size-cells = <0>; 9322e78620bSAllen-KH Cheng reg = <0 0x11015000 0 0x1000>; 9332e78620bSAllen-KH Cheng interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 9342e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 9352e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 9362e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI5>; 9372e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 9382e78620bSAllen-KH Cheng status = "disabled"; 9392e78620bSAllen-KH Cheng }; 9402e78620bSAllen-KH Cheng 9412e78620bSAllen-KH Cheng imp_iic_wrap: clock-controller@11017000 { 9422e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-imp_iic_wrap"; 9432e78620bSAllen-KH Cheng reg = <0 0x11017000 0 0x1000>; 9442e78620bSAllen-KH Cheng #clock-cells = <1>; 9452e78620bSAllen-KH Cheng }; 9462e78620bSAllen-KH Cheng 9472e78620bSAllen-KH Cheng uart2: serial@11018000 { 9482e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-uart", 9492e78620bSAllen-KH Cheng "mediatek,mt6577-uart"; 9502e78620bSAllen-KH Cheng reg = <0 0x11018000 0 0x1000>; 9512e78620bSAllen-KH Cheng interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 9522e78620bSAllen-KH Cheng clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 9532e78620bSAllen-KH Cheng clock-names = "baud", "bus"; 9542e78620bSAllen-KH Cheng status = "disabled"; 9552e78620bSAllen-KH Cheng }; 9562e78620bSAllen-KH Cheng 9572e78620bSAllen-KH Cheng i2c9: i2c@11019000 { 9582e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 9592e78620bSAllen-KH Cheng reg = <0 0x11019000 0 0x1000>, 9602e78620bSAllen-KH Cheng <0 0x10200c00 0 0x180>; 9612e78620bSAllen-KH Cheng interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 9622e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 9632e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 9642e78620bSAllen-KH Cheng clock-names = "main", "dma"; 9652e78620bSAllen-KH Cheng clock-div = <1>; 9662e78620bSAllen-KH Cheng #address-cells = <1>; 9672e78620bSAllen-KH Cheng #size-cells = <0>; 9682e78620bSAllen-KH Cheng status = "disabled"; 9692e78620bSAllen-KH Cheng }; 9702e78620bSAllen-KH Cheng 97118942d29SAllen-KH Cheng afe: audio-controller@11210000 { 97218942d29SAllen-KH Cheng compatible = "mediatek,mt8186-sound"; 97318942d29SAllen-KH Cheng reg = <0 0x11210000 0 0x2000>; 97418942d29SAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 97518942d29SAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 97618942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO>, 97718942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_INTBUS>, 97818942d29SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D2_D4>, 97918942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_1>, 98018942d29SAllen-KH Cheng <&apmixedsys CLK_APMIXED_APLL1>, 98118942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_2>, 98218942d29SAllen-KH Cheng <&apmixedsys CLK_APMIXED_APLL2>, 98318942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN1>, 98418942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL1_D8>, 98518942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN2>, 98618942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL2_D8>, 98718942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 98818942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 98918942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 99018942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 99118942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 99218942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV0>, 99318942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV1>, 99418942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV2>, 99518942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV4>, 99618942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 99718942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_H>, 99818942d29SAllen-KH Cheng <&clk26m>; 99918942d29SAllen-KH Cheng clock-names = "aud_infra_clk", 100018942d29SAllen-KH Cheng "mtkaif_26m_clk", 100118942d29SAllen-KH Cheng "top_mux_audio", 100218942d29SAllen-KH Cheng "top_mux_audio_int", 100318942d29SAllen-KH Cheng "top_mainpll_d2_d4", 100418942d29SAllen-KH Cheng "top_mux_aud_1", 100518942d29SAllen-KH Cheng "top_apll1_ck", 100618942d29SAllen-KH Cheng "top_mux_aud_2", 100718942d29SAllen-KH Cheng "top_apll2_ck", 100818942d29SAllen-KH Cheng "top_mux_aud_eng1", 100918942d29SAllen-KH Cheng "top_apll1_d8", 101018942d29SAllen-KH Cheng "top_mux_aud_eng2", 101118942d29SAllen-KH Cheng "top_apll2_d8", 101218942d29SAllen-KH Cheng "top_i2s0_m_sel", 101318942d29SAllen-KH Cheng "top_i2s1_m_sel", 101418942d29SAllen-KH Cheng "top_i2s2_m_sel", 101518942d29SAllen-KH Cheng "top_i2s4_m_sel", 101618942d29SAllen-KH Cheng "top_tdm_m_sel", 101718942d29SAllen-KH Cheng "top_apll12_div0", 101818942d29SAllen-KH Cheng "top_apll12_div1", 101918942d29SAllen-KH Cheng "top_apll12_div2", 102018942d29SAllen-KH Cheng "top_apll12_div4", 102118942d29SAllen-KH Cheng "top_apll12_div_tdm", 102218942d29SAllen-KH Cheng "top_mux_audio_h", 102318942d29SAllen-KH Cheng "top_clk26m_clk"; 102418942d29SAllen-KH Cheng interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 102518942d29SAllen-KH Cheng mediatek,apmixedsys = <&apmixedsys>; 102618942d29SAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 102718942d29SAllen-KH Cheng mediatek,topckgen = <&topckgen>; 102818942d29SAllen-KH Cheng resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 102918942d29SAllen-KH Cheng reset-names = "audiosys"; 103018942d29SAllen-KH Cheng status = "disabled"; 103118942d29SAllen-KH Cheng }; 103218942d29SAllen-KH Cheng 1033f6c3e61cSAllen-KH Cheng ssusb0: usb@11201000 { 1034f6c3e61cSAllen-KH Cheng compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1035f6c3e61cSAllen-KH Cheng reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1036f6c3e61cSAllen-KH Cheng reg-names = "mac", "ippc"; 1037f6c3e61cSAllen-KH Cheng clocks = <&topckgen CLK_TOP_USB_TOP>, 1038f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1039f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1040f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_ICUSB>; 1041f6c3e61cSAllen-KH Cheng clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1042f6c3e61cSAllen-KH Cheng interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1043f6c3e61cSAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>; 1044f6c3e61cSAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1045f6c3e61cSAllen-KH Cheng #address-cells = <2>; 1046f6c3e61cSAllen-KH Cheng #size-cells = <2>; 1047f6c3e61cSAllen-KH Cheng ranges; 1048f6c3e61cSAllen-KH Cheng status = "disabled"; 1049f6c3e61cSAllen-KH Cheng 1050f6c3e61cSAllen-KH Cheng usb_host0: usb@11200000 { 1051f6c3e61cSAllen-KH Cheng compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1052f6c3e61cSAllen-KH Cheng reg = <0 0x11200000 0 0x1000>; 1053f6c3e61cSAllen-KH Cheng reg-names = "mac"; 1054f6c3e61cSAllen-KH Cheng clocks = <&topckgen CLK_TOP_USB_TOP>, 1055f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1056f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1057f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1058f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1059f6c3e61cSAllen-KH Cheng clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1060f6c3e61cSAllen-KH Cheng interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1061f6c3e61cSAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1062f6c3e61cSAllen-KH Cheng wakeup-source; 1063f6c3e61cSAllen-KH Cheng status = "disabled"; 1064f6c3e61cSAllen-KH Cheng }; 1065f6c3e61cSAllen-KH Cheng }; 1066f6c3e61cSAllen-KH Cheng 10672e78620bSAllen-KH Cheng mmc0: mmc@11230000 { 10682e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mmc", 10692e78620bSAllen-KH Cheng "mediatek,mt8183-mmc"; 1070558741f8SAllen-KH Cheng reg = <0 0x11230000 0 0x10000>, 10712e78620bSAllen-KH Cheng <0 0x11cd0000 0 0x1000>; 10722e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC50_0>, 10732e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1074558741f8SAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1075558741f8SAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1076558741f8SAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "crypto"; 10772e78620bSAllen-KH Cheng interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 10782e78620bSAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 10792e78620bSAllen-KH Cheng assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 10802e78620bSAllen-KH Cheng status = "disabled"; 10812e78620bSAllen-KH Cheng }; 10822e78620bSAllen-KH Cheng 10832e78620bSAllen-KH Cheng mmc1: mmc@11240000 { 10842e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mmc", 10852e78620bSAllen-KH Cheng "mediatek,mt8183-mmc"; 10862e78620bSAllen-KH Cheng reg = <0 0x11240000 0 0x1000>, 10872e78620bSAllen-KH Cheng <0 0x11c90000 0 0x1000>; 10882e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC30_1>, 10892e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDC1>, 10902e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 10912e78620bSAllen-KH Cheng clock-names = "source", "hclk", "source_cg"; 10922e78620bSAllen-KH Cheng interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 10932e78620bSAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 10942e78620bSAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 10952e78620bSAllen-KH Cheng status = "disabled"; 10962e78620bSAllen-KH Cheng }; 10972e78620bSAllen-KH Cheng 1098f6c3e61cSAllen-KH Cheng ssusb1: usb@11281000 { 1099f6c3e61cSAllen-KH Cheng compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1100f6c3e61cSAllen-KH Cheng reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1101f6c3e61cSAllen-KH Cheng reg-names = "mac", "ippc"; 1102f6c3e61cSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1103f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1104f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1105f6c3e61cSAllen-KH Cheng <&clk26m>; 1106f6c3e61cSAllen-KH Cheng clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1107f6c3e61cSAllen-KH Cheng interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1108f6c3e61cSAllen-KH Cheng phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1109f6c3e61cSAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1110f6c3e61cSAllen-KH Cheng #address-cells = <2>; 1111f6c3e61cSAllen-KH Cheng #size-cells = <2>; 1112f6c3e61cSAllen-KH Cheng ranges; 1113f6c3e61cSAllen-KH Cheng status = "disabled"; 1114f6c3e61cSAllen-KH Cheng 1115f6c3e61cSAllen-KH Cheng usb_host1: usb@11280000 { 1116f6c3e61cSAllen-KH Cheng compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1117f6c3e61cSAllen-KH Cheng reg = <0 0x11280000 0 0x1000>; 1118f6c3e61cSAllen-KH Cheng reg-names = "mac"; 1119f6c3e61cSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1120f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1121f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1122f6c3e61cSAllen-KH Cheng <&clk26m>, 1123f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1124f6c3e61cSAllen-KH Cheng clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1125f6c3e61cSAllen-KH Cheng interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1126f6c3e61cSAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1127f6c3e61cSAllen-KH Cheng wakeup-source; 1128f6c3e61cSAllen-KH Cheng status = "disabled"; 1129f6c3e61cSAllen-KH Cheng }; 1130f6c3e61cSAllen-KH Cheng }; 1131f6c3e61cSAllen-KH Cheng 11322e78620bSAllen-KH Cheng u3phy0: t-phy@11c80000 { 11332e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-tphy", 11342e78620bSAllen-KH Cheng "mediatek,generic-tphy-v2"; 11352e78620bSAllen-KH Cheng #address-cells = <1>; 11362e78620bSAllen-KH Cheng #size-cells = <1>; 11372e78620bSAllen-KH Cheng ranges = <0x0 0x0 0x11c80000 0x1000>; 11382e78620bSAllen-KH Cheng status = "disabled"; 11392e78620bSAllen-KH Cheng 11402e78620bSAllen-KH Cheng u2port1: usb-phy@0 { 11412e78620bSAllen-KH Cheng reg = <0x0 0x700>; 11422e78620bSAllen-KH Cheng clocks = <&clk26m>; 11432e78620bSAllen-KH Cheng clock-names = "ref"; 11442e78620bSAllen-KH Cheng #phy-cells = <1>; 11452e78620bSAllen-KH Cheng }; 11462e78620bSAllen-KH Cheng 11472e78620bSAllen-KH Cheng u3port1: usb-phy@700 { 11482e78620bSAllen-KH Cheng reg = <0x700 0x900>; 11492e78620bSAllen-KH Cheng clocks = <&clk26m>; 11502e78620bSAllen-KH Cheng clock-names = "ref"; 11512e78620bSAllen-KH Cheng #phy-cells = <1>; 11522e78620bSAllen-KH Cheng }; 11532e78620bSAllen-KH Cheng }; 11542e78620bSAllen-KH Cheng 11552e78620bSAllen-KH Cheng u3phy1: t-phy@11ca0000 { 11562e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-tphy", 11572e78620bSAllen-KH Cheng "mediatek,generic-tphy-v2"; 11582e78620bSAllen-KH Cheng #address-cells = <1>; 11592e78620bSAllen-KH Cheng #size-cells = <1>; 11602e78620bSAllen-KH Cheng ranges = <0x0 0x0 0x11ca0000 0x1000>; 11612e78620bSAllen-KH Cheng status = "disabled"; 11622e78620bSAllen-KH Cheng 11632e78620bSAllen-KH Cheng u2port0: usb-phy@0 { 11642e78620bSAllen-KH Cheng reg = <0x0 0x700>; 11652e78620bSAllen-KH Cheng clocks = <&clk26m>; 11662e78620bSAllen-KH Cheng clock-names = "ref"; 11672e78620bSAllen-KH Cheng #phy-cells = <1>; 11682e78620bSAllen-KH Cheng mediatek,discth = <0x8>; 11692e78620bSAllen-KH Cheng }; 11702e78620bSAllen-KH Cheng }; 11712e78620bSAllen-KH Cheng 11722e78620bSAllen-KH Cheng efuse: efuse@11cb0000 { 11732e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 11742e78620bSAllen-KH Cheng reg = <0 0x11cb0000 0 0x1000>; 11752e78620bSAllen-KH Cheng #address-cells = <1>; 11762e78620bSAllen-KH Cheng #size-cells = <1>; 11772e78620bSAllen-KH Cheng }; 11782e78620bSAllen-KH Cheng 11792e78620bSAllen-KH Cheng mipi_tx0: dsi-phy@11cc0000 { 11802e78620bSAllen-KH Cheng compatible = "mediatek,mt8183-mipi-tx"; 11812e78620bSAllen-KH Cheng reg = <0 0x11cc0000 0 0x1000>; 11822e78620bSAllen-KH Cheng clocks = <&clk26m>; 11832e78620bSAllen-KH Cheng #clock-cells = <0>; 11842e78620bSAllen-KH Cheng #phy-cells = <0>; 11852e78620bSAllen-KH Cheng clock-output-names = "mipi_tx0_pll"; 11862e78620bSAllen-KH Cheng status = "disabled"; 11872e78620bSAllen-KH Cheng }; 11882e78620bSAllen-KH Cheng 11892e78620bSAllen-KH Cheng mfgsys: clock-controller@13000000 { 11902e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mfgsys"; 11912e78620bSAllen-KH Cheng reg = <0 0x13000000 0 0x1000>; 11922e78620bSAllen-KH Cheng #clock-cells = <1>; 11932e78620bSAllen-KH Cheng }; 11942e78620bSAllen-KH Cheng 1195ee63f414SAngeloGioacchino Del Regno gpu: gpu@13040000 { 1196ee63f414SAngeloGioacchino Del Regno compatible = "mediatek,mt8186-mali", 1197ee63f414SAngeloGioacchino Del Regno "arm,mali-bifrost"; 1198ee63f414SAngeloGioacchino Del Regno reg = <0 0x13040000 0 0x4000>; 1199ee63f414SAngeloGioacchino Del Regno 1200ee63f414SAngeloGioacchino Del Regno clocks = <&mfgsys CLK_MFG_BG3D>; 1201ee63f414SAngeloGioacchino Del Regno interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1202ee63f414SAngeloGioacchino Del Regno <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1203ee63f414SAngeloGioacchino Del Regno <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1204ee63f414SAngeloGioacchino Del Regno interrupt-names = "job", "mmu", "gpu"; 1205ee63f414SAngeloGioacchino Del Regno power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1206ee63f414SAngeloGioacchino Del Regno <&spm MT8186_POWER_DOMAIN_MFG3>; 1207ee63f414SAngeloGioacchino Del Regno power-domain-names = "core0", "core1"; 1208ee63f414SAngeloGioacchino Del Regno #cooling-cells = <2>; 1209ee63f414SAngeloGioacchino Del Regno status = "disabled"; 1210ee63f414SAngeloGioacchino Del Regno }; 1211ee63f414SAngeloGioacchino Del Regno 12122e78620bSAllen-KH Cheng mmsys: syscon@14000000 { 12132e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mmsys", "syscon"; 12142e78620bSAllen-KH Cheng reg = <0 0x14000000 0 0x1000>; 12152e78620bSAllen-KH Cheng #clock-cells = <1>; 12162e78620bSAllen-KH Cheng #reset-cells = <1>; 1217*7e07d332SAllen-KH Cheng mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1218*7e07d332SAllen-KH Cheng <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1219*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1220*7e07d332SAllen-KH Cheng }; 1221*7e07d332SAllen-KH Cheng 1222*7e07d332SAllen-KH Cheng mutex: mutex@14001000 { 1223*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-mutex"; 1224*7e07d332SAllen-KH Cheng reg = <0 0x14001000 0 0x1000>; 1225*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1226*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 1227*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1228*7e07d332SAllen-KH Cheng mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1229*7e07d332SAllen-KH Cheng <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1230*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 12312e78620bSAllen-KH Cheng }; 12322e78620bSAllen-KH Cheng 1233d4a65162SAllen-KH Cheng smi_common: smi@14002000 { 1234d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-common"; 1235d4a65162SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 1236d4a65162SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1237d4a65162SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1238d4a65162SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 1239d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1240d4a65162SAllen-KH Cheng }; 1241d4a65162SAllen-KH Cheng 1242d4a65162SAllen-KH Cheng larb0: smi@14003000 { 1243d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1244d4a65162SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 1245d4a65162SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 1246d4a65162SAllen-KH Cheng <&mmsys CLK_MM_SMI_COMMON>; 1247d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1248d4a65162SAllen-KH Cheng mediatek,larb-id = <0>; 1249d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1250d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1251d4a65162SAllen-KH Cheng }; 1252d4a65162SAllen-KH Cheng 1253d4a65162SAllen-KH Cheng larb1: smi@14004000 { 1254d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1255d4a65162SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 1256d4a65162SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 1257d4a65162SAllen-KH Cheng <&mmsys CLK_MM_SMI_COMMON>; 1258d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1259d4a65162SAllen-KH Cheng mediatek,larb-id = <1>; 1260d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1261d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1262d4a65162SAllen-KH Cheng }; 1263d4a65162SAllen-KH Cheng 1264*7e07d332SAllen-KH Cheng ovl0: ovl@14005000 { 1265*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; 1266*7e07d332SAllen-KH Cheng reg = <0 0x14005000 0 0x1000>; 1267*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0>; 1268*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 1269*7e07d332SAllen-KH Cheng iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; 1270*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1271*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1272*7e07d332SAllen-KH Cheng }; 1273*7e07d332SAllen-KH Cheng 1274*7e07d332SAllen-KH Cheng ovl_2l0: ovl@14006000 { 1275*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; 1276*7e07d332SAllen-KH Cheng reg = <0 0x14006000 0 0x1000>; 1277*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1278*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1279*7e07d332SAllen-KH Cheng iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; 1280*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1281*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1282*7e07d332SAllen-KH Cheng }; 1283*7e07d332SAllen-KH Cheng 1284*7e07d332SAllen-KH Cheng rdma0: rdma@14007000 { 1285*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1286*7e07d332SAllen-KH Cheng reg = <0 0x14007000 0 0x1000>; 1287*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1288*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 1289*7e07d332SAllen-KH Cheng iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; 1290*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1291*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1292*7e07d332SAllen-KH Cheng }; 1293*7e07d332SAllen-KH Cheng 1294*7e07d332SAllen-KH Cheng color: color@14009000 { 1295*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; 1296*7e07d332SAllen-KH Cheng reg = <0 0x14009000 0 0x1000>; 1297*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1298*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 1299*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1300*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1301*7e07d332SAllen-KH Cheng }; 1302*7e07d332SAllen-KH Cheng 130390e75e82SAllen-KH Cheng dpi: dpi@1400a000 { 130490e75e82SAllen-KH Cheng compatible = "mediatek,mt8186-dpi"; 130590e75e82SAllen-KH Cheng reg = <0 0x1400a000 0 0x1000>; 130690e75e82SAllen-KH Cheng clocks = <&topckgen CLK_TOP_DPI>, 130790e75e82SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI>, 130890e75e82SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 130990e75e82SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 131090e75e82SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_DPI>; 131190e75e82SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 131290e75e82SAllen-KH Cheng interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 131390e75e82SAllen-KH Cheng status = "disabled"; 131490e75e82SAllen-KH Cheng 131590e75e82SAllen-KH Cheng port { 131690e75e82SAllen-KH Cheng dpi_out: endpoint { }; 131790e75e82SAllen-KH Cheng }; 131890e75e82SAllen-KH Cheng }; 131990e75e82SAllen-KH Cheng 1320*7e07d332SAllen-KH Cheng ccorr: ccorr@1400b000 { 1321*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 1322*7e07d332SAllen-KH Cheng reg = <0 0x1400b000 0 0x1000>; 1323*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1324*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; 1325*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1326*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1327*7e07d332SAllen-KH Cheng }; 1328*7e07d332SAllen-KH Cheng 1329*7e07d332SAllen-KH Cheng aal: aal@1400c000 { 1330*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; 1331*7e07d332SAllen-KH Cheng reg = <0 0x1400c000 0 0x1000>; 1332*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_AAL0>; 1333*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 1334*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1335*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1336*7e07d332SAllen-KH Cheng }; 1337*7e07d332SAllen-KH Cheng 1338*7e07d332SAllen-KH Cheng gamma: gamma@1400d000 { 1339*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; 1340*7e07d332SAllen-KH Cheng reg = <0 0x1400d000 0 0x1000>; 1341*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1342*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 1343*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1344*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1345*7e07d332SAllen-KH Cheng }; 1346*7e07d332SAllen-KH Cheng 1347*7e07d332SAllen-KH Cheng postmask: postmask@1400e000 { 1348*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-postmask", 1349*7e07d332SAllen-KH Cheng "mediatek,mt8192-disp-postmask"; 1350*7e07d332SAllen-KH Cheng reg = <0 0x1400e000 0 0x1000>; 1351*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1352*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 1353*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1354*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1355*7e07d332SAllen-KH Cheng }; 1356*7e07d332SAllen-KH Cheng 1357*7e07d332SAllen-KH Cheng dither: dither@1400f000 { 1358*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; 1359*7e07d332SAllen-KH Cheng reg = <0 0x1400f000 0 0x1000>; 1360*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1361*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 1362*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1363*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1364*7e07d332SAllen-KH Cheng }; 1365*7e07d332SAllen-KH Cheng 1366bd2b1b4aSAllen-KH Cheng dsi0: dsi@14013000 { 1367bd2b1b4aSAllen-KH Cheng compatible = "mediatek,mt8186-dsi"; 1368bd2b1b4aSAllen-KH Cheng reg = <0 0x14013000 0 0x1000>; 1369bd2b1b4aSAllen-KH Cheng clocks = <&mmsys CLK_MM_DSI0>, 1370bd2b1b4aSAllen-KH Cheng <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1371bd2b1b4aSAllen-KH Cheng <&mipi_tx0>; 1372bd2b1b4aSAllen-KH Cheng clock-names = "engine", "digital", "hs"; 1373bd2b1b4aSAllen-KH Cheng interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1374bd2b1b4aSAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1375bd2b1b4aSAllen-KH Cheng resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1376bd2b1b4aSAllen-KH Cheng phys = <&mipi_tx0>; 1377bd2b1b4aSAllen-KH Cheng phy-names = "dphy"; 1378bd2b1b4aSAllen-KH Cheng status = "disabled"; 1379bd2b1b4aSAllen-KH Cheng 1380bd2b1b4aSAllen-KH Cheng port { 1381bd2b1b4aSAllen-KH Cheng dsi_out: endpoint { }; 1382bd2b1b4aSAllen-KH Cheng }; 1383bd2b1b4aSAllen-KH Cheng }; 1384bd2b1b4aSAllen-KH Cheng 1385d4a65162SAllen-KH Cheng iommu_mm: iommu@14016000 { 1386d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-iommu-mm"; 1387d4a65162SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1388d4a65162SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1389d4a65162SAllen-KH Cheng clock-names = "bclk"; 1390d4a65162SAllen-KH Cheng interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1391d4a65162SAllen-KH Cheng mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1392d4a65162SAllen-KH Cheng &larb7 &larb8 &larb9 &larb11 1393d4a65162SAllen-KH Cheng &larb13 &larb14 &larb16 &larb17 1394d4a65162SAllen-KH Cheng &larb19 &larb20>; 1395d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1396d4a65162SAllen-KH Cheng #iommu-cells = <1>; 1397d4a65162SAllen-KH Cheng }; 1398d4a65162SAllen-KH Cheng 1399*7e07d332SAllen-KH Cheng rdma1: rdma@1401f000 { 1400*7e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1401*7e07d332SAllen-KH Cheng reg = <0 0x1401f000 0 0x1000>; 1402*7e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1403*7e07d332SAllen-KH Cheng interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; 1404*7e07d332SAllen-KH Cheng iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; 1405*7e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; 1406*7e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1407*7e07d332SAllen-KH Cheng }; 1408*7e07d332SAllen-KH Cheng 14092e78620bSAllen-KH Cheng wpesys: clock-controller@14020000 { 14102e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-wpesys"; 14112e78620bSAllen-KH Cheng reg = <0 0x14020000 0 0x1000>; 14122e78620bSAllen-KH Cheng #clock-cells = <1>; 14132e78620bSAllen-KH Cheng }; 14142e78620bSAllen-KH Cheng 1415d4a65162SAllen-KH Cheng larb8: smi@14023000 { 1416d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1417d4a65162SAllen-KH Cheng reg = <0 0x14023000 0 0x1000>; 1418d4a65162SAllen-KH Cheng clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1419d4a65162SAllen-KH Cheng <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1420d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1421d4a65162SAllen-KH Cheng mediatek,larb-id = <8>; 1422d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1423d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1424d4a65162SAllen-KH Cheng }; 1425d4a65162SAllen-KH Cheng 14262e78620bSAllen-KH Cheng imgsys1: clock-controller@15020000 { 14272e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-imgsys1"; 14282e78620bSAllen-KH Cheng reg = <0 0x15020000 0 0x1000>; 14292e78620bSAllen-KH Cheng #clock-cells = <1>; 14302e78620bSAllen-KH Cheng }; 14312e78620bSAllen-KH Cheng 1432d4a65162SAllen-KH Cheng larb9: smi@1502e000 { 1433d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1434d4a65162SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 1435d4a65162SAllen-KH Cheng clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1436d4a65162SAllen-KH Cheng <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1437d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1438d4a65162SAllen-KH Cheng mediatek,larb-id = <9>; 1439d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1440d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1441d4a65162SAllen-KH Cheng }; 1442d4a65162SAllen-KH Cheng 14432e78620bSAllen-KH Cheng imgsys2: clock-controller@15820000 { 14442e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-imgsys2"; 14452e78620bSAllen-KH Cheng reg = <0 0x15820000 0 0x1000>; 14462e78620bSAllen-KH Cheng #clock-cells = <1>; 14472e78620bSAllen-KH Cheng }; 14482e78620bSAllen-KH Cheng 1449d4a65162SAllen-KH Cheng larb11: smi@1582e000 { 1450d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1451d4a65162SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 1452d4a65162SAllen-KH Cheng clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1453d4a65162SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1454d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1455d4a65162SAllen-KH Cheng mediatek,larb-id = <11>; 1456d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1457d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1458d4a65162SAllen-KH Cheng }; 1459d4a65162SAllen-KH Cheng 1460d4a65162SAllen-KH Cheng larb4: smi@1602e000 { 1461d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1462d4a65162SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 1463d4a65162SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1464d4a65162SAllen-KH Cheng <&vdecsys CLK_VDEC_LARB1_CKEN>; 1465d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1466d4a65162SAllen-KH Cheng mediatek,larb-id = <4>; 1467d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1468d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1469d4a65162SAllen-KH Cheng }; 1470d4a65162SAllen-KH Cheng 14712e78620bSAllen-KH Cheng vdecsys: clock-controller@1602f000 { 14722e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-vdecsys"; 14732e78620bSAllen-KH Cheng reg = <0 0x1602f000 0 0x1000>; 14742e78620bSAllen-KH Cheng #clock-cells = <1>; 14752e78620bSAllen-KH Cheng }; 14762e78620bSAllen-KH Cheng 14772e78620bSAllen-KH Cheng vencsys: clock-controller@17000000 { 14782e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-vencsys"; 14792e78620bSAllen-KH Cheng reg = <0 0x17000000 0 0x1000>; 14802e78620bSAllen-KH Cheng #clock-cells = <1>; 14812e78620bSAllen-KH Cheng }; 14822e78620bSAllen-KH Cheng 1483d4a65162SAllen-KH Cheng larb7: smi@17010000 { 1484d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1485d4a65162SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 1486d4a65162SAllen-KH Cheng clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1487d4a65162SAllen-KH Cheng <&vencsys CLK_VENC_CKE1_VENC>; 1488d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1489d4a65162SAllen-KH Cheng mediatek,larb-id = <7>; 1490d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1491d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1492d4a65162SAllen-KH Cheng }; 1493d4a65162SAllen-KH Cheng 14942e78620bSAllen-KH Cheng camsys: clock-controller@1a000000 { 14952e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-camsys"; 14962e78620bSAllen-KH Cheng reg = <0 0x1a000000 0 0x1000>; 14972e78620bSAllen-KH Cheng #clock-cells = <1>; 14982e78620bSAllen-KH Cheng }; 14992e78620bSAllen-KH Cheng 1500d4a65162SAllen-KH Cheng larb13: smi@1a001000 { 1501d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1502d4a65162SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 1503d4a65162SAllen-KH Cheng clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1504d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1505d4a65162SAllen-KH Cheng mediatek,larb-id = <13>; 1506d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1507d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1508d4a65162SAllen-KH Cheng }; 1509d4a65162SAllen-KH Cheng 1510d4a65162SAllen-KH Cheng larb14: smi@1a002000 { 1511d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1512d4a65162SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 1513d4a65162SAllen-KH Cheng clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1514d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1515d4a65162SAllen-KH Cheng mediatek,larb-id = <14>; 1516d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1517d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1518d4a65162SAllen-KH Cheng }; 1519d4a65162SAllen-KH Cheng 1520d4a65162SAllen-KH Cheng larb16: smi@1a00f000 { 1521d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1522d4a65162SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 1523d4a65162SAllen-KH Cheng clocks = <&camsys CLK_CAM_LARB14>, 1524d4a65162SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1525d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1526d4a65162SAllen-KH Cheng mediatek,larb-id = <16>; 1527d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1528d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1529d4a65162SAllen-KH Cheng }; 1530d4a65162SAllen-KH Cheng 1531d4a65162SAllen-KH Cheng larb17: smi@1a010000 { 1532d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1533d4a65162SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 1534d4a65162SAllen-KH Cheng clocks = <&camsys CLK_CAM_LARB13>, 1535d4a65162SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1536d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1537d4a65162SAllen-KH Cheng mediatek,larb-id = <17>; 1538d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1539d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1540d4a65162SAllen-KH Cheng }; 1541d4a65162SAllen-KH Cheng 15422e78620bSAllen-KH Cheng camsys_rawa: clock-controller@1a04f000 { 15432e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-camsys_rawa"; 15442e78620bSAllen-KH Cheng reg = <0 0x1a04f000 0 0x1000>; 15452e78620bSAllen-KH Cheng #clock-cells = <1>; 15462e78620bSAllen-KH Cheng }; 15472e78620bSAllen-KH Cheng 15482e78620bSAllen-KH Cheng camsys_rawb: clock-controller@1a06f000 { 15492e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-camsys_rawb"; 15502e78620bSAllen-KH Cheng reg = <0 0x1a06f000 0 0x1000>; 15512e78620bSAllen-KH Cheng #clock-cells = <1>; 15522e78620bSAllen-KH Cheng }; 15532e78620bSAllen-KH Cheng 15542e78620bSAllen-KH Cheng mdpsys: clock-controller@1b000000 { 15552e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mdpsys"; 15562e78620bSAllen-KH Cheng reg = <0 0x1b000000 0 0x1000>; 15572e78620bSAllen-KH Cheng #clock-cells = <1>; 15582e78620bSAllen-KH Cheng }; 15592e78620bSAllen-KH Cheng 1560d4a65162SAllen-KH Cheng larb2: smi@1b002000 { 1561d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1562d4a65162SAllen-KH Cheng reg = <0 0x1b002000 0 0x1000>; 1563d4a65162SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1564d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1565d4a65162SAllen-KH Cheng mediatek,larb-id = <2>; 1566d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1567d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1568d4a65162SAllen-KH Cheng }; 1569d4a65162SAllen-KH Cheng 15702e78620bSAllen-KH Cheng ipesys: clock-controller@1c000000 { 15712e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-ipesys"; 15722e78620bSAllen-KH Cheng reg = <0 0x1c000000 0 0x1000>; 15732e78620bSAllen-KH Cheng #clock-cells = <1>; 15742e78620bSAllen-KH Cheng }; 1575d4a65162SAllen-KH Cheng 1576d4a65162SAllen-KH Cheng larb20: smi@1c00f000 { 1577d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1578d4a65162SAllen-KH Cheng reg = <0 0x1c00f000 0 0x1000>; 1579d4a65162SAllen-KH Cheng clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1580d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1581d4a65162SAllen-KH Cheng mediatek,larb-id = <20>; 1582d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1583d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1584d4a65162SAllen-KH Cheng }; 1585d4a65162SAllen-KH Cheng 1586d4a65162SAllen-KH Cheng larb19: smi@1c10f000 { 1587d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1588d4a65162SAllen-KH Cheng reg = <0 0x1c10f000 0 0x1000>; 1589d4a65162SAllen-KH Cheng clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1590d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1591d4a65162SAllen-KH Cheng mediatek,larb-id = <19>; 1592d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1593d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1594d4a65162SAllen-KH Cheng }; 15952e78620bSAllen-KH Cheng }; 15962e78620bSAllen-KH Cheng}; 1597