1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset-controller/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include "mt8183-pinfunc.h" 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu-map { 50 cluster0 { 51 core0 { 52 cpu = <&cpu0>; 53 }; 54 core1 { 55 cpu = <&cpu1>; 56 }; 57 core2 { 58 cpu = <&cpu2>; 59 }; 60 core3 { 61 cpu = <&cpu3>; 62 }; 63 }; 64 65 cluster1 { 66 core0 { 67 cpu = <&cpu4>; 68 }; 69 core1 { 70 cpu = <&cpu5>; 71 }; 72 core2 { 73 cpu = <&cpu6>; 74 }; 75 core3 { 76 cpu = <&cpu7>; 77 }; 78 }; 79 }; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x000>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <741>; 87 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 88 dynamic-power-coefficient = <84>; 89 #cooling-cells = <2>; 90 }; 91 92 cpu1: cpu@1 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x001>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <741>; 98 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 99 dynamic-power-coefficient = <84>; 100 #cooling-cells = <2>; 101 }; 102 103 cpu2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x002>; 107 enable-method = "psci"; 108 capacity-dmips-mhz = <741>; 109 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 110 dynamic-power-coefficient = <84>; 111 #cooling-cells = <2>; 112 }; 113 114 cpu3: cpu@3 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x003>; 118 enable-method = "psci"; 119 capacity-dmips-mhz = <741>; 120 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 121 dynamic-power-coefficient = <84>; 122 #cooling-cells = <2>; 123 }; 124 125 cpu4: cpu@100 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a73"; 128 reg = <0x100>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <1024>; 131 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 132 dynamic-power-coefficient = <211>; 133 #cooling-cells = <2>; 134 }; 135 136 cpu5: cpu@101 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a73"; 139 reg = <0x101>; 140 enable-method = "psci"; 141 capacity-dmips-mhz = <1024>; 142 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 143 dynamic-power-coefficient = <211>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu6: cpu@102 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a73"; 150 reg = <0x102>; 151 enable-method = "psci"; 152 capacity-dmips-mhz = <1024>; 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 154 dynamic-power-coefficient = <211>; 155 #cooling-cells = <2>; 156 }; 157 158 cpu7: cpu@103 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a73"; 161 reg = <0x103>; 162 enable-method = "psci"; 163 capacity-dmips-mhz = <1024>; 164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 165 dynamic-power-coefficient = <211>; 166 #cooling-cells = <2>; 167 }; 168 169 idle-states { 170 entry-method = "psci"; 171 172 CPU_SLEEP: cpu-sleep { 173 compatible = "arm,idle-state"; 174 local-timer-stop; 175 arm,psci-suspend-param = <0x00010001>; 176 entry-latency-us = <200>; 177 exit-latency-us = <200>; 178 min-residency-us = <800>; 179 }; 180 181 CLUSTER_SLEEP0: cluster-sleep-0 { 182 compatible = "arm,idle-state"; 183 local-timer-stop; 184 arm,psci-suspend-param = <0x01010001>; 185 entry-latency-us = <250>; 186 exit-latency-us = <400>; 187 min-residency-us = <1000>; 188 }; 189 CLUSTER_SLEEP1: cluster-sleep-1 { 190 compatible = "arm,idle-state"; 191 local-timer-stop; 192 arm,psci-suspend-param = <0x01010001>; 193 entry-latency-us = <250>; 194 exit-latency-us = <400>; 195 min-residency-us = <1300>; 196 }; 197 }; 198 }; 199 200 pmu-a53 { 201 compatible = "arm,cortex-a53-pmu"; 202 interrupt-parent = <&gic>; 203 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 204 }; 205 206 pmu-a73 { 207 compatible = "arm,cortex-a73-pmu"; 208 interrupt-parent = <&gic>; 209 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 210 }; 211 212 psci { 213 compatible = "arm,psci-1.0"; 214 method = "smc"; 215 }; 216 217 clk26m: oscillator { 218 compatible = "fixed-clock"; 219 #clock-cells = <0>; 220 clock-frequency = <26000000>; 221 clock-output-names = "clk26m"; 222 }; 223 224 timer { 225 compatible = "arm,armv8-timer"; 226 interrupt-parent = <&gic>; 227 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 228 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 229 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 230 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 231 }; 232 233 soc { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 compatible = "simple-bus"; 237 ranges; 238 239 soc_data: soc_data@8000000 { 240 compatible = "mediatek,mt8183-efuse", 241 "mediatek,efuse"; 242 reg = <0 0x08000000 0 0x0010>; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 status = "disabled"; 246 }; 247 248 gic: interrupt-controller@c000000 { 249 compatible = "arm,gic-v3"; 250 #interrupt-cells = <4>; 251 interrupt-parent = <&gic>; 252 interrupt-controller; 253 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 254 <0 0x0c100000 0 0x200000>, /* GICR */ 255 <0 0x0c400000 0 0x2000>, /* GICC */ 256 <0 0x0c410000 0 0x1000>, /* GICH */ 257 <0 0x0c420000 0 0x2000>; /* GICV */ 258 259 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 260 ppi-partitions { 261 ppi_cluster0: interrupt-partition-0 { 262 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 263 }; 264 ppi_cluster1: interrupt-partition-1 { 265 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 266 }; 267 }; 268 }; 269 270 mcucfg: syscon@c530000 { 271 compatible = "mediatek,mt8183-mcucfg", "syscon"; 272 reg = <0 0x0c530000 0 0x1000>; 273 #clock-cells = <1>; 274 }; 275 276 sysirq: interrupt-controller@c530a80 { 277 compatible = "mediatek,mt8183-sysirq", 278 "mediatek,mt6577-sysirq"; 279 interrupt-controller; 280 #interrupt-cells = <3>; 281 interrupt-parent = <&gic>; 282 reg = <0 0x0c530a80 0 0x50>; 283 }; 284 285 topckgen: syscon@10000000 { 286 compatible = "mediatek,mt8183-topckgen", "syscon"; 287 reg = <0 0x10000000 0 0x1000>; 288 #clock-cells = <1>; 289 }; 290 291 infracfg: syscon@10001000 { 292 compatible = "mediatek,mt8183-infracfg", "syscon"; 293 reg = <0 0x10001000 0 0x1000>; 294 #clock-cells = <1>; 295 #reset-cells = <1>; 296 }; 297 298 pericfg: syscon@10003000 { 299 compatible = "mediatek,mt8183-pericfg", "syscon"; 300 reg = <0 0x10003000 0 0x1000>; 301 #clock-cells = <1>; 302 }; 303 304 pio: pinctrl@10005000 { 305 compatible = "mediatek,mt8183-pinctrl"; 306 reg = <0 0x10005000 0 0x1000>, 307 <0 0x11f20000 0 0x1000>, 308 <0 0x11e80000 0 0x1000>, 309 <0 0x11e70000 0 0x1000>, 310 <0 0x11e90000 0 0x1000>, 311 <0 0x11d30000 0 0x1000>, 312 <0 0x11d20000 0 0x1000>, 313 <0 0x11c50000 0 0x1000>, 314 <0 0x11f30000 0 0x1000>, 315 <0 0x1000b000 0 0x1000>; 316 reg-names = "iocfg0", "iocfg1", "iocfg2", 317 "iocfg3", "iocfg4", "iocfg5", 318 "iocfg6", "iocfg7", "iocfg8", 319 "eint"; 320 gpio-controller; 321 #gpio-cells = <2>; 322 gpio-ranges = <&pio 0 0 192>; 323 interrupt-controller; 324 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 325 #interrupt-cells = <2>; 326 }; 327 328 scpsys: syscon@10006000 { 329 compatible = "syscon", "simple-mfd"; 330 reg = <0 0x10006000 0 0x1000>; 331 #power-domain-cells = <1>; 332 333 /* System Power Manager */ 334 spm: power-controller { 335 compatible = "mediatek,mt8183-power-controller"; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 #power-domain-cells = <1>; 339 340 /* power domain of the SoC */ 341 power-domain@MT8183_POWER_DOMAIN_AUDIO { 342 reg = <MT8183_POWER_DOMAIN_AUDIO>; 343 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 344 <&infracfg CLK_INFRA_AUDIO>, 345 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 346 clock-names = "audio", "audio1", "audio2"; 347 #power-domain-cells = <0>; 348 }; 349 350 power-domain@MT8183_POWER_DOMAIN_CONN { 351 reg = <MT8183_POWER_DOMAIN_CONN>; 352 mediatek,infracfg = <&infracfg>; 353 #power-domain-cells = <0>; 354 }; 355 356 power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 357 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 358 clocks = <&topckgen CLK_TOP_MUX_MFG>; 359 clock-names = "mfg"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 #power-domain-cells = <1>; 363 364 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 365 reg = <MT8183_POWER_DOMAIN_MFG>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 #power-domain-cells = <1>; 369 370 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 371 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 372 #power-domain-cells = <0>; 373 }; 374 375 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 376 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 377 #power-domain-cells = <0>; 378 }; 379 380 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 381 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 382 mediatek,infracfg = <&infracfg>; 383 #power-domain-cells = <0>; 384 }; 385 }; 386 }; 387 388 power-domain@MT8183_POWER_DOMAIN_DISP { 389 reg = <MT8183_POWER_DOMAIN_DISP>; 390 clocks = <&topckgen CLK_TOP_MUX_MM>, 391 <&mmsys CLK_MM_SMI_COMMON>, 392 <&mmsys CLK_MM_SMI_LARB0>, 393 <&mmsys CLK_MM_SMI_LARB1>, 394 <&mmsys CLK_MM_GALS_COMM0>, 395 <&mmsys CLK_MM_GALS_COMM1>, 396 <&mmsys CLK_MM_GALS_CCU2MM>, 397 <&mmsys CLK_MM_GALS_IPU12MM>, 398 <&mmsys CLK_MM_GALS_IMG2MM>, 399 <&mmsys CLK_MM_GALS_CAM2MM>, 400 <&mmsys CLK_MM_GALS_IPU2MM>; 401 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 402 "mm-4", "mm-5", "mm-6", "mm-7", 403 "mm-8", "mm-9"; 404 mediatek,infracfg = <&infracfg>; 405 mediatek,smi = <&smi_common>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 #power-domain-cells = <1>; 409 410 power-domain@MT8183_POWER_DOMAIN_CAM { 411 reg = <MT8183_POWER_DOMAIN_CAM>; 412 clocks = <&topckgen CLK_TOP_MUX_CAM>, 413 <&camsys CLK_CAM_LARB6>, 414 <&camsys CLK_CAM_LARB3>, 415 <&camsys CLK_CAM_SENINF>, 416 <&camsys CLK_CAM_CAMSV0>, 417 <&camsys CLK_CAM_CAMSV1>, 418 <&camsys CLK_CAM_CAMSV2>, 419 <&camsys CLK_CAM_CCU>; 420 clock-names = "cam", "cam-0", "cam-1", 421 "cam-2", "cam-3", "cam-4", 422 "cam-5", "cam-6"; 423 mediatek,infracfg = <&infracfg>; 424 mediatek,smi = <&smi_common>; 425 #power-domain-cells = <0>; 426 }; 427 428 power-domain@MT8183_POWER_DOMAIN_ISP { 429 reg = <MT8183_POWER_DOMAIN_ISP>; 430 clocks = <&topckgen CLK_TOP_MUX_IMG>, 431 <&imgsys CLK_IMG_LARB5>, 432 <&imgsys CLK_IMG_LARB2>; 433 clock-names = "isp", "isp-0", "isp-1"; 434 mediatek,infracfg = <&infracfg>; 435 mediatek,smi = <&smi_common>; 436 #power-domain-cells = <0>; 437 }; 438 439 power-domain@MT8183_POWER_DOMAIN_VDEC { 440 reg = <MT8183_POWER_DOMAIN_VDEC>; 441 mediatek,smi = <&smi_common>; 442 #power-domain-cells = <0>; 443 }; 444 445 power-domain@MT8183_POWER_DOMAIN_VENC { 446 reg = <MT8183_POWER_DOMAIN_VENC>; 447 mediatek,smi = <&smi_common>; 448 #power-domain-cells = <0>; 449 }; 450 451 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 452 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 453 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 454 <&topckgen CLK_TOP_MUX_DSP>, 455 <&ipu_conn CLK_IPU_CONN_IPU>, 456 <&ipu_conn CLK_IPU_CONN_AHB>, 457 <&ipu_conn CLK_IPU_CONN_AXI>, 458 <&ipu_conn CLK_IPU_CONN_ISP>, 459 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 460 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 461 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 462 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 463 mediatek,infracfg = <&infracfg>; 464 mediatek,smi = <&smi_common>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 #power-domain-cells = <1>; 468 469 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 470 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 471 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 472 clock-names = "vpu2"; 473 mediatek,infracfg = <&infracfg>; 474 #power-domain-cells = <0>; 475 }; 476 477 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 478 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 479 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 480 clock-names = "vpu3"; 481 mediatek,infracfg = <&infracfg>; 482 #power-domain-cells = <0>; 483 }; 484 }; 485 }; 486 }; 487 }; 488 489 watchdog: watchdog@10007000 { 490 compatible = "mediatek,mt8183-wdt"; 491 reg = <0 0x10007000 0 0x100>; 492 #reset-cells = <1>; 493 }; 494 495 apmixedsys: syscon@1000c000 { 496 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 497 reg = <0 0x1000c000 0 0x1000>; 498 #clock-cells = <1>; 499 }; 500 501 pwrap: pwrap@1000d000 { 502 compatible = "mediatek,mt8183-pwrap"; 503 reg = <0 0x1000d000 0 0x1000>; 504 reg-names = "pwrap"; 505 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 507 <&infracfg CLK_INFRA_PMIC_AP>; 508 clock-names = "spi", "wrap"; 509 }; 510 511 scp: scp@10500000 { 512 compatible = "mediatek,mt8183-scp"; 513 reg = <0 0x10500000 0 0x80000>, 514 <0 0x105c0000 0 0x19080>; 515 reg-names = "sram", "cfg"; 516 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&infracfg CLK_INFRA_SCPSYS>; 518 clock-names = "main"; 519 memory-region = <&scp_mem_reserved>; 520 status = "disabled"; 521 }; 522 523 systimer: timer@10017000 { 524 compatible = "mediatek,mt8183-timer", 525 "mediatek,mt6765-timer"; 526 reg = <0 0x10017000 0 0x1000>; 527 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&topckgen CLK_TOP_CLK13M>; 529 clock-names = "clk13m"; 530 }; 531 532 iommu: iommu@10205000 { 533 compatible = "mediatek,mt8183-m4u"; 534 reg = <0 0x10205000 0 0x1000>; 535 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 536 mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 537 &larb4 &larb5 &larb6>; 538 #iommu-cells = <1>; 539 }; 540 541 gce: mailbox@10238000 { 542 compatible = "mediatek,mt8183-gce"; 543 reg = <0 0x10238000 0 0x4000>; 544 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 545 #mbox-cells = <2>; 546 clocks = <&infracfg CLK_INFRA_GCE>; 547 clock-names = "gce"; 548 }; 549 550 auxadc: auxadc@11001000 { 551 compatible = "mediatek,mt8183-auxadc", 552 "mediatek,mt8173-auxadc"; 553 reg = <0 0x11001000 0 0x1000>; 554 clocks = <&infracfg CLK_INFRA_AUXADC>; 555 clock-names = "main"; 556 #io-channel-cells = <1>; 557 status = "disabled"; 558 }; 559 560 uart0: serial@11002000 { 561 compatible = "mediatek,mt8183-uart", 562 "mediatek,mt6577-uart"; 563 reg = <0 0x11002000 0 0x1000>; 564 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 565 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 566 clock-names = "baud", "bus"; 567 status = "disabled"; 568 }; 569 570 uart1: serial@11003000 { 571 compatible = "mediatek,mt8183-uart", 572 "mediatek,mt6577-uart"; 573 reg = <0 0x11003000 0 0x1000>; 574 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 575 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 576 clock-names = "baud", "bus"; 577 status = "disabled"; 578 }; 579 580 uart2: serial@11004000 { 581 compatible = "mediatek,mt8183-uart", 582 "mediatek,mt6577-uart"; 583 reg = <0 0x11004000 0 0x1000>; 584 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 585 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 586 clock-names = "baud", "bus"; 587 status = "disabled"; 588 }; 589 590 i2c6: i2c@11005000 { 591 compatible = "mediatek,mt8183-i2c"; 592 reg = <0 0x11005000 0 0x1000>, 593 <0 0x11000600 0 0x80>; 594 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 595 clocks = <&infracfg CLK_INFRA_I2C6>, 596 <&infracfg CLK_INFRA_AP_DMA>; 597 clock-names = "main", "dma"; 598 clock-div = <1>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 i2c0: i2c@11007000 { 605 compatible = "mediatek,mt8183-i2c"; 606 reg = <0 0x11007000 0 0x1000>, 607 <0 0x11000080 0 0x80>; 608 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 609 clocks = <&infracfg CLK_INFRA_I2C0>, 610 <&infracfg CLK_INFRA_AP_DMA>; 611 clock-names = "main", "dma"; 612 clock-div = <1>; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 status = "disabled"; 616 }; 617 618 i2c4: i2c@11008000 { 619 compatible = "mediatek,mt8183-i2c"; 620 reg = <0 0x11008000 0 0x1000>, 621 <0 0x11000100 0 0x80>; 622 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 623 clocks = <&infracfg CLK_INFRA_I2C1>, 624 <&infracfg CLK_INFRA_AP_DMA>, 625 <&infracfg CLK_INFRA_I2C1_ARBITER>; 626 clock-names = "main", "dma","arb"; 627 clock-div = <1>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 i2c2: i2c@11009000 { 634 compatible = "mediatek,mt8183-i2c"; 635 reg = <0 0x11009000 0 0x1000>, 636 <0 0x11000280 0 0x80>; 637 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 638 clocks = <&infracfg CLK_INFRA_I2C2>, 639 <&infracfg CLK_INFRA_AP_DMA>, 640 <&infracfg CLK_INFRA_I2C2_ARBITER>; 641 clock-names = "main", "dma", "arb"; 642 clock-div = <1>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 status = "disabled"; 646 }; 647 648 spi0: spi@1100a000 { 649 compatible = "mediatek,mt8183-spi"; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 reg = <0 0x1100a000 0 0x1000>; 653 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 654 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 655 <&topckgen CLK_TOP_MUX_SPI>, 656 <&infracfg CLK_INFRA_SPI0>; 657 clock-names = "parent-clk", "sel-clk", "spi-clk"; 658 status = "disabled"; 659 }; 660 661 thermal: thermal@1100b000 { 662 #thermal-sensor-cells = <1>; 663 compatible = "mediatek,mt8183-thermal"; 664 reg = <0 0x1100b000 0 0x1000>; 665 clocks = <&infracfg CLK_INFRA_THERM>, 666 <&infracfg CLK_INFRA_AUXADC>; 667 clock-names = "therm", "auxadc"; 668 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 669 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 670 mediatek,auxadc = <&auxadc>; 671 mediatek,apmixedsys = <&apmixedsys>; 672 nvmem-cells = <&thermal_calibration>; 673 nvmem-cell-names = "calibration-data"; 674 }; 675 676 thermal-zones { 677 cpu_thermal: cpu_thermal { 678 polling-delay-passive = <100>; 679 polling-delay = <500>; 680 thermal-sensors = <&thermal 0>; 681 sustainable-power = <5000>; 682 683 trips { 684 threshold: trip-point0 { 685 temperature = <68000>; 686 hysteresis = <2000>; 687 type = "passive"; 688 }; 689 690 target: trip-point1 { 691 temperature = <80000>; 692 hysteresis = <2000>; 693 type = "passive"; 694 }; 695 696 cpu_crit: cpu-crit { 697 temperature = <115000>; 698 hysteresis = <2000>; 699 type = "critical"; 700 }; 701 }; 702 703 cooling-maps { 704 map0 { 705 trip = <&target>; 706 cooling-device = <&cpu0 707 THERMAL_NO_LIMIT 708 THERMAL_NO_LIMIT>, 709 <&cpu1 710 THERMAL_NO_LIMIT 711 THERMAL_NO_LIMIT>, 712 <&cpu2 713 THERMAL_NO_LIMIT 714 THERMAL_NO_LIMIT>, 715 <&cpu3 716 THERMAL_NO_LIMIT 717 THERMAL_NO_LIMIT>; 718 contribution = <3072>; 719 }; 720 map1 { 721 trip = <&target>; 722 cooling-device = <&cpu4 723 THERMAL_NO_LIMIT 724 THERMAL_NO_LIMIT>, 725 <&cpu5 726 THERMAL_NO_LIMIT 727 THERMAL_NO_LIMIT>, 728 <&cpu6 729 THERMAL_NO_LIMIT 730 THERMAL_NO_LIMIT>, 731 <&cpu7 732 THERMAL_NO_LIMIT 733 THERMAL_NO_LIMIT>; 734 contribution = <1024>; 735 }; 736 }; 737 }; 738 739 /* The tzts1 ~ tzts6 don't need to polling */ 740 /* The tzts1 ~ tzts6 don't need to thermal throttle */ 741 742 tzts1: tzts1 { 743 polling-delay-passive = <0>; 744 polling-delay = <0>; 745 thermal-sensors = <&thermal 1>; 746 sustainable-power = <5000>; 747 trips {}; 748 cooling-maps {}; 749 }; 750 751 tzts2: tzts2 { 752 polling-delay-passive = <0>; 753 polling-delay = <0>; 754 thermal-sensors = <&thermal 2>; 755 sustainable-power = <5000>; 756 trips {}; 757 cooling-maps {}; 758 }; 759 760 tzts3: tzts3 { 761 polling-delay-passive = <0>; 762 polling-delay = <0>; 763 thermal-sensors = <&thermal 3>; 764 sustainable-power = <5000>; 765 trips {}; 766 cooling-maps {}; 767 }; 768 769 tzts4: tzts4 { 770 polling-delay-passive = <0>; 771 polling-delay = <0>; 772 thermal-sensors = <&thermal 4>; 773 sustainable-power = <5000>; 774 trips {}; 775 cooling-maps {}; 776 }; 777 778 tzts5: tzts5 { 779 polling-delay-passive = <0>; 780 polling-delay = <0>; 781 thermal-sensors = <&thermal 5>; 782 sustainable-power = <5000>; 783 trips {}; 784 cooling-maps {}; 785 }; 786 787 tztsABB: tztsABB { 788 polling-delay-passive = <0>; 789 polling-delay = <0>; 790 thermal-sensors = <&thermal 6>; 791 sustainable-power = <5000>; 792 trips {}; 793 cooling-maps {}; 794 }; 795 }; 796 797 pwm0: pwm@1100e000 { 798 compatible = "mediatek,mt8183-disp-pwm"; 799 reg = <0 0x1100e000 0 0x1000>; 800 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 801 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 802 #pwm-cells = <2>; 803 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 804 <&infracfg CLK_INFRA_DISP_PWM>; 805 clock-names = "main", "mm"; 806 }; 807 808 pwm1: pwm@11006000 { 809 compatible = "mediatek,mt8183-pwm"; 810 reg = <0 0x11006000 0 0x1000>; 811 #pwm-cells = <2>; 812 clocks = <&infracfg CLK_INFRA_PWM>, 813 <&infracfg CLK_INFRA_PWM_HCLK>, 814 <&infracfg CLK_INFRA_PWM1>, 815 <&infracfg CLK_INFRA_PWM2>, 816 <&infracfg CLK_INFRA_PWM3>, 817 <&infracfg CLK_INFRA_PWM4>; 818 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 819 "pwm4"; 820 }; 821 822 i2c3: i2c@1100f000 { 823 compatible = "mediatek,mt8183-i2c"; 824 reg = <0 0x1100f000 0 0x1000>, 825 <0 0x11000400 0 0x80>; 826 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 827 clocks = <&infracfg CLK_INFRA_I2C3>, 828 <&infracfg CLK_INFRA_AP_DMA>; 829 clock-names = "main", "dma"; 830 clock-div = <1>; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 status = "disabled"; 834 }; 835 836 spi1: spi@11010000 { 837 compatible = "mediatek,mt8183-spi"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 reg = <0 0x11010000 0 0x1000>; 841 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 842 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 843 <&topckgen CLK_TOP_MUX_SPI>, 844 <&infracfg CLK_INFRA_SPI1>; 845 clock-names = "parent-clk", "sel-clk", "spi-clk"; 846 status = "disabled"; 847 }; 848 849 i2c1: i2c@11011000 { 850 compatible = "mediatek,mt8183-i2c"; 851 reg = <0 0x11011000 0 0x1000>, 852 <0 0x11000480 0 0x80>; 853 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 854 clocks = <&infracfg CLK_INFRA_I2C4>, 855 <&infracfg CLK_INFRA_AP_DMA>; 856 clock-names = "main", "dma"; 857 clock-div = <1>; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 status = "disabled"; 861 }; 862 863 spi2: spi@11012000 { 864 compatible = "mediatek,mt8183-spi"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 reg = <0 0x11012000 0 0x1000>; 868 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 869 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 870 <&topckgen CLK_TOP_MUX_SPI>, 871 <&infracfg CLK_INFRA_SPI2>; 872 clock-names = "parent-clk", "sel-clk", "spi-clk"; 873 status = "disabled"; 874 }; 875 876 spi3: spi@11013000 { 877 compatible = "mediatek,mt8183-spi"; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 reg = <0 0x11013000 0 0x1000>; 881 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 882 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 883 <&topckgen CLK_TOP_MUX_SPI>, 884 <&infracfg CLK_INFRA_SPI3>; 885 clock-names = "parent-clk", "sel-clk", "spi-clk"; 886 status = "disabled"; 887 }; 888 889 i2c9: i2c@11014000 { 890 compatible = "mediatek,mt8183-i2c"; 891 reg = <0 0x11014000 0 0x1000>, 892 <0 0x11000180 0 0x80>; 893 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 894 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 895 <&infracfg CLK_INFRA_AP_DMA>, 896 <&infracfg CLK_INFRA_I2C1_ARBITER>; 897 clock-names = "main", "dma", "arb"; 898 clock-div = <1>; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 status = "disabled"; 902 }; 903 904 i2c10: i2c@11015000 { 905 compatible = "mediatek,mt8183-i2c"; 906 reg = <0 0x11015000 0 0x1000>, 907 <0 0x11000300 0 0x80>; 908 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 909 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 910 <&infracfg CLK_INFRA_AP_DMA>, 911 <&infracfg CLK_INFRA_I2C2_ARBITER>; 912 clock-names = "main", "dma", "arb"; 913 clock-div = <1>; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 i2c5: i2c@11016000 { 920 compatible = "mediatek,mt8183-i2c"; 921 reg = <0 0x11016000 0 0x1000>, 922 <0 0x11000500 0 0x80>; 923 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 924 clocks = <&infracfg CLK_INFRA_I2C5>, 925 <&infracfg CLK_INFRA_AP_DMA>, 926 <&infracfg CLK_INFRA_I2C5_ARBITER>; 927 clock-names = "main", "dma", "arb"; 928 clock-div = <1>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 status = "disabled"; 932 }; 933 934 i2c11: i2c@11017000 { 935 compatible = "mediatek,mt8183-i2c"; 936 reg = <0 0x11017000 0 0x1000>, 937 <0 0x11000580 0 0x80>; 938 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 939 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 940 <&infracfg CLK_INFRA_AP_DMA>, 941 <&infracfg CLK_INFRA_I2C5_ARBITER>; 942 clock-names = "main", "dma", "arb"; 943 clock-div = <1>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 status = "disabled"; 947 }; 948 949 spi4: spi@11018000 { 950 compatible = "mediatek,mt8183-spi"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 reg = <0 0x11018000 0 0x1000>; 954 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 955 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 956 <&topckgen CLK_TOP_MUX_SPI>, 957 <&infracfg CLK_INFRA_SPI4>; 958 clock-names = "parent-clk", "sel-clk", "spi-clk"; 959 status = "disabled"; 960 }; 961 962 spi5: spi@11019000 { 963 compatible = "mediatek,mt8183-spi"; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 reg = <0 0x11019000 0 0x1000>; 967 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 968 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 969 <&topckgen CLK_TOP_MUX_SPI>, 970 <&infracfg CLK_INFRA_SPI5>; 971 clock-names = "parent-clk", "sel-clk", "spi-clk"; 972 status = "disabled"; 973 }; 974 975 i2c7: i2c@1101a000 { 976 compatible = "mediatek,mt8183-i2c"; 977 reg = <0 0x1101a000 0 0x1000>, 978 <0 0x11000680 0 0x80>; 979 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 980 clocks = <&infracfg CLK_INFRA_I2C7>, 981 <&infracfg CLK_INFRA_AP_DMA>; 982 clock-names = "main", "dma"; 983 clock-div = <1>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 status = "disabled"; 987 }; 988 989 i2c8: i2c@1101b000 { 990 compatible = "mediatek,mt8183-i2c"; 991 reg = <0 0x1101b000 0 0x1000>, 992 <0 0x11000700 0 0x80>; 993 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 994 clocks = <&infracfg CLK_INFRA_I2C8>, 995 <&infracfg CLK_INFRA_AP_DMA>; 996 clock-names = "main", "dma"; 997 clock-div = <1>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 ssusb: usb@11201000 { 1004 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 1005 reg = <0 0x11201000 0 0x2e00>, 1006 <0 0x11203e00 0 0x0100>; 1007 reg-names = "mac", "ippc"; 1008 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 1009 phys = <&u2port0 PHY_TYPE_USB2>, 1010 <&u3port0 PHY_TYPE_USB3>; 1011 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1012 <&infracfg CLK_INFRA_USB>; 1013 clock-names = "sys_ck", "ref_ck"; 1014 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 1015 #address-cells = <2>; 1016 #size-cells = <2>; 1017 ranges; 1018 status = "disabled"; 1019 1020 usb_host: usb@11200000 { 1021 compatible = "mediatek,mt8183-xhci", 1022 "mediatek,mtk-xhci"; 1023 reg = <0 0x11200000 0 0x1000>; 1024 reg-names = "mac"; 1025 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 1026 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1027 <&infracfg CLK_INFRA_USB>; 1028 clock-names = "sys_ck", "ref_ck"; 1029 status = "disabled"; 1030 }; 1031 }; 1032 1033 audiosys: syscon@11220000 { 1034 compatible = "mediatek,mt8183-audiosys", "syscon"; 1035 reg = <0 0x11220000 0 0x1000>; 1036 #clock-cells = <1>; 1037 }; 1038 1039 mmc0: mmc@11230000 { 1040 compatible = "mediatek,mt8183-mmc"; 1041 reg = <0 0x11230000 0 0x1000>, 1042 <0 0x11f50000 0 0x1000>; 1043 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1044 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1045 <&infracfg CLK_INFRA_MSDC0>, 1046 <&infracfg CLK_INFRA_MSDC0_SCK>; 1047 clock-names = "source", "hclk", "source_cg"; 1048 status = "disabled"; 1049 }; 1050 1051 mmc1: mmc@11240000 { 1052 compatible = "mediatek,mt8183-mmc"; 1053 reg = <0 0x11240000 0 0x1000>, 1054 <0 0x11e10000 0 0x1000>; 1055 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1056 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1057 <&infracfg CLK_INFRA_MSDC1>, 1058 <&infracfg CLK_INFRA_MSDC1_SCK>; 1059 clock-names = "source", "hclk", "source_cg"; 1060 status = "disabled"; 1061 }; 1062 1063 mipi_tx0: dsi-phy@11e50000 { 1064 compatible = "mediatek,mt8183-mipi-tx"; 1065 reg = <0 0x11e50000 0 0x1000>; 1066 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1067 #clock-cells = <0>; 1068 #phy-cells = <0>; 1069 clock-output-names = "mipi_tx0_pll"; 1070 nvmem-cells = <&mipi_tx_calibration>; 1071 nvmem-cell-names = "calibration-data"; 1072 }; 1073 1074 efuse: efuse@11f10000 { 1075 compatible = "mediatek,mt8183-efuse", 1076 "mediatek,efuse"; 1077 reg = <0 0x11f10000 0 0x1000>; 1078 #address-cells = <1>; 1079 #size-cells = <1>; 1080 thermal_calibration: calib@180 { 1081 reg = <0x180 0xc>; 1082 }; 1083 1084 mipi_tx_calibration: calib@190 { 1085 reg = <0x190 0xc>; 1086 }; 1087 }; 1088 1089 u3phy: t-phy@11f40000 { 1090 compatible = "mediatek,mt8183-tphy", 1091 "mediatek,generic-tphy-v2"; 1092 #address-cells = <1>; 1093 #size-cells = <1>; 1094 ranges = <0 0 0x11f40000 0x1000>; 1095 status = "okay"; 1096 1097 u2port0: usb-phy@0 { 1098 reg = <0x0 0x700>; 1099 clocks = <&clk26m>; 1100 clock-names = "ref"; 1101 #phy-cells = <1>; 1102 mediatek,discth = <15>; 1103 status = "okay"; 1104 }; 1105 1106 u3port0: usb-phy@700 { 1107 reg = <0x0700 0x900>; 1108 clocks = <&clk26m>; 1109 clock-names = "ref"; 1110 #phy-cells = <1>; 1111 status = "okay"; 1112 }; 1113 }; 1114 1115 mfgcfg: syscon@13000000 { 1116 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1117 reg = <0 0x13000000 0 0x1000>; 1118 #clock-cells = <1>; 1119 }; 1120 1121 mmsys: syscon@14000000 { 1122 compatible = "mediatek,mt8183-mmsys", "syscon"; 1123 reg = <0 0x14000000 0 0x1000>; 1124 #clock-cells = <1>; 1125 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1126 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1127 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1128 }; 1129 1130 ovl0: ovl@14008000 { 1131 compatible = "mediatek,mt8183-disp-ovl"; 1132 reg = <0 0x14008000 0 0x1000>; 1133 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1134 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1135 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1136 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1137 mediatek,larb = <&larb0>; 1138 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1139 }; 1140 1141 ovl_2l0: ovl@14009000 { 1142 compatible = "mediatek,mt8183-disp-ovl-2l"; 1143 reg = <0 0x14009000 0 0x1000>; 1144 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1145 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1146 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1147 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1148 mediatek,larb = <&larb0>; 1149 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1150 }; 1151 1152 ovl_2l1: ovl@1400a000 { 1153 compatible = "mediatek,mt8183-disp-ovl-2l"; 1154 reg = <0 0x1400a000 0 0x1000>; 1155 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1156 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1157 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1158 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1159 mediatek,larb = <&larb0>; 1160 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1161 }; 1162 1163 rdma0: rdma@1400b000 { 1164 compatible = "mediatek,mt8183-disp-rdma"; 1165 reg = <0 0x1400b000 0 0x1000>; 1166 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1167 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1168 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1169 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1170 mediatek,larb = <&larb0>; 1171 mediatek,rdma-fifo-size = <5120>; 1172 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1173 }; 1174 1175 rdma1: rdma@1400c000 { 1176 compatible = "mediatek,mt8183-disp-rdma"; 1177 reg = <0 0x1400c000 0 0x1000>; 1178 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1179 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1180 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1181 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1182 mediatek,larb = <&larb0>; 1183 mediatek,rdma-fifo-size = <2048>; 1184 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1185 }; 1186 1187 color0: color@1400e000 { 1188 compatible = "mediatek,mt8183-disp-color", 1189 "mediatek,mt8173-disp-color"; 1190 reg = <0 0x1400e000 0 0x1000>; 1191 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1192 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1193 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1194 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1195 }; 1196 1197 ccorr0: ccorr@1400f000 { 1198 compatible = "mediatek,mt8183-disp-ccorr"; 1199 reg = <0 0x1400f000 0 0x1000>; 1200 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1201 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1202 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1203 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1204 }; 1205 1206 aal0: aal@14010000 { 1207 compatible = "mediatek,mt8183-disp-aal", 1208 "mediatek,mt8173-disp-aal"; 1209 reg = <0 0x14010000 0 0x1000>; 1210 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1211 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1212 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1213 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1214 }; 1215 1216 gamma0: gamma@14011000 { 1217 compatible = "mediatek,mt8183-disp-gamma"; 1218 reg = <0 0x14011000 0 0x1000>; 1219 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1220 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1221 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1222 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1223 }; 1224 1225 dither0: dither@14012000 { 1226 compatible = "mediatek,mt8183-disp-dither"; 1227 reg = <0 0x14012000 0 0x1000>; 1228 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 1229 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1230 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1231 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1232 }; 1233 1234 dsi0: dsi@14014000 { 1235 compatible = "mediatek,mt8183-dsi"; 1236 reg = <0 0x14014000 0 0x1000>; 1237 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 1238 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1239 mediatek,syscon-dsi = <&mmsys 0x140>; 1240 clocks = <&mmsys CLK_MM_DSI0_MM>, 1241 <&mmsys CLK_MM_DSI0_IF>, 1242 <&mipi_tx0>; 1243 clock-names = "engine", "digital", "hs"; 1244 phys = <&mipi_tx0>; 1245 phy-names = "dphy"; 1246 }; 1247 1248 mutex: mutex@14016000 { 1249 compatible = "mediatek,mt8183-disp-mutex"; 1250 reg = <0 0x14016000 0 0x1000>; 1251 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 1252 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1253 }; 1254 1255 larb0: larb@14017000 { 1256 compatible = "mediatek,mt8183-smi-larb"; 1257 reg = <0 0x14017000 0 0x1000>; 1258 mediatek,smi = <&smi_common>; 1259 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1260 <&mmsys CLK_MM_SMI_LARB0>; 1261 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1262 clock-names = "apb", "smi"; 1263 }; 1264 1265 smi_common: smi@14019000 { 1266 compatible = "mediatek,mt8183-smi-common", "syscon"; 1267 reg = <0 0x14019000 0 0x1000>; 1268 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1269 <&mmsys CLK_MM_SMI_COMMON>, 1270 <&mmsys CLK_MM_GALS_COMM0>, 1271 <&mmsys CLK_MM_GALS_COMM1>; 1272 clock-names = "apb", "smi", "gals0", "gals1"; 1273 }; 1274 1275 imgsys: syscon@15020000 { 1276 compatible = "mediatek,mt8183-imgsys", "syscon"; 1277 reg = <0 0x15020000 0 0x1000>; 1278 #clock-cells = <1>; 1279 }; 1280 1281 larb5: larb@15021000 { 1282 compatible = "mediatek,mt8183-smi-larb"; 1283 reg = <0 0x15021000 0 0x1000>; 1284 mediatek,smi = <&smi_common>; 1285 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1286 <&mmsys CLK_MM_GALS_IMG2MM>; 1287 clock-names = "apb", "smi", "gals"; 1288 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1289 }; 1290 1291 larb2: larb@1502f000 { 1292 compatible = "mediatek,mt8183-smi-larb"; 1293 reg = <0 0x1502f000 0 0x1000>; 1294 mediatek,smi = <&smi_common>; 1295 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1296 <&mmsys CLK_MM_GALS_IPU2MM>; 1297 clock-names = "apb", "smi", "gals"; 1298 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1299 }; 1300 1301 vdecsys: syscon@16000000 { 1302 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1303 reg = <0 0x16000000 0 0x1000>; 1304 #clock-cells = <1>; 1305 }; 1306 1307 larb1: larb@16010000 { 1308 compatible = "mediatek,mt8183-smi-larb"; 1309 reg = <0 0x16010000 0 0x1000>; 1310 mediatek,smi = <&smi_common>; 1311 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1312 clock-names = "apb", "smi"; 1313 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1314 }; 1315 1316 vencsys: syscon@17000000 { 1317 compatible = "mediatek,mt8183-vencsys", "syscon"; 1318 reg = <0 0x17000000 0 0x1000>; 1319 #clock-cells = <1>; 1320 }; 1321 1322 larb4: larb@17010000 { 1323 compatible = "mediatek,mt8183-smi-larb"; 1324 reg = <0 0x17010000 0 0x1000>; 1325 mediatek,smi = <&smi_common>; 1326 clocks = <&vencsys CLK_VENC_LARB>, 1327 <&vencsys CLK_VENC_LARB>; 1328 clock-names = "apb", "smi"; 1329 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1330 }; 1331 1332 ipu_conn: syscon@19000000 { 1333 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1334 reg = <0 0x19000000 0 0x1000>; 1335 #clock-cells = <1>; 1336 }; 1337 1338 ipu_adl: syscon@19010000 { 1339 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1340 reg = <0 0x19010000 0 0x1000>; 1341 #clock-cells = <1>; 1342 }; 1343 1344 ipu_core0: syscon@19180000 { 1345 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1346 reg = <0 0x19180000 0 0x1000>; 1347 #clock-cells = <1>; 1348 }; 1349 1350 ipu_core1: syscon@19280000 { 1351 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 1352 reg = <0 0x19280000 0 0x1000>; 1353 #clock-cells = <1>; 1354 }; 1355 1356 camsys: syscon@1a000000 { 1357 compatible = "mediatek,mt8183-camsys", "syscon"; 1358 reg = <0 0x1a000000 0 0x1000>; 1359 #clock-cells = <1>; 1360 }; 1361 1362 larb6: larb@1a001000 { 1363 compatible = "mediatek,mt8183-smi-larb"; 1364 reg = <0 0x1a001000 0 0x1000>; 1365 mediatek,smi = <&smi_common>; 1366 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 1367 <&mmsys CLK_MM_GALS_CAM2MM>; 1368 clock-names = "apb", "smi", "gals"; 1369 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1370 }; 1371 1372 larb3: larb@1a002000 { 1373 compatible = "mediatek,mt8183-smi-larb"; 1374 reg = <0 0x1a002000 0 0x1000>; 1375 mediatek,smi = <&smi_common>; 1376 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 1377 <&mmsys CLK_MM_GALS_IPU12MM>; 1378 clock-names = "apb", "smi", "gals"; 1379 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1380 }; 1381 }; 1382}; 1383