1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset-controller/mt8183-resets.h> 12#include "mt8183-pinfunc.h" 13 14/ { 15 compatible = "mediatek,mt8183"; 16 interrupt-parent = <&sysirq>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &i2c7; 29 i2c8 = &i2c8; 30 i2c9 = &i2c9; 31 i2c10 = &i2c10; 32 i2c11 = &i2c11; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&cpu0>; 43 }; 44 core1 { 45 cpu = <&cpu1>; 46 }; 47 core2 { 48 cpu = <&cpu2>; 49 }; 50 core3 { 51 cpu = <&cpu3>; 52 }; 53 }; 54 55 cluster1 { 56 core0 { 57 cpu = <&cpu4>; 58 }; 59 core1 { 60 cpu = <&cpu5>; 61 }; 62 core2 { 63 cpu = <&cpu6>; 64 }; 65 core3 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x000>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <741>; 77 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 78 dynamic-power-coefficient = <84>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x001>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <741>; 88 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 89 dynamic-power-coefficient = <84>; 90 #cooling-cells = <2>; 91 }; 92 93 cpu2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x002>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <741>; 99 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 100 dynamic-power-coefficient = <84>; 101 #cooling-cells = <2>; 102 }; 103 104 cpu3: cpu@3 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53"; 107 reg = <0x003>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <741>; 110 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 111 dynamic-power-coefficient = <84>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu4: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a73"; 118 reg = <0x100>; 119 enable-method = "psci"; 120 capacity-dmips-mhz = <1024>; 121 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 122 dynamic-power-coefficient = <211>; 123 #cooling-cells = <2>; 124 }; 125 126 cpu5: cpu@101 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a73"; 129 reg = <0x101>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <1024>; 132 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 133 dynamic-power-coefficient = <211>; 134 #cooling-cells = <2>; 135 }; 136 137 cpu6: cpu@102 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a73"; 140 reg = <0x102>; 141 enable-method = "psci"; 142 capacity-dmips-mhz = <1024>; 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 144 dynamic-power-coefficient = <211>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu7: cpu@103 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a73"; 151 reg = <0x103>; 152 enable-method = "psci"; 153 capacity-dmips-mhz = <1024>; 154 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 155 dynamic-power-coefficient = <211>; 156 #cooling-cells = <2>; 157 }; 158 159 idle-states { 160 entry-method = "psci"; 161 162 CPU_SLEEP: cpu-sleep { 163 compatible = "arm,idle-state"; 164 local-timer-stop; 165 arm,psci-suspend-param = <0x00010001>; 166 entry-latency-us = <200>; 167 exit-latency-us = <200>; 168 min-residency-us = <800>; 169 }; 170 171 CLUSTER_SLEEP: cluster-sleep { 172 compatible = "arm,idle-state"; 173 local-timer-stop; 174 arm,psci-suspend-param = <0x01010001>; 175 entry-latency-us = <250>; 176 exit-latency-us = <400>; 177 min-residency-us = <1300>; 178 }; 179 }; 180 }; 181 182 pmu-a53 { 183 compatible = "arm,cortex-a53-pmu"; 184 interrupt-parent = <&gic>; 185 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 186 }; 187 188 pmu-a73 { 189 compatible = "arm,cortex-a73-pmu"; 190 interrupt-parent = <&gic>; 191 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 192 }; 193 194 psci { 195 compatible = "arm,psci-1.0"; 196 method = "smc"; 197 }; 198 199 clk26m: oscillator { 200 compatible = "fixed-clock"; 201 #clock-cells = <0>; 202 clock-frequency = <26000000>; 203 clock-output-names = "clk26m"; 204 }; 205 206 timer { 207 compatible = "arm,armv8-timer"; 208 interrupt-parent = <&gic>; 209 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 210 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 211 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 212 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 213 }; 214 215 soc { 216 #address-cells = <2>; 217 #size-cells = <2>; 218 compatible = "simple-bus"; 219 ranges; 220 221 soc_data: soc_data@8000000 { 222 compatible = "mediatek,mt8183-efuse", 223 "mediatek,efuse"; 224 reg = <0 0x08000000 0 0x0010>; 225 #address-cells = <1>; 226 #size-cells = <1>; 227 status = "disabled"; 228 }; 229 230 gic: interrupt-controller@c000000 { 231 compatible = "arm,gic-v3"; 232 #interrupt-cells = <4>; 233 interrupt-parent = <&gic>; 234 interrupt-controller; 235 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 236 <0 0x0c100000 0 0x200000>, /* GICR */ 237 <0 0x0c400000 0 0x2000>, /* GICC */ 238 <0 0x0c410000 0 0x1000>, /* GICH */ 239 <0 0x0c420000 0 0x2000>; /* GICV */ 240 241 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 242 ppi-partitions { 243 ppi_cluster0: interrupt-partition-0 { 244 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 245 }; 246 ppi_cluster1: interrupt-partition-1 { 247 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 248 }; 249 }; 250 }; 251 252 mcucfg: syscon@c530000 { 253 compatible = "mediatek,mt8183-mcucfg", "syscon"; 254 reg = <0 0x0c530000 0 0x1000>; 255 #clock-cells = <1>; 256 }; 257 258 sysirq: interrupt-controller@c530a80 { 259 compatible = "mediatek,mt8183-sysirq", 260 "mediatek,mt6577-sysirq"; 261 interrupt-controller; 262 #interrupt-cells = <3>; 263 interrupt-parent = <&gic>; 264 reg = <0 0x0c530a80 0 0x50>; 265 }; 266 267 topckgen: syscon@10000000 { 268 compatible = "mediatek,mt8183-topckgen", "syscon"; 269 reg = <0 0x10000000 0 0x1000>; 270 #clock-cells = <1>; 271 }; 272 273 infracfg: syscon@10001000 { 274 compatible = "mediatek,mt8183-infracfg", "syscon"; 275 reg = <0 0x10001000 0 0x1000>; 276 #clock-cells = <1>; 277 #reset-cells = <1>; 278 }; 279 280 pio: pinctrl@10005000 { 281 compatible = "mediatek,mt8183-pinctrl"; 282 reg = <0 0x10005000 0 0x1000>, 283 <0 0x11f20000 0 0x1000>, 284 <0 0x11e80000 0 0x1000>, 285 <0 0x11e70000 0 0x1000>, 286 <0 0x11e90000 0 0x1000>, 287 <0 0x11d30000 0 0x1000>, 288 <0 0x11d20000 0 0x1000>, 289 <0 0x11c50000 0 0x1000>, 290 <0 0x11f30000 0 0x1000>, 291 <0 0x1000b000 0 0x1000>; 292 reg-names = "iocfg0", "iocfg1", "iocfg2", 293 "iocfg3", "iocfg4", "iocfg5", 294 "iocfg6", "iocfg7", "iocfg8", 295 "eint"; 296 gpio-controller; 297 #gpio-cells = <2>; 298 gpio-ranges = <&pio 0 0 192>; 299 interrupt-controller; 300 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 301 #interrupt-cells = <2>; 302 }; 303 304 watchdog: watchdog@10007000 { 305 compatible = "mediatek,mt8183-wdt", 306 "mediatek,mt6589-wdt"; 307 reg = <0 0x10007000 0 0x100>; 308 #reset-cells = <1>; 309 }; 310 311 apmixedsys: syscon@1000c000 { 312 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 313 reg = <0 0x1000c000 0 0x1000>; 314 #clock-cells = <1>; 315 }; 316 317 pwrap: pwrap@1000d000 { 318 compatible = "mediatek,mt8183-pwrap"; 319 reg = <0 0x1000d000 0 0x1000>; 320 reg-names = "pwrap"; 321 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 323 <&infracfg CLK_INFRA_PMIC_AP>; 324 clock-names = "spi", "wrap"; 325 }; 326 327 systimer: timer@10017000 { 328 compatible = "mediatek,mt8183-timer", 329 "mediatek,mt6765-timer"; 330 reg = <0 0x10017000 0 0x1000>; 331 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&topckgen CLK_TOP_CLK13M>; 333 clock-names = "clk13m"; 334 }; 335 336 gce: mailbox@10238000 { 337 compatible = "mediatek,mt8183-gce"; 338 reg = <0 0x10238000 0 0x4000>; 339 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 340 #mbox-cells = <3>; 341 clocks = <&infracfg CLK_INFRA_GCE>; 342 clock-names = "gce"; 343 }; 344 345 auxadc: auxadc@11001000 { 346 compatible = "mediatek,mt8183-auxadc", 347 "mediatek,mt8173-auxadc"; 348 reg = <0 0x11001000 0 0x1000>; 349 clocks = <&infracfg CLK_INFRA_AUXADC>; 350 clock-names = "main"; 351 #io-channel-cells = <1>; 352 status = "disabled"; 353 }; 354 355 uart0: serial@11002000 { 356 compatible = "mediatek,mt8183-uart", 357 "mediatek,mt6577-uart"; 358 reg = <0 0x11002000 0 0x1000>; 359 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 360 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 361 clock-names = "baud", "bus"; 362 status = "disabled"; 363 }; 364 365 uart1: serial@11003000 { 366 compatible = "mediatek,mt8183-uart", 367 "mediatek,mt6577-uart"; 368 reg = <0 0x11003000 0 0x1000>; 369 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 370 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 371 clock-names = "baud", "bus"; 372 status = "disabled"; 373 }; 374 375 uart2: serial@11004000 { 376 compatible = "mediatek,mt8183-uart", 377 "mediatek,mt6577-uart"; 378 reg = <0 0x11004000 0 0x1000>; 379 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 380 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 381 clock-names = "baud", "bus"; 382 status = "disabled"; 383 }; 384 385 i2c6: i2c@11005000 { 386 compatible = "mediatek,mt8183-i2c"; 387 reg = <0 0x11005000 0 0x1000>, 388 <0 0x11000600 0 0x80>; 389 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 390 clocks = <&infracfg CLK_INFRA_I2C6>, 391 <&infracfg CLK_INFRA_AP_DMA>; 392 clock-names = "main", "dma"; 393 clock-div = <1>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 status = "disabled"; 397 }; 398 399 i2c0: i2c@11007000 { 400 compatible = "mediatek,mt8183-i2c"; 401 reg = <0 0x11007000 0 0x1000>, 402 <0 0x11000080 0 0x80>; 403 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 404 clocks = <&infracfg CLK_INFRA_I2C0>, 405 <&infracfg CLK_INFRA_AP_DMA>; 406 clock-names = "main", "dma"; 407 clock-div = <1>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 i2c4: i2c@11008000 { 414 compatible = "mediatek,mt8183-i2c"; 415 reg = <0 0x11008000 0 0x1000>, 416 <0 0x11000100 0 0x80>; 417 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 418 clocks = <&infracfg CLK_INFRA_I2C1>, 419 <&infracfg CLK_INFRA_AP_DMA>, 420 <&infracfg CLK_INFRA_I2C1_ARBITER>; 421 clock-names = "main", "dma","arb"; 422 clock-div = <1>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 i2c2: i2c@11009000 { 429 compatible = "mediatek,mt8183-i2c"; 430 reg = <0 0x11009000 0 0x1000>, 431 <0 0x11000280 0 0x80>; 432 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 433 clocks = <&infracfg CLK_INFRA_I2C2>, 434 <&infracfg CLK_INFRA_AP_DMA>, 435 <&infracfg CLK_INFRA_I2C2_ARBITER>; 436 clock-names = "main", "dma", "arb"; 437 clock-div = <1>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 status = "disabled"; 441 }; 442 443 spi0: spi@1100a000 { 444 compatible = "mediatek,mt8183-spi"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 reg = <0 0x1100a000 0 0x1000>; 448 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 449 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 450 <&topckgen CLK_TOP_MUX_SPI>, 451 <&infracfg CLK_INFRA_SPI0>; 452 clock-names = "parent-clk", "sel-clk", "spi-clk"; 453 status = "disabled"; 454 }; 455 456 i2c3: i2c@1100f000 { 457 compatible = "mediatek,mt8183-i2c"; 458 reg = <0 0x1100f000 0 0x1000>, 459 <0 0x11000400 0 0x80>; 460 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 461 clocks = <&infracfg CLK_INFRA_I2C3>, 462 <&infracfg CLK_INFRA_AP_DMA>; 463 clock-names = "main", "dma"; 464 clock-div = <1>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 status = "disabled"; 468 }; 469 470 spi1: spi@11010000 { 471 compatible = "mediatek,mt8183-spi"; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 reg = <0 0x11010000 0 0x1000>; 475 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 476 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 477 <&topckgen CLK_TOP_MUX_SPI>, 478 <&infracfg CLK_INFRA_SPI1>; 479 clock-names = "parent-clk", "sel-clk", "spi-clk"; 480 status = "disabled"; 481 }; 482 483 i2c1: i2c@11011000 { 484 compatible = "mediatek,mt8183-i2c"; 485 reg = <0 0x11011000 0 0x1000>, 486 <0 0x11000480 0 0x80>; 487 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 488 clocks = <&infracfg CLK_INFRA_I2C4>, 489 <&infracfg CLK_INFRA_AP_DMA>; 490 clock-names = "main", "dma"; 491 clock-div = <1>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 status = "disabled"; 495 }; 496 497 spi2: spi@11012000 { 498 compatible = "mediatek,mt8183-spi"; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 reg = <0 0x11012000 0 0x1000>; 502 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 503 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 504 <&topckgen CLK_TOP_MUX_SPI>, 505 <&infracfg CLK_INFRA_SPI2>; 506 clock-names = "parent-clk", "sel-clk", "spi-clk"; 507 status = "disabled"; 508 }; 509 510 spi3: spi@11013000 { 511 compatible = "mediatek,mt8183-spi"; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 reg = <0 0x11013000 0 0x1000>; 515 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 516 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 517 <&topckgen CLK_TOP_MUX_SPI>, 518 <&infracfg CLK_INFRA_SPI3>; 519 clock-names = "parent-clk", "sel-clk", "spi-clk"; 520 status = "disabled"; 521 }; 522 523 i2c9: i2c@11014000 { 524 compatible = "mediatek,mt8183-i2c"; 525 reg = <0 0x11014000 0 0x1000>, 526 <0 0x11000180 0 0x80>; 527 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 528 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 529 <&infracfg CLK_INFRA_AP_DMA>, 530 <&infracfg CLK_INFRA_I2C1_ARBITER>; 531 clock-names = "main", "dma", "arb"; 532 clock-div = <1>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 status = "disabled"; 536 }; 537 538 i2c10: i2c@11015000 { 539 compatible = "mediatek,mt8183-i2c"; 540 reg = <0 0x11015000 0 0x1000>, 541 <0 0x11000300 0 0x80>; 542 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 543 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 544 <&infracfg CLK_INFRA_AP_DMA>, 545 <&infracfg CLK_INFRA_I2C2_ARBITER>; 546 clock-names = "main", "dma", "arb"; 547 clock-div = <1>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 i2c5: i2c@11016000 { 554 compatible = "mediatek,mt8183-i2c"; 555 reg = <0 0x11016000 0 0x1000>, 556 <0 0x11000500 0 0x80>; 557 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 558 clocks = <&infracfg CLK_INFRA_I2C5>, 559 <&infracfg CLK_INFRA_AP_DMA>, 560 <&infracfg CLK_INFRA_I2C5_ARBITER>; 561 clock-names = "main", "dma", "arb"; 562 clock-div = <1>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 i2c11: i2c@11017000 { 569 compatible = "mediatek,mt8183-i2c"; 570 reg = <0 0x11017000 0 0x1000>, 571 <0 0x11000580 0 0x80>; 572 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 573 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 574 <&infracfg CLK_INFRA_AP_DMA>, 575 <&infracfg CLK_INFRA_I2C5_ARBITER>; 576 clock-names = "main", "dma", "arb"; 577 clock-div = <1>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 status = "disabled"; 581 }; 582 583 spi4: spi@11018000 { 584 compatible = "mediatek,mt8183-spi"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 reg = <0 0x11018000 0 0x1000>; 588 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 589 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 590 <&topckgen CLK_TOP_MUX_SPI>, 591 <&infracfg CLK_INFRA_SPI4>; 592 clock-names = "parent-clk", "sel-clk", "spi-clk"; 593 status = "disabled"; 594 }; 595 596 spi5: spi@11019000 { 597 compatible = "mediatek,mt8183-spi"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 reg = <0 0x11019000 0 0x1000>; 601 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 602 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 603 <&topckgen CLK_TOP_MUX_SPI>, 604 <&infracfg CLK_INFRA_SPI5>; 605 clock-names = "parent-clk", "sel-clk", "spi-clk"; 606 status = "disabled"; 607 }; 608 609 i2c7: i2c@1101a000 { 610 compatible = "mediatek,mt8183-i2c"; 611 reg = <0 0x1101a000 0 0x1000>, 612 <0 0x11000680 0 0x80>; 613 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 614 clocks = <&infracfg CLK_INFRA_I2C7>, 615 <&infracfg CLK_INFRA_AP_DMA>; 616 clock-names = "main", "dma"; 617 clock-div = <1>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 i2c8: i2c@1101b000 { 624 compatible = "mediatek,mt8183-i2c"; 625 reg = <0 0x1101b000 0 0x1000>, 626 <0 0x11000700 0 0x80>; 627 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 628 clocks = <&infracfg CLK_INFRA_I2C8>, 629 <&infracfg CLK_INFRA_AP_DMA>; 630 clock-names = "main", "dma"; 631 clock-div = <1>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 status = "disabled"; 635 }; 636 637 audiosys: syscon@11220000 { 638 compatible = "mediatek,mt8183-audiosys", "syscon"; 639 reg = <0 0x11220000 0 0x1000>; 640 #clock-cells = <1>; 641 }; 642 643 efuse: efuse@11f10000 { 644 compatible = "mediatek,mt8183-efuse", 645 "mediatek,efuse"; 646 reg = <0 0x11f10000 0 0x1000>; 647 }; 648 649 mfgcfg: syscon@13000000 { 650 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 651 reg = <0 0x13000000 0 0x1000>; 652 #clock-cells = <1>; 653 }; 654 655 mmsys: syscon@14000000 { 656 compatible = "mediatek,mt8183-mmsys", "syscon"; 657 reg = <0 0x14000000 0 0x1000>; 658 #clock-cells = <1>; 659 }; 660 661 imgsys: syscon@15020000 { 662 compatible = "mediatek,mt8183-imgsys", "syscon"; 663 reg = <0 0x15020000 0 0x1000>; 664 #clock-cells = <1>; 665 }; 666 667 vdecsys: syscon@16000000 { 668 compatible = "mediatek,mt8183-vdecsys", "syscon"; 669 reg = <0 0x16000000 0 0x1000>; 670 #clock-cells = <1>; 671 }; 672 673 vencsys: syscon@17000000 { 674 compatible = "mediatek,mt8183-vencsys", "syscon"; 675 reg = <0 0x17000000 0 0x1000>; 676 #clock-cells = <1>; 677 }; 678 679 ipu_conn: syscon@19000000 { 680 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 681 reg = <0 0x19000000 0 0x1000>; 682 #clock-cells = <1>; 683 }; 684 685 ipu_adl: syscon@19010000 { 686 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 687 reg = <0 0x19010000 0 0x1000>; 688 #clock-cells = <1>; 689 }; 690 691 ipu_core0: syscon@19180000 { 692 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 693 reg = <0 0x19180000 0 0x1000>; 694 #clock-cells = <1>; 695 }; 696 697 ipu_core1: syscon@19280000 { 698 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 699 reg = <0 0x19280000 0 0x1000>; 700 #clock-cells = <1>; 701 }; 702 703 camsys: syscon@1a000000 { 704 compatible = "mediatek,mt8183-camsys", "syscon"; 705 reg = <0 0x1a000000 0 0x1000>; 706 #clock-cells = <1>; 707 }; 708 }; 709}; 710