1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/clock/mt8173-clk.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/memory/mt8173-larb-port.h>
18#include <dt-bindings/phy/phy.h>
19#include <dt-bindings/power/mt8173-power.h>
20#include <dt-bindings/reset/mt8173-resets.h>
21#include <dt-bindings/gce/mt8173-gce.h>
22#include "mt8173-pinfunc.h"
23
24/ {
25	compatible = "mediatek,mt8173";
26	interrupt-parent = <&sysirq>;
27	#address-cells = <2>;
28	#size-cells = <2>;
29
30	aliases {
31		ovl0 = &ovl0;
32		ovl1 = &ovl1;
33		rdma0 = &rdma0;
34		rdma1 = &rdma1;
35		rdma2 = &rdma2;
36		wdma0 = &wdma0;
37		wdma1 = &wdma1;
38		color0 = &color0;
39		color1 = &color1;
40		split0 = &split0;
41		split1 = &split1;
42		dpi0 = &dpi0;
43		dsi0 = &dsi0;
44		dsi1 = &dsi1;
45		mdp_rdma0 = &mdp_rdma0;
46		mdp_rdma1 = &mdp_rdma1;
47		mdp_rsz0 = &mdp_rsz0;
48		mdp_rsz1 = &mdp_rsz1;
49		mdp_rsz2 = &mdp_rsz2;
50		mdp_wdma0 = &mdp_wdma0;
51		mdp_wrot0 = &mdp_wrot0;
52		mdp_wrot1 = &mdp_wrot1;
53	};
54
55	cluster0_opp: opp_table0 {
56		compatible = "operating-points-v2";
57		opp-shared;
58		opp-507000000 {
59			opp-hz = /bits/ 64 <507000000>;
60			opp-microvolt = <859000>;
61		};
62		opp-702000000 {
63			opp-hz = /bits/ 64 <702000000>;
64			opp-microvolt = <908000>;
65		};
66		opp-1001000000 {
67			opp-hz = /bits/ 64 <1001000000>;
68			opp-microvolt = <983000>;
69		};
70		opp-1105000000 {
71			opp-hz = /bits/ 64 <1105000000>;
72			opp-microvolt = <1009000>;
73		};
74		opp-1209000000 {
75			opp-hz = /bits/ 64 <1209000000>;
76			opp-microvolt = <1034000>;
77		};
78		opp-1300000000 {
79			opp-hz = /bits/ 64 <1300000000>;
80			opp-microvolt = <1057000>;
81		};
82		opp-1508000000 {
83			opp-hz = /bits/ 64 <1508000000>;
84			opp-microvolt = <1109000>;
85		};
86		opp-1703000000 {
87			opp-hz = /bits/ 64 <1703000000>;
88			opp-microvolt = <1125000>;
89		};
90	};
91
92	cluster1_opp: opp_table1 {
93		compatible = "operating-points-v2";
94		opp-shared;
95		opp-507000000 {
96			opp-hz = /bits/ 64 <507000000>;
97			opp-microvolt = <828000>;
98		};
99		opp-702000000 {
100			opp-hz = /bits/ 64 <702000000>;
101			opp-microvolt = <867000>;
102		};
103		opp-1001000000 {
104			opp-hz = /bits/ 64 <1001000000>;
105			opp-microvolt = <927000>;
106		};
107		opp-1209000000 {
108			opp-hz = /bits/ 64 <1209000000>;
109			opp-microvolt = <968000>;
110		};
111		opp-1404000000 {
112			opp-hz = /bits/ 64 <1404000000>;
113			opp-microvolt = <1007000>;
114		};
115		opp-1612000000 {
116			opp-hz = /bits/ 64 <1612000000>;
117			opp-microvolt = <1049000>;
118		};
119		opp-1807000000 {
120			opp-hz = /bits/ 64 <1807000000>;
121			opp-microvolt = <1089000>;
122		};
123		opp-2106000000 {
124			opp-hz = /bits/ 64 <2106000000>;
125			opp-microvolt = <1125000>;
126		};
127	};
128
129	cpus {
130		#address-cells = <1>;
131		#size-cells = <0>;
132
133		cpu-map {
134			cluster0 {
135				core0 {
136					cpu = <&cpu0>;
137				};
138				core1 {
139					cpu = <&cpu1>;
140				};
141			};
142
143			cluster1 {
144				core0 {
145					cpu = <&cpu2>;
146				};
147				core1 {
148					cpu = <&cpu3>;
149				};
150			};
151		};
152
153		cpu0: cpu@0 {
154			device_type = "cpu";
155			compatible = "arm,cortex-a53";
156			reg = <0x000>;
157			enable-method = "psci";
158			cpu-idle-states = <&CPU_SLEEP_0>;
159			#cooling-cells = <2>;
160			clocks = <&infracfg CLK_INFRA_CA53SEL>,
161				 <&apmixedsys CLK_APMIXED_MAINPLL>;
162			clock-names = "cpu", "intermediate";
163			operating-points-v2 = <&cluster0_opp>;
164		};
165
166		cpu1: cpu@1 {
167			device_type = "cpu";
168			compatible = "arm,cortex-a53";
169			reg = <0x001>;
170			enable-method = "psci";
171			cpu-idle-states = <&CPU_SLEEP_0>;
172			#cooling-cells = <2>;
173			clocks = <&infracfg CLK_INFRA_CA53SEL>,
174				 <&apmixedsys CLK_APMIXED_MAINPLL>;
175			clock-names = "cpu", "intermediate";
176			operating-points-v2 = <&cluster0_opp>;
177		};
178
179		cpu2: cpu@100 {
180			device_type = "cpu";
181			compatible = "arm,cortex-a72";
182			reg = <0x100>;
183			enable-method = "psci";
184			cpu-idle-states = <&CPU_SLEEP_0>;
185			#cooling-cells = <2>;
186			clocks = <&infracfg CLK_INFRA_CA72SEL>,
187				 <&apmixedsys CLK_APMIXED_MAINPLL>;
188			clock-names = "cpu", "intermediate";
189			operating-points-v2 = <&cluster1_opp>;
190		};
191
192		cpu3: cpu@101 {
193			device_type = "cpu";
194			compatible = "arm,cortex-a72";
195			reg = <0x101>;
196			enable-method = "psci";
197			cpu-idle-states = <&CPU_SLEEP_0>;
198			#cooling-cells = <2>;
199			clocks = <&infracfg CLK_INFRA_CA72SEL>,
200				 <&apmixedsys CLK_APMIXED_MAINPLL>;
201			clock-names = "cpu", "intermediate";
202			operating-points-v2 = <&cluster1_opp>;
203		};
204
205		idle-states {
206			entry-method = "psci";
207
208			CPU_SLEEP_0: cpu-sleep-0 {
209				compatible = "arm,idle-state";
210				local-timer-stop;
211				entry-latency-us = <639>;
212				exit-latency-us = <680>;
213				min-residency-us = <1088>;
214				arm,psci-suspend-param = <0x0010000>;
215			};
216		};
217	};
218
219	pmu_a53 {
220		compatible = "arm,cortex-a53-pmu";
221		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
222			     <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
223		interrupt-affinity = <&cpu0>, <&cpu1>;
224	};
225
226	pmu_a72 {
227		compatible = "arm,cortex-a72-pmu";
228		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
229			     <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
230		interrupt-affinity = <&cpu2>, <&cpu3>;
231	};
232
233	psci {
234		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
235		method = "smc";
236		cpu_suspend   = <0x84000001>;
237		cpu_off	      = <0x84000002>;
238		cpu_on	      = <0x84000003>;
239	};
240
241	clk26m: oscillator@0 {
242		compatible = "fixed-clock";
243		#clock-cells = <0>;
244		clock-frequency = <26000000>;
245		clock-output-names = "clk26m";
246	};
247
248	clk32k: oscillator@1 {
249		compatible = "fixed-clock";
250		#clock-cells = <0>;
251		clock-frequency = <32000>;
252		clock-output-names = "clk32k";
253	};
254
255	cpum_ck: oscillator@2 {
256		compatible = "fixed-clock";
257		#clock-cells = <0>;
258		clock-frequency = <0>;
259		clock-output-names = "cpum_ck";
260	};
261
262	thermal-zones {
263		cpu_thermal: cpu_thermal {
264			polling-delay-passive = <1000>; /* milliseconds */
265			polling-delay = <1000>; /* milliseconds */
266
267			thermal-sensors = <&thermal>;
268			sustainable-power = <1500>; /* milliwatts */
269
270			trips {
271				threshold: trip-point@0 {
272					temperature = <68000>;
273					hysteresis = <2000>;
274					type = "passive";
275				};
276
277				target: trip-point@1 {
278					temperature = <85000>;
279					hysteresis = <2000>;
280					type = "passive";
281				};
282
283				cpu_crit: cpu_crit@0 {
284					temperature = <115000>;
285					hysteresis = <2000>;
286					type = "critical";
287				};
288			};
289
290			cooling-maps {
291				map@0 {
292					trip = <&target>;
293					cooling-device = <&cpu0 0 0>,
294							 <&cpu1 0 0>;
295					contribution = <3072>;
296				};
297				map@1 {
298					trip = <&target>;
299					cooling-device = <&cpu2 0 0>,
300							 <&cpu3 0 0>;
301					contribution = <1024>;
302				};
303			};
304		};
305	};
306
307	reserved-memory {
308		#address-cells = <2>;
309		#size-cells = <2>;
310		ranges;
311		vpu_dma_reserved: vpu_dma_mem_region {
312			compatible = "shared-dma-pool";
313			reg = <0 0xb7000000 0 0x500000>;
314			alignment = <0x1000>;
315			no-map;
316		};
317	};
318
319	timer {
320		compatible = "arm,armv8-timer";
321		interrupt-parent = <&gic>;
322		interrupts = <GIC_PPI 13
323			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
324			     <GIC_PPI 14
325			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
326			     <GIC_PPI 11
327			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
328			     <GIC_PPI 10
329			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
330	};
331
332	soc {
333		#address-cells = <2>;
334		#size-cells = <2>;
335		compatible = "simple-bus";
336		ranges;
337
338		topckgen: clock-controller@10000000 {
339			compatible = "mediatek,mt8173-topckgen";
340			reg = <0 0x10000000 0 0x1000>;
341			#clock-cells = <1>;
342		};
343
344		infracfg: power-controller@10001000 {
345			compatible = "mediatek,mt8173-infracfg", "syscon";
346			reg = <0 0x10001000 0 0x1000>;
347			#clock-cells = <1>;
348			#reset-cells = <1>;
349		};
350
351		pericfg: power-controller@10003000 {
352			compatible = "mediatek,mt8173-pericfg", "syscon";
353			reg = <0 0x10003000 0 0x1000>;
354			#clock-cells = <1>;
355			#reset-cells = <1>;
356		};
357
358		syscfg_pctl_a: syscfg_pctl_a@10005000 {
359			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
360			reg = <0 0x10005000 0 0x1000>;
361		};
362
363		pio: pinctrl@10005000 {
364			compatible = "mediatek,mt8173-pinctrl";
365			reg = <0 0x1000b000 0 0x1000>;
366			mediatek,pctl-regmap = <&syscfg_pctl_a>;
367			pins-are-numbered;
368			gpio-controller;
369			#gpio-cells = <2>;
370			interrupt-controller;
371			#interrupt-cells = <2>;
372			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
373				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
374				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
375
376			hdmi_pin: xxx {
377
378				/*hdmi htplg pin*/
379				pins1 {
380					pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
381					input-enable;
382					bias-pull-down;
383				};
384			};
385
386			i2c0_pins_a: i2c0 {
387				pins1 {
388					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
389						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
390					bias-disable;
391				};
392			};
393
394			i2c1_pins_a: i2c1 {
395				pins1 {
396					pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
397						 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
398					bias-disable;
399				};
400			};
401
402			i2c2_pins_a: i2c2 {
403				pins1 {
404					pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
405						 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
406					bias-disable;
407				};
408			};
409
410			i2c3_pins_a: i2c3 {
411				pins1 {
412					pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
413						 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
414					bias-disable;
415				};
416			};
417
418			i2c4_pins_a: i2c4 {
419				pins1 {
420					pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
421						 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
422					bias-disable;
423				};
424			};
425
426			i2c6_pins_a: i2c6 {
427				pins1 {
428					pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
429						 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
430					bias-disable;
431				};
432			};
433		};
434
435		scpsys: scpsys@10006000 {
436			compatible = "mediatek,mt8173-scpsys";
437			#power-domain-cells = <1>;
438			reg = <0 0x10006000 0 0x1000>;
439			clocks = <&clk26m>,
440				 <&topckgen CLK_TOP_MM_SEL>,
441				 <&topckgen CLK_TOP_VENC_SEL>,
442				 <&topckgen CLK_TOP_VENC_LT_SEL>;
443			clock-names = "mfg", "mm", "venc", "venc_lt";
444			infracfg = <&infracfg>;
445		};
446
447		watchdog: watchdog@10007000 {
448			compatible = "mediatek,mt8173-wdt",
449				     "mediatek,mt6589-wdt";
450			reg = <0 0x10007000 0 0x100>;
451		};
452
453		timer: timer@10008000 {
454			compatible = "mediatek,mt8173-timer",
455				     "mediatek,mt6577-timer";
456			reg = <0 0x10008000 0 0x1000>;
457			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
458			clocks = <&infracfg CLK_INFRA_CLK_13M>,
459				 <&topckgen CLK_TOP_RTC_SEL>;
460		};
461
462		pwrap: pwrap@1000d000 {
463			compatible = "mediatek,mt8173-pwrap";
464			reg = <0 0x1000d000 0 0x1000>;
465			reg-names = "pwrap";
466			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
467			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
468			reset-names = "pwrap";
469			clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
470			clock-names = "spi", "wrap";
471		};
472
473		cec: cec@10013000 {
474			compatible = "mediatek,mt8173-cec";
475			reg = <0 0x10013000 0 0xbc>;
476			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
477			clocks = <&infracfg CLK_INFRA_CEC>;
478			status = "disabled";
479		};
480
481		vpu: vpu@10020000 {
482			compatible = "mediatek,mt8173-vpu";
483			reg = <0 0x10020000 0 0x30000>,
484			      <0 0x10050000 0 0x100>;
485			reg-names = "tcm", "cfg_reg";
486			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
487			clocks = <&topckgen CLK_TOP_SCP_SEL>;
488			clock-names = "main";
489			memory-region = <&vpu_dma_reserved>;
490		};
491
492		sysirq: intpol-controller@10200620 {
493			compatible = "mediatek,mt8173-sysirq",
494				     "mediatek,mt6577-sysirq";
495			interrupt-controller;
496			#interrupt-cells = <3>;
497			interrupt-parent = <&gic>;
498			reg = <0 0x10200620 0 0x20>;
499		};
500
501		iommu: iommu@10205000 {
502			compatible = "mediatek,mt8173-m4u";
503			reg = <0 0x10205000 0 0x1000>;
504			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
505			clocks = <&infracfg CLK_INFRA_M4U>;
506			clock-names = "bclk";
507			mediatek,larbs = <&larb0 &larb1 &larb2
508					  &larb3 &larb4 &larb5>;
509			#iommu-cells = <1>;
510		};
511
512		efuse: efuse@10206000 {
513			compatible = "mediatek,mt8173-efuse";
514			reg = <0 0x10206000 0 0x1000>;
515			#address-cells = <1>;
516			#size-cells = <1>;
517			thermal_calibration: calib@528 {
518				reg = <0x528 0xc>;
519			};
520		};
521
522		apmixedsys: clock-controller@10209000 {
523			compatible = "mediatek,mt8173-apmixedsys";
524			reg = <0 0x10209000 0 0x1000>;
525			#clock-cells = <1>;
526		};
527
528		hdmi_phy: hdmi-phy@10209100 {
529			compatible = "mediatek,mt8173-hdmi-phy";
530			reg = <0 0x10209100 0 0x24>;
531			clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
532			clock-names = "pll_ref";
533			clock-output-names = "hdmitx_dig_cts";
534			mediatek,ibias = <0xa>;
535			mediatek,ibias_up = <0x1c>;
536			#clock-cells = <0>;
537			#phy-cells = <0>;
538			status = "disabled";
539		};
540
541		gce: mailbox@10212000 {
542			compatible = "mediatek,mt8173-gce";
543			reg = <0 0x10212000 0 0x1000>;
544			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
545			clocks = <&infracfg CLK_INFRA_GCE>;
546			clock-names = "gce";
547			#mbox-cells = <3>;
548		};
549
550		mipi_tx0: mipi-dphy@10215000 {
551			compatible = "mediatek,mt8173-mipi-tx";
552			reg = <0 0x10215000 0 0x1000>;
553			clocks = <&clk26m>;
554			clock-output-names = "mipi_tx0_pll";
555			#clock-cells = <0>;
556			#phy-cells = <0>;
557			status = "disabled";
558		};
559
560		mipi_tx1: mipi-dphy@10216000 {
561			compatible = "mediatek,mt8173-mipi-tx";
562			reg = <0 0x10216000 0 0x1000>;
563			clocks = <&clk26m>;
564			clock-output-names = "mipi_tx1_pll";
565			#clock-cells = <0>;
566			#phy-cells = <0>;
567			status = "disabled";
568		};
569
570		gic: interrupt-controller@10220000 {
571			compatible = "arm,gic-400";
572			#interrupt-cells = <3>;
573			interrupt-parent = <&gic>;
574			interrupt-controller;
575			reg = <0 0x10221000 0 0x1000>,
576			      <0 0x10222000 0 0x2000>,
577			      <0 0x10224000 0 0x2000>,
578			      <0 0x10226000 0 0x2000>;
579			interrupts = <GIC_PPI 9
580				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
581		};
582
583		auxadc: auxadc@11001000 {
584			compatible = "mediatek,mt8173-auxadc";
585			reg = <0 0x11001000 0 0x1000>;
586			clocks = <&pericfg CLK_PERI_AUXADC>;
587			clock-names = "main";
588			#io-channel-cells = <1>;
589		};
590
591		uart0: serial@11002000 {
592			compatible = "mediatek,mt8173-uart",
593				     "mediatek,mt6577-uart";
594			reg = <0 0x11002000 0 0x400>;
595			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
596			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
597			clock-names = "baud", "bus";
598			status = "disabled";
599		};
600
601		uart1: serial@11003000 {
602			compatible = "mediatek,mt8173-uart",
603				     "mediatek,mt6577-uart";
604			reg = <0 0x11003000 0 0x400>;
605			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
606			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
607			clock-names = "baud", "bus";
608			status = "disabled";
609		};
610
611		uart2: serial@11004000 {
612			compatible = "mediatek,mt8173-uart",
613				     "mediatek,mt6577-uart";
614			reg = <0 0x11004000 0 0x400>;
615			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
616			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
617			clock-names = "baud", "bus";
618			status = "disabled";
619		};
620
621		uart3: serial@11005000 {
622			compatible = "mediatek,mt8173-uart",
623				     "mediatek,mt6577-uart";
624			reg = <0 0x11005000 0 0x400>;
625			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
626			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
627			clock-names = "baud", "bus";
628			status = "disabled";
629		};
630
631		i2c0: i2c@11007000 {
632			compatible = "mediatek,mt8173-i2c";
633			reg = <0 0x11007000 0 0x70>,
634			      <0 0x11000100 0 0x80>;
635			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
636			clock-div = <16>;
637			clocks = <&pericfg CLK_PERI_I2C0>,
638				 <&pericfg CLK_PERI_AP_DMA>;
639			clock-names = "main", "dma";
640			pinctrl-names = "default";
641			pinctrl-0 = <&i2c0_pins_a>;
642			#address-cells = <1>;
643			#size-cells = <0>;
644			status = "disabled";
645		};
646
647		i2c1: i2c@11008000 {
648			compatible = "mediatek,mt8173-i2c";
649			reg = <0 0x11008000 0 0x70>,
650			      <0 0x11000180 0 0x80>;
651			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
652			clock-div = <16>;
653			clocks = <&pericfg CLK_PERI_I2C1>,
654				 <&pericfg CLK_PERI_AP_DMA>;
655			clock-names = "main", "dma";
656			pinctrl-names = "default";
657			pinctrl-0 = <&i2c1_pins_a>;
658			#address-cells = <1>;
659			#size-cells = <0>;
660			status = "disabled";
661		};
662
663		i2c2: i2c@11009000 {
664			compatible = "mediatek,mt8173-i2c";
665			reg = <0 0x11009000 0 0x70>,
666			      <0 0x11000200 0 0x80>;
667			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
668			clock-div = <16>;
669			clocks = <&pericfg CLK_PERI_I2C2>,
670				 <&pericfg CLK_PERI_AP_DMA>;
671			clock-names = "main", "dma";
672			pinctrl-names = "default";
673			pinctrl-0 = <&i2c2_pins_a>;
674			#address-cells = <1>;
675			#size-cells = <0>;
676			status = "disabled";
677		};
678
679		spi: spi@1100a000 {
680			compatible = "mediatek,mt8173-spi";
681			#address-cells = <1>;
682			#size-cells = <0>;
683			reg = <0 0x1100a000 0 0x1000>;
684			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
685			clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
686				 <&topckgen CLK_TOP_SPI_SEL>,
687				 <&pericfg CLK_PERI_SPI0>;
688			clock-names = "parent-clk", "sel-clk", "spi-clk";
689			status = "disabled";
690		};
691
692		thermal: thermal@1100b000 {
693			#thermal-sensor-cells = <0>;
694			compatible = "mediatek,mt8173-thermal";
695			reg = <0 0x1100b000 0 0x1000>;
696			interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
697			clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
698			clock-names = "therm", "auxadc";
699			resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
700			mediatek,auxadc = <&auxadc>;
701			mediatek,apmixedsys = <&apmixedsys>;
702			nvmem-cells = <&thermal_calibration>;
703			nvmem-cell-names = "calibration-data";
704		};
705
706		nor_flash: spi@1100d000 {
707			compatible = "mediatek,mt8173-nor";
708			reg = <0 0x1100d000 0 0xe0>;
709			clocks = <&pericfg CLK_PERI_SPI>,
710				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
711			clock-names = "spi", "sf";
712			#address-cells = <1>;
713			#size-cells = <0>;
714			status = "disabled";
715		};
716
717		i2c3: i2c@11010000 {
718			compatible = "mediatek,mt8173-i2c";
719			reg = <0 0x11010000 0 0x70>,
720			      <0 0x11000280 0 0x80>;
721			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
722			clock-div = <16>;
723			clocks = <&pericfg CLK_PERI_I2C3>,
724				 <&pericfg CLK_PERI_AP_DMA>;
725			clock-names = "main", "dma";
726			pinctrl-names = "default";
727			pinctrl-0 = <&i2c3_pins_a>;
728			#address-cells = <1>;
729			#size-cells = <0>;
730			status = "disabled";
731		};
732
733		i2c4: i2c@11011000 {
734			compatible = "mediatek,mt8173-i2c";
735			reg = <0 0x11011000 0 0x70>,
736			      <0 0x11000300 0 0x80>;
737			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
738			clock-div = <16>;
739			clocks = <&pericfg CLK_PERI_I2C4>,
740				 <&pericfg CLK_PERI_AP_DMA>;
741			clock-names = "main", "dma";
742			pinctrl-names = "default";
743			pinctrl-0 = <&i2c4_pins_a>;
744			#address-cells = <1>;
745			#size-cells = <0>;
746			status = "disabled";
747		};
748
749		hdmiddc0: i2c@11012000 {
750			compatible = "mediatek,mt8173-hdmi-ddc";
751			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
752			reg = <0 0x11012000 0 0x1C>;
753			clocks = <&pericfg CLK_PERI_I2C5>;
754			clock-names = "ddc-i2c";
755		};
756
757		i2c6: i2c@11013000 {
758			compatible = "mediatek,mt8173-i2c";
759			reg = <0 0x11013000 0 0x70>,
760			      <0 0x11000080 0 0x80>;
761			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
762			clock-div = <16>;
763			clocks = <&pericfg CLK_PERI_I2C6>,
764				 <&pericfg CLK_PERI_AP_DMA>;
765			clock-names = "main", "dma";
766			pinctrl-names = "default";
767			pinctrl-0 = <&i2c6_pins_a>;
768			#address-cells = <1>;
769			#size-cells = <0>;
770			status = "disabled";
771		};
772
773		afe: audio-controller@11220000  {
774			compatible = "mediatek,mt8173-afe-pcm";
775			reg = <0 0x11220000 0 0x1000>;
776			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
777			power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
778			clocks = <&infracfg CLK_INFRA_AUDIO>,
779				 <&topckgen CLK_TOP_AUDIO_SEL>,
780				 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
781				 <&topckgen CLK_TOP_APLL1_DIV0>,
782				 <&topckgen CLK_TOP_APLL2_DIV0>,
783				 <&topckgen CLK_TOP_I2S0_M_SEL>,
784				 <&topckgen CLK_TOP_I2S1_M_SEL>,
785				 <&topckgen CLK_TOP_I2S2_M_SEL>,
786				 <&topckgen CLK_TOP_I2S3_M_SEL>,
787				 <&topckgen CLK_TOP_I2S3_B_SEL>;
788			clock-names = "infra_sys_audio_clk",
789				      "top_pdn_audio",
790				      "top_pdn_aud_intbus",
791				      "bck0",
792				      "bck1",
793				      "i2s0_m",
794				      "i2s1_m",
795				      "i2s2_m",
796				      "i2s3_m",
797				      "i2s3_b";
798			assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
799					  <&topckgen CLK_TOP_AUD_2_SEL>;
800			assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
801						 <&topckgen CLK_TOP_APLL2>;
802		};
803
804		mmc0: mmc@11230000 {
805			compatible = "mediatek,mt8173-mmc";
806			reg = <0 0x11230000 0 0x1000>;
807			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
808			clocks = <&pericfg CLK_PERI_MSDC30_0>,
809				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
810			clock-names = "source", "hclk";
811			status = "disabled";
812		};
813
814		mmc1: mmc@11240000 {
815			compatible = "mediatek,mt8173-mmc";
816			reg = <0 0x11240000 0 0x1000>;
817			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
818			clocks = <&pericfg CLK_PERI_MSDC30_1>,
819				 <&topckgen CLK_TOP_AXI_SEL>;
820			clock-names = "source", "hclk";
821			status = "disabled";
822		};
823
824		mmc2: mmc@11250000 {
825			compatible = "mediatek,mt8173-mmc";
826			reg = <0 0x11250000 0 0x1000>;
827			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
828			clocks = <&pericfg CLK_PERI_MSDC30_2>,
829				 <&topckgen CLK_TOP_AXI_SEL>;
830			clock-names = "source", "hclk";
831			status = "disabled";
832		};
833
834		mmc3: mmc@11260000 {
835			compatible = "mediatek,mt8173-mmc";
836			reg = <0 0x11260000 0 0x1000>;
837			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
838			clocks = <&pericfg CLK_PERI_MSDC30_3>,
839				 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
840			clock-names = "source", "hclk";
841			status = "disabled";
842		};
843
844		ssusb: usb@11271000 {
845			compatible = "mediatek,mt8173-mtu3";
846			reg = <0 0x11271000 0 0x3000>,
847			      <0 0x11280700 0 0x0100>;
848			reg-names = "mac", "ippc";
849			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
850			phys = <&u2port0 PHY_TYPE_USB2>,
851			       <&u3port0 PHY_TYPE_USB3>,
852			       <&u2port1 PHY_TYPE_USB2>;
853			power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
854			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
855			clock-names = "sys_ck", "ref_ck";
856			mediatek,syscon-wakeup = <&pericfg 0x400 1>;
857			#address-cells = <2>;
858			#size-cells = <2>;
859			ranges;
860			status = "disabled";
861
862			usb_host: xhci@11270000 {
863				compatible = "mediatek,mt8173-xhci";
864				reg = <0 0x11270000 0 0x1000>;
865				reg-names = "mac";
866				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
867				power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
868				clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
869				clock-names = "sys_ck", "ref_ck";
870				status = "disabled";
871			};
872		};
873
874		u3phy: usb-phy@11290000 {
875			compatible = "mediatek,mt8173-u3phy";
876			reg = <0 0x11290000 0 0x800>;
877			#address-cells = <2>;
878			#size-cells = <2>;
879			ranges;
880			status = "okay";
881
882			u2port0: usb-phy@11290800 {
883				reg = <0 0x11290800 0 0x100>;
884				clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
885				clock-names = "ref";
886				#phy-cells = <1>;
887				status = "okay";
888			};
889
890			u3port0: usb-phy@11290900 {
891				reg = <0 0x11290900 0 0x700>;
892				clocks = <&clk26m>;
893				clock-names = "ref";
894				#phy-cells = <1>;
895				status = "okay";
896			};
897
898			u2port1: usb-phy@11291000 {
899				reg = <0 0x11291000 0 0x100>;
900				clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
901				clock-names = "ref";
902				#phy-cells = <1>;
903				status = "okay";
904			};
905		};
906
907		mmsys: clock-controller@14000000 {
908			compatible = "mediatek,mt8173-mmsys", "syscon";
909			reg = <0 0x14000000 0 0x1000>;
910			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
911			assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
912			assigned-clock-rates = <400000000>;
913			#clock-cells = <1>;
914		};
915
916		mdp_rdma0: rdma@14001000 {
917			compatible = "mediatek,mt8173-mdp-rdma",
918				     "mediatek,mt8173-mdp";
919			reg = <0 0x14001000 0 0x1000>;
920			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
921				 <&mmsys CLK_MM_MUTEX_32K>;
922			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
923			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
924			mediatek,larb = <&larb0>;
925			mediatek,vpu = <&vpu>;
926		};
927
928		mdp_rdma1: rdma@14002000 {
929			compatible = "mediatek,mt8173-mdp-rdma";
930			reg = <0 0x14002000 0 0x1000>;
931			clocks = <&mmsys CLK_MM_MDP_RDMA1>,
932				 <&mmsys CLK_MM_MUTEX_32K>;
933			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
934			iommus = <&iommu M4U_PORT_MDP_RDMA1>;
935			mediatek,larb = <&larb4>;
936		};
937
938		mdp_rsz0: rsz@14003000 {
939			compatible = "mediatek,mt8173-mdp-rsz";
940			reg = <0 0x14003000 0 0x1000>;
941			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
942			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
943		};
944
945		mdp_rsz1: rsz@14004000 {
946			compatible = "mediatek,mt8173-mdp-rsz";
947			reg = <0 0x14004000 0 0x1000>;
948			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
949			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
950		};
951
952		mdp_rsz2: rsz@14005000 {
953			compatible = "mediatek,mt8173-mdp-rsz";
954			reg = <0 0x14005000 0 0x1000>;
955			clocks = <&mmsys CLK_MM_MDP_RSZ2>;
956			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
957		};
958
959		mdp_wdma0: wdma@14006000 {
960			compatible = "mediatek,mt8173-mdp-wdma";
961			reg = <0 0x14006000 0 0x1000>;
962			clocks = <&mmsys CLK_MM_MDP_WDMA>;
963			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
964			iommus = <&iommu M4U_PORT_MDP_WDMA>;
965			mediatek,larb = <&larb0>;
966		};
967
968		mdp_wrot0: wrot@14007000 {
969			compatible = "mediatek,mt8173-mdp-wrot";
970			reg = <0 0x14007000 0 0x1000>;
971			clocks = <&mmsys CLK_MM_MDP_WROT0>;
972			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
973			iommus = <&iommu M4U_PORT_MDP_WROT0>;
974			mediatek,larb = <&larb0>;
975		};
976
977		mdp_wrot1: wrot@14008000 {
978			compatible = "mediatek,mt8173-mdp-wrot";
979			reg = <0 0x14008000 0 0x1000>;
980			clocks = <&mmsys CLK_MM_MDP_WROT1>;
981			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
982			iommus = <&iommu M4U_PORT_MDP_WROT1>;
983			mediatek,larb = <&larb4>;
984		};
985
986		ovl0: ovl@1400c000 {
987			compatible = "mediatek,mt8173-disp-ovl";
988			reg = <0 0x1400c000 0 0x1000>;
989			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
990			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
991			clocks = <&mmsys CLK_MM_DISP_OVL0>;
992			iommus = <&iommu M4U_PORT_DISP_OVL0>;
993			mediatek,larb = <&larb0>;
994		};
995
996		ovl1: ovl@1400d000 {
997			compatible = "mediatek,mt8173-disp-ovl";
998			reg = <0 0x1400d000 0 0x1000>;
999			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
1000			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1001			clocks = <&mmsys CLK_MM_DISP_OVL1>;
1002			iommus = <&iommu M4U_PORT_DISP_OVL1>;
1003			mediatek,larb = <&larb4>;
1004		};
1005
1006		rdma0: rdma@1400e000 {
1007			compatible = "mediatek,mt8173-disp-rdma";
1008			reg = <0 0x1400e000 0 0x1000>;
1009			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
1010			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1011			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1012			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1013			mediatek,larb = <&larb0>;
1014		};
1015
1016		rdma1: rdma@1400f000 {
1017			compatible = "mediatek,mt8173-disp-rdma";
1018			reg = <0 0x1400f000 0 0x1000>;
1019			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
1020			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1021			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1022			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1023			mediatek,larb = <&larb4>;
1024		};
1025
1026		rdma2: rdma@14010000 {
1027			compatible = "mediatek,mt8173-disp-rdma";
1028			reg = <0 0x14010000 0 0x1000>;
1029			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1030			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1031			clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1032			iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1033			mediatek,larb = <&larb4>;
1034		};
1035
1036		wdma0: wdma@14011000 {
1037			compatible = "mediatek,mt8173-disp-wdma";
1038			reg = <0 0x14011000 0 0x1000>;
1039			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1040			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1041			clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1042			iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1043			mediatek,larb = <&larb0>;
1044		};
1045
1046		wdma1: wdma@14012000 {
1047			compatible = "mediatek,mt8173-disp-wdma";
1048			reg = <0 0x14012000 0 0x1000>;
1049			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1050			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1051			clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1052			iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1053			mediatek,larb = <&larb4>;
1054		};
1055
1056		color0: color@14013000 {
1057			compatible = "mediatek,mt8173-disp-color";
1058			reg = <0 0x14013000 0 0x1000>;
1059			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1060			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1061			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1062		};
1063
1064		color1: color@14014000 {
1065			compatible = "mediatek,mt8173-disp-color";
1066			reg = <0 0x14014000 0 0x1000>;
1067			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1068			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1069			clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1070		};
1071
1072		aal@14015000 {
1073			compatible = "mediatek,mt8173-disp-aal";
1074			reg = <0 0x14015000 0 0x1000>;
1075			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1076			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1077			clocks = <&mmsys CLK_MM_DISP_AAL>;
1078		};
1079
1080		gamma@14016000 {
1081			compatible = "mediatek,mt8173-disp-gamma";
1082			reg = <0 0x14016000 0 0x1000>;
1083			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1084			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1085			clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1086		};
1087
1088		merge@14017000 {
1089			compatible = "mediatek,mt8173-disp-merge";
1090			reg = <0 0x14017000 0 0x1000>;
1091			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1092			clocks = <&mmsys CLK_MM_DISP_MERGE>;
1093		};
1094
1095		split0: split@14018000 {
1096			compatible = "mediatek,mt8173-disp-split";
1097			reg = <0 0x14018000 0 0x1000>;
1098			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1099			clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1100		};
1101
1102		split1: split@14019000 {
1103			compatible = "mediatek,mt8173-disp-split";
1104			reg = <0 0x14019000 0 0x1000>;
1105			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1106			clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1107		};
1108
1109		ufoe@1401a000 {
1110			compatible = "mediatek,mt8173-disp-ufoe";
1111			reg = <0 0x1401a000 0 0x1000>;
1112			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1113			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1114			clocks = <&mmsys CLK_MM_DISP_UFOE>;
1115		};
1116
1117		dsi0: dsi@1401b000 {
1118			compatible = "mediatek,mt8173-dsi";
1119			reg = <0 0x1401b000 0 0x1000>;
1120			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1121			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1122			clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1123				 <&mmsys CLK_MM_DSI0_DIGITAL>,
1124				 <&mipi_tx0>;
1125			clock-names = "engine", "digital", "hs";
1126			phys = <&mipi_tx0>;
1127			phy-names = "dphy";
1128			status = "disabled";
1129		};
1130
1131		dsi1: dsi@1401c000 {
1132			compatible = "mediatek,mt8173-dsi";
1133			reg = <0 0x1401c000 0 0x1000>;
1134			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1135			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1136			clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1137				 <&mmsys CLK_MM_DSI1_DIGITAL>,
1138				 <&mipi_tx1>;
1139			clock-names = "engine", "digital", "hs";
1140			phy = <&mipi_tx1>;
1141			phy-names = "dphy";
1142			status = "disabled";
1143		};
1144
1145		dpi0: dpi@1401d000 {
1146			compatible = "mediatek,mt8173-dpi";
1147			reg = <0 0x1401d000 0 0x1000>;
1148			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1149			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1150			clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1151				 <&mmsys CLK_MM_DPI_ENGINE>,
1152				 <&apmixedsys CLK_APMIXED_TVDPLL>;
1153			clock-names = "pixel", "engine", "pll";
1154			status = "disabled";
1155
1156			port {
1157				dpi0_out: endpoint {
1158					remote-endpoint = <&hdmi0_in>;
1159				};
1160			};
1161		};
1162
1163		pwm0: pwm@1401e000 {
1164			compatible = "mediatek,mt8173-disp-pwm",
1165				     "mediatek,mt6595-disp-pwm";
1166			reg = <0 0x1401e000 0 0x1000>;
1167			#pwm-cells = <2>;
1168			clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1169				 <&mmsys CLK_MM_DISP_PWM0MM>;
1170			clock-names = "main", "mm";
1171			status = "disabled";
1172		};
1173
1174		pwm1: pwm@1401f000 {
1175			compatible = "mediatek,mt8173-disp-pwm",
1176				     "mediatek,mt6595-disp-pwm";
1177			reg = <0 0x1401f000 0 0x1000>;
1178			#pwm-cells = <2>;
1179			clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1180				 <&mmsys CLK_MM_DISP_PWM1MM>;
1181			clock-names = "main", "mm";
1182			status = "disabled";
1183		};
1184
1185		mutex: mutex@14020000 {
1186			compatible = "mediatek,mt8173-disp-mutex";
1187			reg = <0 0x14020000 0 0x1000>;
1188			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1189			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1190			clocks = <&mmsys CLK_MM_MUTEX_32K>;
1191		};
1192
1193		larb0: larb@14021000 {
1194			compatible = "mediatek,mt8173-smi-larb";
1195			reg = <0 0x14021000 0 0x1000>;
1196			mediatek,smi = <&smi_common>;
1197			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1198			clocks = <&mmsys CLK_MM_SMI_LARB0>,
1199				 <&mmsys CLK_MM_SMI_LARB0>;
1200			clock-names = "apb", "smi";
1201		};
1202
1203		smi_common: smi@14022000 {
1204			compatible = "mediatek,mt8173-smi-common";
1205			reg = <0 0x14022000 0 0x1000>;
1206			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1207			clocks = <&mmsys CLK_MM_SMI_COMMON>,
1208				 <&mmsys CLK_MM_SMI_COMMON>;
1209			clock-names = "apb", "smi";
1210		};
1211
1212		od@14023000 {
1213			compatible = "mediatek,mt8173-disp-od";
1214			reg = <0 0x14023000 0 0x1000>;
1215			clocks = <&mmsys CLK_MM_DISP_OD>;
1216		};
1217
1218		hdmi0: hdmi@14025000 {
1219			compatible = "mediatek,mt8173-hdmi";
1220			reg = <0 0x14025000 0 0x400>;
1221			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1222			clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1223				 <&mmsys CLK_MM_HDMI_PLLCK>,
1224				 <&mmsys CLK_MM_HDMI_AUDIO>,
1225				 <&mmsys CLK_MM_HDMI_SPDIF>;
1226			clock-names = "pixel", "pll", "bclk", "spdif";
1227			pinctrl-names = "default";
1228			pinctrl-0 = <&hdmi_pin>;
1229			phys = <&hdmi_phy>;
1230			phy-names = "hdmi";
1231			mediatek,syscon-hdmi = <&mmsys 0x900>;
1232			assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1233			assigned-clock-parents = <&hdmi_phy>;
1234			status = "disabled";
1235
1236			ports {
1237				#address-cells = <1>;
1238				#size-cells = <0>;
1239
1240				port@0 {
1241					reg = <0>;
1242
1243					hdmi0_in: endpoint {
1244						remote-endpoint = <&dpi0_out>;
1245					};
1246				};
1247			};
1248		};
1249
1250		larb4: larb@14027000 {
1251			compatible = "mediatek,mt8173-smi-larb";
1252			reg = <0 0x14027000 0 0x1000>;
1253			mediatek,smi = <&smi_common>;
1254			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1255			clocks = <&mmsys CLK_MM_SMI_LARB4>,
1256				 <&mmsys CLK_MM_SMI_LARB4>;
1257			clock-names = "apb", "smi";
1258		};
1259
1260		imgsys: clock-controller@15000000 {
1261			compatible = "mediatek,mt8173-imgsys", "syscon";
1262			reg = <0 0x15000000 0 0x1000>;
1263			#clock-cells = <1>;
1264		};
1265
1266		larb2: larb@15001000 {
1267			compatible = "mediatek,mt8173-smi-larb";
1268			reg = <0 0x15001000 0 0x1000>;
1269			mediatek,smi = <&smi_common>;
1270			power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1271			clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1272				 <&imgsys CLK_IMG_LARB2_SMI>;
1273			clock-names = "apb", "smi";
1274		};
1275
1276		vdecsys: clock-controller@16000000 {
1277			compatible = "mediatek,mt8173-vdecsys", "syscon";
1278			reg = <0 0x16000000 0 0x1000>;
1279			#clock-cells = <1>;
1280		};
1281
1282		vcodec_dec: vcodec@16000000 {
1283			compatible = "mediatek,mt8173-vcodec-dec";
1284			reg = <0 0x16000000 0 0x100>,	/* VDEC_SYS */
1285			      <0 0x16020000 0 0x1000>,	/* VDEC_MISC */
1286			      <0 0x16021000 0 0x800>,	/* VDEC_LD */
1287			      <0 0x16021800 0 0x800>,	/* VDEC_TOP */
1288			      <0 0x16022000 0 0x1000>,	/* VDEC_CM */
1289			      <0 0x16023000 0 0x1000>,	/* VDEC_AD */
1290			      <0 0x16024000 0 0x1000>,	/* VDEC_AV */
1291			      <0 0x16025000 0 0x1000>,	/* VDEC_PP */
1292			      <0 0x16026800 0 0x800>,	/* VDEC_HWD */
1293			      <0 0x16027000 0 0x800>,	/* VDEC_HWQ */
1294			      <0 0x16027800 0 0x800>,	/* VDEC_HWB */
1295			      <0 0x16028400 0 0x400>;	/* VDEC_HWG */
1296			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1297			mediatek,larb = <&larb1>;
1298			iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1299				 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1300				 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1301				 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1302				 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1303				 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1304				 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1305				 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1306			mediatek,vpu = <&vpu>;
1307			power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1308			clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1309				 <&topckgen CLK_TOP_UNIVPLL_D2>,
1310				 <&topckgen CLK_TOP_CCI400_SEL>,
1311				 <&topckgen CLK_TOP_VDEC_SEL>,
1312				 <&topckgen CLK_TOP_VCODECPLL>,
1313				 <&apmixedsys CLK_APMIXED_VENCPLL>,
1314				 <&topckgen CLK_TOP_VENC_LT_SEL>,
1315				 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1316			clock-names = "vcodecpll",
1317				      "univpll_d2",
1318				      "clk_cci400_sel",
1319				      "vdec_sel",
1320				      "vdecpll",
1321				      "vencpll",
1322				      "venc_lt_sel",
1323				      "vdec_bus_clk_src";
1324			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1325					  <&topckgen CLK_TOP_CCI400_SEL>,
1326					  <&topckgen CLK_TOP_VDEC_SEL>,
1327					  <&apmixedsys CLK_APMIXED_VCODECPLL>,
1328					  <&apmixedsys CLK_APMIXED_VENCPLL>;
1329			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1330						 <&topckgen CLK_TOP_UNIVPLL_D2>,
1331						 <&topckgen CLK_TOP_VCODECPLL>;
1332			assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1333		};
1334
1335		larb1: larb@16010000 {
1336			compatible = "mediatek,mt8173-smi-larb";
1337			reg = <0 0x16010000 0 0x1000>;
1338			mediatek,smi = <&smi_common>;
1339			power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1340			clocks = <&vdecsys CLK_VDEC_CKEN>,
1341				 <&vdecsys CLK_VDEC_LARB_CKEN>;
1342			clock-names = "apb", "smi";
1343		};
1344
1345		vencsys: clock-controller@18000000 {
1346			compatible = "mediatek,mt8173-vencsys", "syscon";
1347			reg = <0 0x18000000 0 0x1000>;
1348			#clock-cells = <1>;
1349		};
1350
1351		larb3: larb@18001000 {
1352			compatible = "mediatek,mt8173-smi-larb";
1353			reg = <0 0x18001000 0 0x1000>;
1354			mediatek,smi = <&smi_common>;
1355			power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1356			clocks = <&vencsys CLK_VENC_CKE1>,
1357				 <&vencsys CLK_VENC_CKE0>;
1358			clock-names = "apb", "smi";
1359		};
1360
1361		vcodec_enc: vcodec@18002000 {
1362			compatible = "mediatek,mt8173-vcodec-enc";
1363			reg = <0 0x18002000 0 0x1000>,	/* VENC_SYS */
1364			      <0 0x19002000 0 0x1000>;	/* VENC_LT_SYS */
1365			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1366				     <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1367			mediatek,larb = <&larb3>,
1368					<&larb5>;
1369			iommus = <&iommu M4U_PORT_VENC_RCPU>,
1370				 <&iommu M4U_PORT_VENC_REC>,
1371				 <&iommu M4U_PORT_VENC_BSDMA>,
1372				 <&iommu M4U_PORT_VENC_SV_COMV>,
1373				 <&iommu M4U_PORT_VENC_RD_COMV>,
1374				 <&iommu M4U_PORT_VENC_CUR_LUMA>,
1375				 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1376				 <&iommu M4U_PORT_VENC_REF_LUMA>,
1377				 <&iommu M4U_PORT_VENC_REF_CHROMA>,
1378				 <&iommu M4U_PORT_VENC_NBM_RDMA>,
1379				 <&iommu M4U_PORT_VENC_NBM_WDMA>,
1380				 <&iommu M4U_PORT_VENC_RCPU_SET2>,
1381				 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1382				 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1383				 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1384				 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1385				 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1386				 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1387				 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1388				 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1389			mediatek,vpu = <&vpu>;
1390			clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1391				 <&topckgen CLK_TOP_VENC_SEL>,
1392				 <&topckgen CLK_TOP_UNIVPLL1_D2>,
1393				 <&topckgen CLK_TOP_VENC_LT_SEL>;
1394			clock-names = "venc_sel_src",
1395				      "venc_sel",
1396				      "venc_lt_sel_src",
1397				      "venc_lt_sel";
1398			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
1399					  <&topckgen CLK_TOP_VENC_LT_SEL>;
1400			assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
1401						 <&topckgen CLK_TOP_UNIVPLL1_D2>;
1402		};
1403
1404		vencltsys: clock-controller@19000000 {
1405			compatible = "mediatek,mt8173-vencltsys", "syscon";
1406			reg = <0 0x19000000 0 0x1000>;
1407			#clock-cells = <1>;
1408		};
1409
1410		larb5: larb@19001000 {
1411			compatible = "mediatek,mt8173-smi-larb";
1412			reg = <0 0x19001000 0 0x1000>;
1413			mediatek,smi = <&smi_common>;
1414			power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1415			clocks = <&vencltsys CLK_VENCLT_CKE1>,
1416				 <&vencltsys CLK_VENCLT_CKE0>;
1417			clock-names = "apb", "smi";
1418		};
1419	};
1420};
1421
1422