1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Eddie Huang <eddie.huang@mediatek.com>
5 */
6
7#include <dt-bindings/clock/mt8173-clk.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/memory/mt8173-larb-port.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/power/mt8173-power.h>
13#include <dt-bindings/reset/mt8173-resets.h>
14#include <dt-bindings/gce/mt8173-gce.h>
15#include <dt-bindings/thermal/thermal.h>
16#include "mt8173-pinfunc.h"
17
18/ {
19	compatible = "mediatek,mt8173";
20	interrupt-parent = <&sysirq>;
21	#address-cells = <2>;
22	#size-cells = <2>;
23
24	aliases {
25		ovl0 = &ovl0;
26		ovl1 = &ovl1;
27		rdma0 = &rdma0;
28		rdma1 = &rdma1;
29		rdma2 = &rdma2;
30		wdma0 = &wdma0;
31		wdma1 = &wdma1;
32		color0 = &color0;
33		color1 = &color1;
34		split0 = &split0;
35		split1 = &split1;
36		dpi0 = &dpi0;
37		dsi0 = &dsi0;
38		dsi1 = &dsi1;
39		mdp-rdma0 = &mdp_rdma0;
40		mdp-rdma1 = &mdp_rdma1;
41		mdp-rsz0 = &mdp_rsz0;
42		mdp-rsz1 = &mdp_rsz1;
43		mdp-rsz2 = &mdp_rsz2;
44		mdp-wdma0 = &mdp_wdma0;
45		mdp-wrot0 = &mdp_wrot0;
46		mdp-wrot1 = &mdp_wrot1;
47		serial0 = &uart0;
48		serial1 = &uart1;
49		serial2 = &uart2;
50		serial3 = &uart3;
51	};
52
53	cluster0_opp: opp-table-0 {
54		compatible = "operating-points-v2";
55		opp-shared;
56		opp-507000000 {
57			opp-hz = /bits/ 64 <507000000>;
58			opp-microvolt = <859000>;
59		};
60		opp-702000000 {
61			opp-hz = /bits/ 64 <702000000>;
62			opp-microvolt = <908000>;
63		};
64		opp-1001000000 {
65			opp-hz = /bits/ 64 <1001000000>;
66			opp-microvolt = <983000>;
67		};
68		opp-1105000000 {
69			opp-hz = /bits/ 64 <1105000000>;
70			opp-microvolt = <1009000>;
71		};
72		opp-1209000000 {
73			opp-hz = /bits/ 64 <1209000000>;
74			opp-microvolt = <1034000>;
75		};
76		opp-1300000000 {
77			opp-hz = /bits/ 64 <1300000000>;
78			opp-microvolt = <1057000>;
79		};
80		opp-1508000000 {
81			opp-hz = /bits/ 64 <1508000000>;
82			opp-microvolt = <1109000>;
83		};
84		opp-1703000000 {
85			opp-hz = /bits/ 64 <1703000000>;
86			opp-microvolt = <1125000>;
87		};
88	};
89
90	cluster1_opp: opp-table-1 {
91		compatible = "operating-points-v2";
92		opp-shared;
93		opp-507000000 {
94			opp-hz = /bits/ 64 <507000000>;
95			opp-microvolt = <828000>;
96		};
97		opp-702000000 {
98			opp-hz = /bits/ 64 <702000000>;
99			opp-microvolt = <867000>;
100		};
101		opp-1001000000 {
102			opp-hz = /bits/ 64 <1001000000>;
103			opp-microvolt = <927000>;
104		};
105		opp-1209000000 {
106			opp-hz = /bits/ 64 <1209000000>;
107			opp-microvolt = <968000>;
108		};
109		opp-1404000000 {
110			opp-hz = /bits/ 64 <1404000000>;
111			opp-microvolt = <1007000>;
112		};
113		opp-1612000000 {
114			opp-hz = /bits/ 64 <1612000000>;
115			opp-microvolt = <1049000>;
116		};
117		opp-1807000000 {
118			opp-hz = /bits/ 64 <1807000000>;
119			opp-microvolt = <1089000>;
120		};
121		opp-2106000000 {
122			opp-hz = /bits/ 64 <2106000000>;
123			opp-microvolt = <1125000>;
124		};
125	};
126
127	cpus {
128		#address-cells = <1>;
129		#size-cells = <0>;
130
131		cpu-map {
132			cluster0 {
133				core0 {
134					cpu = <&cpu0>;
135				};
136				core1 {
137					cpu = <&cpu1>;
138				};
139			};
140
141			cluster1 {
142				core0 {
143					cpu = <&cpu2>;
144				};
145				core1 {
146					cpu = <&cpu3>;
147				};
148			};
149		};
150
151		cpu0: cpu@0 {
152			device_type = "cpu";
153			compatible = "arm,cortex-a53";
154			reg = <0x000>;
155			enable-method = "psci";
156			cpu-idle-states = <&CPU_SLEEP_0>;
157			#cooling-cells = <2>;
158			dynamic-power-coefficient = <263>;
159			clocks = <&infracfg CLK_INFRA_CA53SEL>,
160				 <&apmixedsys CLK_APMIXED_MAINPLL>;
161			clock-names = "cpu", "intermediate";
162			operating-points-v2 = <&cluster0_opp>;
163			capacity-dmips-mhz = <740>;
164		};
165
166		cpu1: cpu@1 {
167			device_type = "cpu";
168			compatible = "arm,cortex-a53";
169			reg = <0x001>;
170			enable-method = "psci";
171			cpu-idle-states = <&CPU_SLEEP_0>;
172			#cooling-cells = <2>;
173			dynamic-power-coefficient = <263>;
174			clocks = <&infracfg CLK_INFRA_CA53SEL>,
175				 <&apmixedsys CLK_APMIXED_MAINPLL>;
176			clock-names = "cpu", "intermediate";
177			operating-points-v2 = <&cluster0_opp>;
178			capacity-dmips-mhz = <740>;
179		};
180
181		cpu2: cpu@100 {
182			device_type = "cpu";
183			compatible = "arm,cortex-a72";
184			reg = <0x100>;
185			enable-method = "psci";
186			cpu-idle-states = <&CPU_SLEEP_0>;
187			#cooling-cells = <2>;
188			dynamic-power-coefficient = <530>;
189			clocks = <&infracfg CLK_INFRA_CA72SEL>,
190				 <&apmixedsys CLK_APMIXED_MAINPLL>;
191			clock-names = "cpu", "intermediate";
192			operating-points-v2 = <&cluster1_opp>;
193			capacity-dmips-mhz = <1024>;
194		};
195
196		cpu3: cpu@101 {
197			device_type = "cpu";
198			compatible = "arm,cortex-a72";
199			reg = <0x101>;
200			enable-method = "psci";
201			cpu-idle-states = <&CPU_SLEEP_0>;
202			#cooling-cells = <2>;
203			dynamic-power-coefficient = <530>;
204			clocks = <&infracfg CLK_INFRA_CA72SEL>,
205				 <&apmixedsys CLK_APMIXED_MAINPLL>;
206			clock-names = "cpu", "intermediate";
207			operating-points-v2 = <&cluster1_opp>;
208			capacity-dmips-mhz = <1024>;
209		};
210
211		idle-states {
212			entry-method = "psci";
213
214			CPU_SLEEP_0: cpu-sleep-0 {
215				compatible = "arm,idle-state";
216				local-timer-stop;
217				entry-latency-us = <639>;
218				exit-latency-us = <680>;
219				min-residency-us = <1088>;
220				arm,psci-suspend-param = <0x0010000>;
221			};
222		};
223	};
224
225	pmu_a53 {
226		compatible = "arm,cortex-a53-pmu";
227		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
228			     <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
229		interrupt-affinity = <&cpu0>, <&cpu1>;
230	};
231
232	pmu_a72 {
233		compatible = "arm,cortex-a72-pmu";
234		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
235			     <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
236		interrupt-affinity = <&cpu2>, <&cpu3>;
237	};
238
239	psci {
240		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
241		method = "smc";
242		cpu_suspend = <0x84000001>;
243		cpu_off	 = <0x84000002>;
244		cpu_on	 = <0x84000003>;
245	};
246
247	clk26m: oscillator0 {
248		compatible = "fixed-clock";
249		#clock-cells = <0>;
250		clock-frequency = <26000000>;
251		clock-output-names = "clk26m";
252	};
253
254	clk32k: oscillator1 {
255		compatible = "fixed-clock";
256		#clock-cells = <0>;
257		clock-frequency = <32000>;
258		clock-output-names = "clk32k";
259	};
260
261	cpum_ck: oscillator2 {
262		compatible = "fixed-clock";
263		#clock-cells = <0>;
264		clock-frequency = <0>;
265		clock-output-names = "cpum_ck";
266	};
267
268	thermal-zones {
269		cpu_thermal: cpu-thermal {
270			polling-delay-passive = <1000>; /* milliseconds */
271			polling-delay = <1000>; /* milliseconds */
272
273			thermal-sensors = <&thermal>;
274			sustainable-power = <1500>; /* milliwatts */
275
276			trips {
277				threshold: trip-point0 {
278					temperature = <68000>;
279					hysteresis = <2000>;
280					type = "passive";
281				};
282
283				target: trip-point1 {
284					temperature = <85000>;
285					hysteresis = <2000>;
286					type = "passive";
287				};
288
289				cpu_crit: cpu_crit0 {
290					temperature = <115000>;
291					hysteresis = <2000>;
292					type = "critical";
293				};
294			};
295
296			cooling-maps {
297				map0 {
298					trip = <&target>;
299					cooling-device = <&cpu0 THERMAL_NO_LIMIT
300							  THERMAL_NO_LIMIT>,
301							 <&cpu1 THERMAL_NO_LIMIT
302							  THERMAL_NO_LIMIT>;
303					contribution = <3072>;
304				};
305				map1 {
306					trip = <&target>;
307					cooling-device = <&cpu2 THERMAL_NO_LIMIT
308							  THERMAL_NO_LIMIT>,
309							 <&cpu3 THERMAL_NO_LIMIT
310							  THERMAL_NO_LIMIT>;
311					contribution = <1024>;
312				};
313			};
314		};
315	};
316
317	reserved-memory {
318		#address-cells = <2>;
319		#size-cells = <2>;
320		ranges;
321		vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
322			compatible = "shared-dma-pool";
323			reg = <0 0xb7000000 0 0x500000>;
324			alignment = <0x1000>;
325			no-map;
326		};
327	};
328
329	timer {
330		compatible = "arm,armv8-timer";
331		interrupt-parent = <&gic>;
332		interrupts = <GIC_PPI 13
333			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
334			     <GIC_PPI 14
335			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
336			     <GIC_PPI 11
337			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
338			     <GIC_PPI 10
339			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
340		arm,no-tick-in-suspend;
341	};
342
343	soc {
344		#address-cells = <2>;
345		#size-cells = <2>;
346		compatible = "simple-bus";
347		ranges;
348
349		topckgen: clock-controller@10000000 {
350			compatible = "mediatek,mt8173-topckgen";
351			reg = <0 0x10000000 0 0x1000>;
352			#clock-cells = <1>;
353		};
354
355		infracfg: power-controller@10001000 {
356			compatible = "mediatek,mt8173-infracfg", "syscon";
357			reg = <0 0x10001000 0 0x1000>;
358			#clock-cells = <1>;
359			#reset-cells = <1>;
360		};
361
362		pericfg: power-controller@10003000 {
363			compatible = "mediatek,mt8173-pericfg", "syscon";
364			reg = <0 0x10003000 0 0x1000>;
365			#clock-cells = <1>;
366			#reset-cells = <1>;
367		};
368
369		syscfg_pctl_a: syscfg_pctl_a@10005000 {
370			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
371			reg = <0 0x10005000 0 0x1000>;
372		};
373
374		pio: pinctrl@1000b000 {
375			compatible = "mediatek,mt8173-pinctrl";
376			reg = <0 0x1000b000 0 0x1000>;
377			mediatek,pctl-regmap = <&syscfg_pctl_a>;
378			pins-are-numbered;
379			gpio-controller;
380			#gpio-cells = <2>;
381			interrupt-controller;
382			#interrupt-cells = <2>;
383			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
384				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
385				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
386
387			hdmi_pin: xxx {
388
389				/*hdmi htplg pin*/
390				pins1 {
391					pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
392					input-enable;
393					bias-pull-down;
394				};
395			};
396
397			i2c0_pins_a: i2c0 {
398				pins1 {
399					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
400						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
401					bias-disable;
402				};
403			};
404
405			i2c1_pins_a: i2c1 {
406				pins1 {
407					pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
408						 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
409					bias-disable;
410				};
411			};
412
413			i2c2_pins_a: i2c2 {
414				pins1 {
415					pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
416						 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
417					bias-disable;
418				};
419			};
420
421			i2c3_pins_a: i2c3 {
422				pins1 {
423					pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
424						 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
425					bias-disable;
426				};
427			};
428
429			i2c4_pins_a: i2c4 {
430				pins1 {
431					pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
432						 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
433					bias-disable;
434				};
435			};
436
437			i2c6_pins_a: i2c6 {
438				pins1 {
439					pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
440						 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
441					bias-disable;
442				};
443			};
444		};
445
446		scpsys: syscon@10006000 {
447			compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
448			reg = <0 0x10006000 0 0x1000>;
449
450			/* System Power Manager */
451			spm: power-controller {
452				compatible = "mediatek,mt8173-power-controller";
453				#address-cells = <1>;
454				#size-cells = <0>;
455				#power-domain-cells = <1>;
456
457				/* power domains of the SoC */
458				power-domain@MT8173_POWER_DOMAIN_VDEC {
459					reg = <MT8173_POWER_DOMAIN_VDEC>;
460					clocks = <&topckgen CLK_TOP_MM_SEL>;
461					clock-names = "mm";
462					#power-domain-cells = <0>;
463				};
464				power-domain@MT8173_POWER_DOMAIN_VENC {
465					reg = <MT8173_POWER_DOMAIN_VENC>;
466					clocks = <&topckgen CLK_TOP_MM_SEL>,
467						 <&topckgen CLK_TOP_VENC_SEL>;
468					clock-names = "mm", "venc";
469					#power-domain-cells = <0>;
470				};
471				power-domain@MT8173_POWER_DOMAIN_ISP {
472					reg = <MT8173_POWER_DOMAIN_ISP>;
473					clocks = <&topckgen CLK_TOP_MM_SEL>;
474					clock-names = "mm";
475					#power-domain-cells = <0>;
476				};
477				power-domain@MT8173_POWER_DOMAIN_MM {
478					reg = <MT8173_POWER_DOMAIN_MM>;
479					clocks = <&topckgen CLK_TOP_MM_SEL>;
480					clock-names = "mm";
481					#power-domain-cells = <0>;
482					mediatek,infracfg = <&infracfg>;
483				};
484				power-domain@MT8173_POWER_DOMAIN_VENC_LT {
485					reg = <MT8173_POWER_DOMAIN_VENC_LT>;
486					clocks = <&topckgen CLK_TOP_MM_SEL>,
487						 <&topckgen CLK_TOP_VENC_LT_SEL>;
488					clock-names = "mm", "venclt";
489					#power-domain-cells = <0>;
490				};
491				power-domain@MT8173_POWER_DOMAIN_AUDIO {
492					reg = <MT8173_POWER_DOMAIN_AUDIO>;
493					#power-domain-cells = <0>;
494				};
495				power-domain@MT8173_POWER_DOMAIN_USB {
496					reg = <MT8173_POWER_DOMAIN_USB>;
497					#power-domain-cells = <0>;
498				};
499				mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
500					reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
501					clocks = <&clk26m>;
502					clock-names = "mfg";
503					#address-cells = <1>;
504					#size-cells = <0>;
505					#power-domain-cells = <1>;
506
507					power-domain@MT8173_POWER_DOMAIN_MFG_2D {
508						reg = <MT8173_POWER_DOMAIN_MFG_2D>;
509						#address-cells = <1>;
510						#size-cells = <0>;
511						#power-domain-cells = <1>;
512
513						power-domain@MT8173_POWER_DOMAIN_MFG {
514							reg = <MT8173_POWER_DOMAIN_MFG>;
515							#power-domain-cells = <0>;
516							mediatek,infracfg = <&infracfg>;
517						};
518					};
519				};
520			};
521		};
522
523		watchdog: watchdog@10007000 {
524			compatible = "mediatek,mt8173-wdt",
525				     "mediatek,mt6589-wdt";
526			reg = <0 0x10007000 0 0x100>;
527		};
528
529		timer: timer@10008000 {
530			compatible = "mediatek,mt8173-timer",
531				     "mediatek,mt6577-timer";
532			reg = <0 0x10008000 0 0x1000>;
533			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
534			clocks = <&infracfg CLK_INFRA_CLK_13M>,
535				 <&topckgen CLK_TOP_RTC_SEL>;
536		};
537
538		pwrap: pwrap@1000d000 {
539			compatible = "mediatek,mt8173-pwrap";
540			reg = <0 0x1000d000 0 0x1000>;
541			reg-names = "pwrap";
542			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
543			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
544			reset-names = "pwrap";
545			clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
546			clock-names = "spi", "wrap";
547		};
548
549		cec: cec@10013000 {
550			compatible = "mediatek,mt8173-cec";
551			reg = <0 0x10013000 0 0xbc>;
552			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
553			clocks = <&infracfg CLK_INFRA_CEC>;
554			status = "disabled";
555		};
556
557		vpu: vpu@10020000 {
558			compatible = "mediatek,mt8173-vpu";
559			reg = <0 0x10020000 0 0x30000>,
560			      <0 0x10050000 0 0x100>;
561			reg-names = "tcm", "cfg_reg";
562			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
563			clocks = <&topckgen CLK_TOP_SCP_SEL>;
564			clock-names = "main";
565			memory-region = <&vpu_dma_reserved>;
566		};
567
568		sysirq: intpol-controller@10200620 {
569			compatible = "mediatek,mt8173-sysirq",
570				     "mediatek,mt6577-sysirq";
571			interrupt-controller;
572			#interrupt-cells = <3>;
573			interrupt-parent = <&gic>;
574			reg = <0 0x10200620 0 0x20>;
575		};
576
577		iommu: iommu@10205000 {
578			compatible = "mediatek,mt8173-m4u";
579			reg = <0 0x10205000 0 0x1000>;
580			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
581			clocks = <&infracfg CLK_INFRA_M4U>;
582			clock-names = "bclk";
583			mediatek,infracfg = <&infracfg>;
584			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
585					 <&larb3>, <&larb4>, <&larb5>;
586			#iommu-cells = <1>;
587		};
588
589		efuse: efuse@10206000 {
590			compatible = "mediatek,mt8173-efuse";
591			reg = <0 0x10206000 0 0x1000>;
592			#address-cells = <1>;
593			#size-cells = <1>;
594			thermal_calibration: calib@528 {
595				reg = <0x528 0xc>;
596			};
597		};
598
599		apmixedsys: clock-controller@10209000 {
600			compatible = "mediatek,mt8173-apmixedsys";
601			reg = <0 0x10209000 0 0x1000>;
602			#clock-cells = <1>;
603		};
604
605		hdmi_phy: hdmi-phy@10209100 {
606			compatible = "mediatek,mt8173-hdmi-phy";
607			reg = <0 0x10209100 0 0x24>;
608			clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
609			clock-names = "pll_ref";
610			clock-output-names = "hdmitx_dig_cts";
611			mediatek,ibias = <0xa>;
612			mediatek,ibias_up = <0x1c>;
613			#clock-cells = <0>;
614			#phy-cells = <0>;
615			status = "disabled";
616		};
617
618		gce: mailbox@10212000 {
619			compatible = "mediatek,mt8173-gce";
620			reg = <0 0x10212000 0 0x1000>;
621			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
622			clocks = <&infracfg CLK_INFRA_GCE>;
623			clock-names = "gce";
624			#mbox-cells = <2>;
625		};
626
627		mipi_tx0: dsi-phy@10215000 {
628			compatible = "mediatek,mt8173-mipi-tx";
629			reg = <0 0x10215000 0 0x1000>;
630			clocks = <&clk26m>;
631			clock-output-names = "mipi_tx0_pll";
632			#clock-cells = <0>;
633			#phy-cells = <0>;
634			status = "disabled";
635		};
636
637		mipi_tx1: dsi-phy@10216000 {
638			compatible = "mediatek,mt8173-mipi-tx";
639			reg = <0 0x10216000 0 0x1000>;
640			clocks = <&clk26m>;
641			clock-output-names = "mipi_tx1_pll";
642			#clock-cells = <0>;
643			#phy-cells = <0>;
644			status = "disabled";
645		};
646
647		gic: interrupt-controller@10221000 {
648			compatible = "arm,gic-400";
649			#interrupt-cells = <3>;
650			interrupt-parent = <&gic>;
651			interrupt-controller;
652			reg = <0 0x10221000 0 0x1000>,
653			      <0 0x10222000 0 0x2000>,
654			      <0 0x10224000 0 0x2000>,
655			      <0 0x10226000 0 0x2000>;
656			interrupts = <GIC_PPI 9
657				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
658		};
659
660		auxadc: auxadc@11001000 {
661			compatible = "mediatek,mt8173-auxadc";
662			reg = <0 0x11001000 0 0x1000>;
663			clocks = <&pericfg CLK_PERI_AUXADC>;
664			clock-names = "main";
665			#io-channel-cells = <1>;
666		};
667
668		uart0: serial@11002000 {
669			compatible = "mediatek,mt8173-uart",
670				     "mediatek,mt6577-uart";
671			reg = <0 0x11002000 0 0x400>;
672			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
673			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
674			clock-names = "baud", "bus";
675			status = "disabled";
676		};
677
678		uart1: serial@11003000 {
679			compatible = "mediatek,mt8173-uart",
680				     "mediatek,mt6577-uart";
681			reg = <0 0x11003000 0 0x400>;
682			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
683			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
684			clock-names = "baud", "bus";
685			status = "disabled";
686		};
687
688		uart2: serial@11004000 {
689			compatible = "mediatek,mt8173-uart",
690				     "mediatek,mt6577-uart";
691			reg = <0 0x11004000 0 0x400>;
692			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
693			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
694			clock-names = "baud", "bus";
695			status = "disabled";
696		};
697
698		uart3: serial@11005000 {
699			compatible = "mediatek,mt8173-uart",
700				     "mediatek,mt6577-uart";
701			reg = <0 0x11005000 0 0x400>;
702			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
703			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
704			clock-names = "baud", "bus";
705			status = "disabled";
706		};
707
708		i2c0: i2c@11007000 {
709			compatible = "mediatek,mt8173-i2c";
710			reg = <0 0x11007000 0 0x70>,
711			      <0 0x11000100 0 0x80>;
712			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
713			clock-div = <16>;
714			clocks = <&pericfg CLK_PERI_I2C0>,
715				 <&pericfg CLK_PERI_AP_DMA>;
716			clock-names = "main", "dma";
717			pinctrl-names = "default";
718			pinctrl-0 = <&i2c0_pins_a>;
719			#address-cells = <1>;
720			#size-cells = <0>;
721			status = "disabled";
722		};
723
724		i2c1: i2c@11008000 {
725			compatible = "mediatek,mt8173-i2c";
726			reg = <0 0x11008000 0 0x70>,
727			      <0 0x11000180 0 0x80>;
728			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
729			clock-div = <16>;
730			clocks = <&pericfg CLK_PERI_I2C1>,
731				 <&pericfg CLK_PERI_AP_DMA>;
732			clock-names = "main", "dma";
733			pinctrl-names = "default";
734			pinctrl-0 = <&i2c1_pins_a>;
735			#address-cells = <1>;
736			#size-cells = <0>;
737			status = "disabled";
738		};
739
740		i2c2: i2c@11009000 {
741			compatible = "mediatek,mt8173-i2c";
742			reg = <0 0x11009000 0 0x70>,
743			      <0 0x11000200 0 0x80>;
744			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
745			clock-div = <16>;
746			clocks = <&pericfg CLK_PERI_I2C2>,
747				 <&pericfg CLK_PERI_AP_DMA>;
748			clock-names = "main", "dma";
749			pinctrl-names = "default";
750			pinctrl-0 = <&i2c2_pins_a>;
751			#address-cells = <1>;
752			#size-cells = <0>;
753			status = "disabled";
754		};
755
756		spi: spi@1100a000 {
757			compatible = "mediatek,mt8173-spi";
758			#address-cells = <1>;
759			#size-cells = <0>;
760			reg = <0 0x1100a000 0 0x1000>;
761			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
762			clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
763				 <&topckgen CLK_TOP_SPI_SEL>,
764				 <&pericfg CLK_PERI_SPI0>;
765			clock-names = "parent-clk", "sel-clk", "spi-clk";
766			status = "disabled";
767		};
768
769		thermal: thermal@1100b000 {
770			#thermal-sensor-cells = <0>;
771			compatible = "mediatek,mt8173-thermal";
772			reg = <0 0x1100b000 0 0x1000>;
773			interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
774			clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
775			clock-names = "therm", "auxadc";
776			resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
777			mediatek,auxadc = <&auxadc>;
778			mediatek,apmixedsys = <&apmixedsys>;
779			nvmem-cells = <&thermal_calibration>;
780			nvmem-cell-names = "calibration-data";
781		};
782
783		nor_flash: spi@1100d000 {
784			compatible = "mediatek,mt8173-nor";
785			reg = <0 0x1100d000 0 0xe0>;
786			assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
787			assigned-clock-parents = <&clk26m>;
788			clocks = <&pericfg CLK_PERI_SPI>,
789				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
790				 <&pericfg CLK_PERI_NFI>;
791			clock-names = "spi", "sf", "axi";
792			#address-cells = <1>;
793			#size-cells = <0>;
794			status = "disabled";
795		};
796
797		i2c3: i2c@11010000 {
798			compatible = "mediatek,mt8173-i2c";
799			reg = <0 0x11010000 0 0x70>,
800			      <0 0x11000280 0 0x80>;
801			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
802			clock-div = <16>;
803			clocks = <&pericfg CLK_PERI_I2C3>,
804				 <&pericfg CLK_PERI_AP_DMA>;
805			clock-names = "main", "dma";
806			pinctrl-names = "default";
807			pinctrl-0 = <&i2c3_pins_a>;
808			#address-cells = <1>;
809			#size-cells = <0>;
810			status = "disabled";
811		};
812
813		i2c4: i2c@11011000 {
814			compatible = "mediatek,mt8173-i2c";
815			reg = <0 0x11011000 0 0x70>,
816			      <0 0x11000300 0 0x80>;
817			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
818			clock-div = <16>;
819			clocks = <&pericfg CLK_PERI_I2C4>,
820				 <&pericfg CLK_PERI_AP_DMA>;
821			clock-names = "main", "dma";
822			pinctrl-names = "default";
823			pinctrl-0 = <&i2c4_pins_a>;
824			#address-cells = <1>;
825			#size-cells = <0>;
826			status = "disabled";
827		};
828
829		hdmiddc0: i2c@11012000 {
830			compatible = "mediatek,mt8173-hdmi-ddc";
831			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
832			reg = <0 0x11012000 0 0x1C>;
833			clocks = <&pericfg CLK_PERI_I2C5>;
834			clock-names = "ddc-i2c";
835		};
836
837		i2c6: i2c@11013000 {
838			compatible = "mediatek,mt8173-i2c";
839			reg = <0 0x11013000 0 0x70>,
840			      <0 0x11000080 0 0x80>;
841			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
842			clock-div = <16>;
843			clocks = <&pericfg CLK_PERI_I2C6>,
844				 <&pericfg CLK_PERI_AP_DMA>;
845			clock-names = "main", "dma";
846			pinctrl-names = "default";
847			pinctrl-0 = <&i2c6_pins_a>;
848			#address-cells = <1>;
849			#size-cells = <0>;
850			status = "disabled";
851		};
852
853		afe: audio-controller@11220000  {
854			compatible = "mediatek,mt8173-afe-pcm";
855			reg = <0 0x11220000 0 0x1000>;
856			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
857			power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
858			clocks = <&infracfg CLK_INFRA_AUDIO>,
859				 <&topckgen CLK_TOP_AUDIO_SEL>,
860				 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
861				 <&topckgen CLK_TOP_APLL1_DIV0>,
862				 <&topckgen CLK_TOP_APLL2_DIV0>,
863				 <&topckgen CLK_TOP_I2S0_M_SEL>,
864				 <&topckgen CLK_TOP_I2S1_M_SEL>,
865				 <&topckgen CLK_TOP_I2S2_M_SEL>,
866				 <&topckgen CLK_TOP_I2S3_M_SEL>,
867				 <&topckgen CLK_TOP_I2S3_B_SEL>;
868			clock-names = "infra_sys_audio_clk",
869				      "top_pdn_audio",
870				      "top_pdn_aud_intbus",
871				      "bck0",
872				      "bck1",
873				      "i2s0_m",
874				      "i2s1_m",
875				      "i2s2_m",
876				      "i2s3_m",
877				      "i2s3_b";
878			assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
879					  <&topckgen CLK_TOP_AUD_2_SEL>;
880			assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
881						 <&topckgen CLK_TOP_APLL2>;
882		};
883
884		mmc0: mmc@11230000 {
885			compatible = "mediatek,mt8173-mmc";
886			reg = <0 0x11230000 0 0x1000>;
887			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
888			clocks = <&pericfg CLK_PERI_MSDC30_0>,
889				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
890			clock-names = "source", "hclk";
891			status = "disabled";
892		};
893
894		mmc1: mmc@11240000 {
895			compatible = "mediatek,mt8173-mmc";
896			reg = <0 0x11240000 0 0x1000>;
897			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
898			clocks = <&pericfg CLK_PERI_MSDC30_1>,
899				 <&topckgen CLK_TOP_AXI_SEL>;
900			clock-names = "source", "hclk";
901			status = "disabled";
902		};
903
904		mmc2: mmc@11250000 {
905			compatible = "mediatek,mt8173-mmc";
906			reg = <0 0x11250000 0 0x1000>;
907			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
908			clocks = <&pericfg CLK_PERI_MSDC30_2>,
909				 <&topckgen CLK_TOP_AXI_SEL>;
910			clock-names = "source", "hclk";
911			status = "disabled";
912		};
913
914		mmc3: mmc@11260000 {
915			compatible = "mediatek,mt8173-mmc";
916			reg = <0 0x11260000 0 0x1000>;
917			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
918			clocks = <&pericfg CLK_PERI_MSDC30_3>,
919				 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
920			clock-names = "source", "hclk";
921			status = "disabled";
922		};
923
924		ssusb: usb@11271000 {
925			compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
926			reg = <0 0x11271000 0 0x3000>,
927			      <0 0x11280700 0 0x0100>;
928			reg-names = "mac", "ippc";
929			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
930			phys = <&u2port0 PHY_TYPE_USB2>,
931			       <&u3port0 PHY_TYPE_USB3>,
932			       <&u2port1 PHY_TYPE_USB2>;
933			power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
934			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
935			clock-names = "sys_ck", "ref_ck";
936			mediatek,syscon-wakeup = <&pericfg 0x400 1>;
937			#address-cells = <2>;
938			#size-cells = <2>;
939			ranges;
940			status = "disabled";
941
942			usb_host: usb@11270000 {
943				compatible = "mediatek,mt8173-xhci",
944					     "mediatek,mtk-xhci";
945				reg = <0 0x11270000 0 0x1000>;
946				reg-names = "mac";
947				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
948				power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
949				clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
950				clock-names = "sys_ck", "ref_ck";
951				status = "disabled";
952			};
953		};
954
955		u3phy: t-phy@11290000 {
956			compatible = "mediatek,mt8173-u3phy";
957			reg = <0 0x11290000 0 0x800>;
958			#address-cells = <2>;
959			#size-cells = <2>;
960			ranges;
961			status = "okay";
962
963			u2port0: usb-phy@11290800 {
964				reg = <0 0x11290800 0 0x100>;
965				clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
966				clock-names = "ref";
967				#phy-cells = <1>;
968				status = "okay";
969			};
970
971			u3port0: usb-phy@11290900 {
972				reg = <0 0x11290900 0 0x700>;
973				clocks = <&clk26m>;
974				clock-names = "ref";
975				#phy-cells = <1>;
976				status = "okay";
977			};
978
979			u2port1: usb-phy@11291000 {
980				reg = <0 0x11291000 0 0x100>;
981				clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
982				clock-names = "ref";
983				#phy-cells = <1>;
984				status = "okay";
985			};
986		};
987
988		mmsys: syscon@14000000 {
989			compatible = "mediatek,mt8173-mmsys", "syscon";
990			reg = <0 0x14000000 0 0x1000>;
991			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
992			assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
993			assigned-clock-rates = <400000000>;
994			#clock-cells = <1>;
995			#reset-cells = <1>;
996			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
997				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
998			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
999		};
1000
1001		mdp_rdma0: rdma@14001000 {
1002			compatible = "mediatek,mt8173-mdp-rdma",
1003				     "mediatek,mt8173-mdp";
1004			reg = <0 0x14001000 0 0x1000>;
1005			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1006				 <&mmsys CLK_MM_MUTEX_32K>;
1007			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1008			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
1009			mediatek,vpu = <&vpu>;
1010		};
1011
1012		mdp_rdma1: rdma@14002000 {
1013			compatible = "mediatek,mt8173-mdp-rdma";
1014			reg = <0 0x14002000 0 0x1000>;
1015			clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1016				 <&mmsys CLK_MM_MUTEX_32K>;
1017			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1018			iommus = <&iommu M4U_PORT_MDP_RDMA1>;
1019		};
1020
1021		mdp_rsz0: rsz@14003000 {
1022			compatible = "mediatek,mt8173-mdp-rsz";
1023			reg = <0 0x14003000 0 0x1000>;
1024			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1025			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1026		};
1027
1028		mdp_rsz1: rsz@14004000 {
1029			compatible = "mediatek,mt8173-mdp-rsz";
1030			reg = <0 0x14004000 0 0x1000>;
1031			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1032			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1033		};
1034
1035		mdp_rsz2: rsz@14005000 {
1036			compatible = "mediatek,mt8173-mdp-rsz";
1037			reg = <0 0x14005000 0 0x1000>;
1038			clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1039			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1040		};
1041
1042		mdp_wdma0: wdma@14006000 {
1043			compatible = "mediatek,mt8173-mdp-wdma";
1044			reg = <0 0x14006000 0 0x1000>;
1045			clocks = <&mmsys CLK_MM_MDP_WDMA>;
1046			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1047			iommus = <&iommu M4U_PORT_MDP_WDMA>;
1048		};
1049
1050		mdp_wrot0: wrot@14007000 {
1051			compatible = "mediatek,mt8173-mdp-wrot";
1052			reg = <0 0x14007000 0 0x1000>;
1053			clocks = <&mmsys CLK_MM_MDP_WROT0>;
1054			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1055			iommus = <&iommu M4U_PORT_MDP_WROT0>;
1056		};
1057
1058		mdp_wrot1: wrot@14008000 {
1059			compatible = "mediatek,mt8173-mdp-wrot";
1060			reg = <0 0x14008000 0 0x1000>;
1061			clocks = <&mmsys CLK_MM_MDP_WROT1>;
1062			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1063			iommus = <&iommu M4U_PORT_MDP_WROT1>;
1064		};
1065
1066		ovl0: ovl@1400c000 {
1067			compatible = "mediatek,mt8173-disp-ovl";
1068			reg = <0 0x1400c000 0 0x1000>;
1069			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
1070			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1071			clocks = <&mmsys CLK_MM_DISP_OVL0>;
1072			iommus = <&iommu M4U_PORT_DISP_OVL0>;
1073			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1074		};
1075
1076		ovl1: ovl@1400d000 {
1077			compatible = "mediatek,mt8173-disp-ovl";
1078			reg = <0 0x1400d000 0 0x1000>;
1079			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
1080			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1081			clocks = <&mmsys CLK_MM_DISP_OVL1>;
1082			iommus = <&iommu M4U_PORT_DISP_OVL1>;
1083			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1084		};
1085
1086		rdma0: rdma@1400e000 {
1087			compatible = "mediatek,mt8173-disp-rdma";
1088			reg = <0 0x1400e000 0 0x1000>;
1089			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
1090			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1091			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1092			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1093			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1094		};
1095
1096		rdma1: rdma@1400f000 {
1097			compatible = "mediatek,mt8173-disp-rdma";
1098			reg = <0 0x1400f000 0 0x1000>;
1099			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
1100			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1101			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1102			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1103			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1104		};
1105
1106		rdma2: rdma@14010000 {
1107			compatible = "mediatek,mt8173-disp-rdma";
1108			reg = <0 0x14010000 0 0x1000>;
1109			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1110			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1111			clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1112			iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1113			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1114		};
1115
1116		wdma0: wdma@14011000 {
1117			compatible = "mediatek,mt8173-disp-wdma";
1118			reg = <0 0x14011000 0 0x1000>;
1119			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1120			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1121			clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1122			iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1123			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1124		};
1125
1126		wdma1: wdma@14012000 {
1127			compatible = "mediatek,mt8173-disp-wdma";
1128			reg = <0 0x14012000 0 0x1000>;
1129			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1130			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1131			clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1132			iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1133			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1134		};
1135
1136		color0: color@14013000 {
1137			compatible = "mediatek,mt8173-disp-color";
1138			reg = <0 0x14013000 0 0x1000>;
1139			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1140			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1141			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1142			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1143		};
1144
1145		color1: color@14014000 {
1146			compatible = "mediatek,mt8173-disp-color";
1147			reg = <0 0x14014000 0 0x1000>;
1148			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1149			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1150			clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1151			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1152		};
1153
1154		aal@14015000 {
1155			compatible = "mediatek,mt8173-disp-aal";
1156			reg = <0 0x14015000 0 0x1000>;
1157			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1158			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1159			clocks = <&mmsys CLK_MM_DISP_AAL>;
1160			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1161		};
1162
1163		gamma@14016000 {
1164			compatible = "mediatek,mt8173-disp-gamma";
1165			reg = <0 0x14016000 0 0x1000>;
1166			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1167			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1168			clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1169			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1170		};
1171
1172		merge@14017000 {
1173			compatible = "mediatek,mt8173-disp-merge";
1174			reg = <0 0x14017000 0 0x1000>;
1175			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1176			clocks = <&mmsys CLK_MM_DISP_MERGE>;
1177		};
1178
1179		split0: split@14018000 {
1180			compatible = "mediatek,mt8173-disp-split";
1181			reg = <0 0x14018000 0 0x1000>;
1182			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1183			clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1184		};
1185
1186		split1: split@14019000 {
1187			compatible = "mediatek,mt8173-disp-split";
1188			reg = <0 0x14019000 0 0x1000>;
1189			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1190			clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1191		};
1192
1193		ufoe@1401a000 {
1194			compatible = "mediatek,mt8173-disp-ufoe";
1195			reg = <0 0x1401a000 0 0x1000>;
1196			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1197			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1198			clocks = <&mmsys CLK_MM_DISP_UFOE>;
1199			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1200		};
1201
1202		dsi0: dsi@1401b000 {
1203			compatible = "mediatek,mt8173-dsi";
1204			reg = <0 0x1401b000 0 0x1000>;
1205			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1206			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1207			clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1208				 <&mmsys CLK_MM_DSI0_DIGITAL>,
1209				 <&mipi_tx0>;
1210			clock-names = "engine", "digital", "hs";
1211			resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
1212			phys = <&mipi_tx0>;
1213			phy-names = "dphy";
1214			status = "disabled";
1215		};
1216
1217		dsi1: dsi@1401c000 {
1218			compatible = "mediatek,mt8173-dsi";
1219			reg = <0 0x1401c000 0 0x1000>;
1220			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1221			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1222			clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1223				 <&mmsys CLK_MM_DSI1_DIGITAL>,
1224				 <&mipi_tx1>;
1225			clock-names = "engine", "digital", "hs";
1226			phys = <&mipi_tx1>;
1227			phy-names = "dphy";
1228			status = "disabled";
1229		};
1230
1231		dpi0: dpi@1401d000 {
1232			compatible = "mediatek,mt8173-dpi";
1233			reg = <0 0x1401d000 0 0x1000>;
1234			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1235			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1236			clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1237				 <&mmsys CLK_MM_DPI_ENGINE>,
1238				 <&apmixedsys CLK_APMIXED_TVDPLL>;
1239			clock-names = "pixel", "engine", "pll";
1240			status = "disabled";
1241
1242			port {
1243				dpi0_out: endpoint {
1244					remote-endpoint = <&hdmi0_in>;
1245				};
1246			};
1247		};
1248
1249		pwm0: pwm@1401e000 {
1250			compatible = "mediatek,mt8173-disp-pwm",
1251				     "mediatek,mt6595-disp-pwm";
1252			reg = <0 0x1401e000 0 0x1000>;
1253			#pwm-cells = <2>;
1254			clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1255				 <&mmsys CLK_MM_DISP_PWM0MM>;
1256			clock-names = "main", "mm";
1257			status = "disabled";
1258		};
1259
1260		pwm1: pwm@1401f000 {
1261			compatible = "mediatek,mt8173-disp-pwm",
1262				     "mediatek,mt6595-disp-pwm";
1263			reg = <0 0x1401f000 0 0x1000>;
1264			#pwm-cells = <2>;
1265			clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1266				 <&mmsys CLK_MM_DISP_PWM1MM>;
1267			clock-names = "main", "mm";
1268			status = "disabled";
1269		};
1270
1271		mutex: mutex@14020000 {
1272			compatible = "mediatek,mt8173-disp-mutex";
1273			reg = <0 0x14020000 0 0x1000>;
1274			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1275			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1276			clocks = <&mmsys CLK_MM_MUTEX_32K>;
1277			mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1278			mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1279                                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
1280		};
1281
1282		larb0: larb@14021000 {
1283			compatible = "mediatek,mt8173-smi-larb";
1284			reg = <0 0x14021000 0 0x1000>;
1285			mediatek,smi = <&smi_common>;
1286			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1287			clocks = <&mmsys CLK_MM_SMI_LARB0>,
1288				 <&mmsys CLK_MM_SMI_LARB0>;
1289			clock-names = "apb", "smi";
1290		};
1291
1292		smi_common: smi@14022000 {
1293			compatible = "mediatek,mt8173-smi-common";
1294			reg = <0 0x14022000 0 0x1000>;
1295			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1296			clocks = <&mmsys CLK_MM_SMI_COMMON>,
1297				 <&mmsys CLK_MM_SMI_COMMON>;
1298			clock-names = "apb", "smi";
1299		};
1300
1301		od@14023000 {
1302			compatible = "mediatek,mt8173-disp-od";
1303			reg = <0 0x14023000 0 0x1000>;
1304			clocks = <&mmsys CLK_MM_DISP_OD>;
1305			mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1306		};
1307
1308		hdmi0: hdmi@14025000 {
1309			compatible = "mediatek,mt8173-hdmi";
1310			reg = <0 0x14025000 0 0x400>;
1311			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1312			clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1313				 <&mmsys CLK_MM_HDMI_PLLCK>,
1314				 <&mmsys CLK_MM_HDMI_AUDIO>,
1315				 <&mmsys CLK_MM_HDMI_SPDIF>;
1316			clock-names = "pixel", "pll", "bclk", "spdif";
1317			pinctrl-names = "default";
1318			pinctrl-0 = <&hdmi_pin>;
1319			phys = <&hdmi_phy>;
1320			phy-names = "hdmi";
1321			mediatek,syscon-hdmi = <&mmsys 0x900>;
1322			assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1323			assigned-clock-parents = <&hdmi_phy>;
1324			status = "disabled";
1325
1326			ports {
1327				#address-cells = <1>;
1328				#size-cells = <0>;
1329
1330				port@0 {
1331					reg = <0>;
1332
1333					hdmi0_in: endpoint {
1334						remote-endpoint = <&dpi0_out>;
1335					};
1336				};
1337			};
1338		};
1339
1340		larb4: larb@14027000 {
1341			compatible = "mediatek,mt8173-smi-larb";
1342			reg = <0 0x14027000 0 0x1000>;
1343			mediatek,smi = <&smi_common>;
1344			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1345			clocks = <&mmsys CLK_MM_SMI_LARB4>,
1346				 <&mmsys CLK_MM_SMI_LARB4>;
1347			clock-names = "apb", "smi";
1348		};
1349
1350		imgsys: clock-controller@15000000 {
1351			compatible = "mediatek,mt8173-imgsys", "syscon";
1352			reg = <0 0x15000000 0 0x1000>;
1353			#clock-cells = <1>;
1354		};
1355
1356		larb2: larb@15001000 {
1357			compatible = "mediatek,mt8173-smi-larb";
1358			reg = <0 0x15001000 0 0x1000>;
1359			mediatek,smi = <&smi_common>;
1360			power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1361			clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1362				 <&imgsys CLK_IMG_LARB2_SMI>;
1363			clock-names = "apb", "smi";
1364		};
1365
1366		vdecsys: clock-controller@16000000 {
1367			compatible = "mediatek,mt8173-vdecsys", "syscon";
1368			reg = <0 0x16000000 0 0x1000>;
1369			#clock-cells = <1>;
1370		};
1371
1372		vcodec_dec: vcodec@16000000 {
1373			compatible = "mediatek,mt8173-vcodec-dec";
1374			reg = <0 0x16000000 0 0x100>,	/* VDEC_SYS */
1375			      <0 0x16020000 0 0x1000>,	/* VDEC_MISC */
1376			      <0 0x16021000 0 0x800>,	/* VDEC_LD */
1377			      <0 0x16021800 0 0x800>,	/* VDEC_TOP */
1378			      <0 0x16022000 0 0x1000>,	/* VDEC_CM */
1379			      <0 0x16023000 0 0x1000>,	/* VDEC_AD */
1380			      <0 0x16024000 0 0x1000>,	/* VDEC_AV */
1381			      <0 0x16025000 0 0x1000>,	/* VDEC_PP */
1382			      <0 0x16026800 0 0x800>,	/* VDEC_HWD */
1383			      <0 0x16027000 0 0x800>,	/* VDEC_HWQ */
1384			      <0 0x16027800 0 0x800>,	/* VDEC_HWB */
1385			      <0 0x16028400 0 0x400>;	/* VDEC_HWG */
1386			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1387			iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1388				 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1389				 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1390				 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1391				 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1392				 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1393				 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1394				 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1395			mediatek,vpu = <&vpu>;
1396			power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1397			clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1398				 <&topckgen CLK_TOP_UNIVPLL_D2>,
1399				 <&topckgen CLK_TOP_CCI400_SEL>,
1400				 <&topckgen CLK_TOP_VDEC_SEL>,
1401				 <&topckgen CLK_TOP_VCODECPLL>,
1402				 <&apmixedsys CLK_APMIXED_VENCPLL>,
1403				 <&topckgen CLK_TOP_VENC_LT_SEL>,
1404				 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1405			clock-names = "vcodecpll",
1406				      "univpll_d2",
1407				      "clk_cci400_sel",
1408				      "vdec_sel",
1409				      "vdecpll",
1410				      "vencpll",
1411				      "venc_lt_sel",
1412				      "vdec_bus_clk_src";
1413			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1414					  <&topckgen CLK_TOP_CCI400_SEL>,
1415					  <&topckgen CLK_TOP_VDEC_SEL>,
1416					  <&apmixedsys CLK_APMIXED_VCODECPLL>,
1417					  <&apmixedsys CLK_APMIXED_VENCPLL>;
1418			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1419						 <&topckgen CLK_TOP_UNIVPLL_D2>,
1420						 <&topckgen CLK_TOP_VCODECPLL>;
1421			assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1422		};
1423
1424		larb1: larb@16010000 {
1425			compatible = "mediatek,mt8173-smi-larb";
1426			reg = <0 0x16010000 0 0x1000>;
1427			mediatek,smi = <&smi_common>;
1428			power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1429			clocks = <&vdecsys CLK_VDEC_CKEN>,
1430				 <&vdecsys CLK_VDEC_LARB_CKEN>;
1431			clock-names = "apb", "smi";
1432		};
1433
1434		vencsys: clock-controller@18000000 {
1435			compatible = "mediatek,mt8173-vencsys", "syscon";
1436			reg = <0 0x18000000 0 0x1000>;
1437			#clock-cells = <1>;
1438		};
1439
1440		larb3: larb@18001000 {
1441			compatible = "mediatek,mt8173-smi-larb";
1442			reg = <0 0x18001000 0 0x1000>;
1443			mediatek,smi = <&smi_common>;
1444			power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1445			clocks = <&vencsys CLK_VENC_CKE1>,
1446				 <&vencsys CLK_VENC_CKE0>;
1447			clock-names = "apb", "smi";
1448		};
1449
1450		vcodec_enc_avc: vcodec@18002000 {
1451			compatible = "mediatek,mt8173-vcodec-enc";
1452			reg = <0 0x18002000 0 0x1000>;	/* VENC_SYS */
1453			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1454			iommus = <&iommu M4U_PORT_VENC_RCPU>,
1455				 <&iommu M4U_PORT_VENC_REC>,
1456				 <&iommu M4U_PORT_VENC_BSDMA>,
1457				 <&iommu M4U_PORT_VENC_SV_COMV>,
1458				 <&iommu M4U_PORT_VENC_RD_COMV>,
1459				 <&iommu M4U_PORT_VENC_CUR_LUMA>,
1460				 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1461				 <&iommu M4U_PORT_VENC_REF_LUMA>,
1462				 <&iommu M4U_PORT_VENC_REF_CHROMA>,
1463				 <&iommu M4U_PORT_VENC_NBM_RDMA>,
1464				 <&iommu M4U_PORT_VENC_NBM_WDMA>;
1465			mediatek,vpu = <&vpu>;
1466			clocks = <&topckgen CLK_TOP_VENC_SEL>;
1467			clock-names = "venc_sel";
1468			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1469			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1470			power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1471		};
1472
1473		jpegdec: jpegdec@18004000 {
1474			compatible = "mediatek,mt8173-jpgdec";
1475			reg = <0 0x18004000 0 0x1000>;
1476			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
1477			clocks = <&vencsys CLK_VENC_CKE0>,
1478				 <&vencsys CLK_VENC_CKE3>;
1479			clock-names = "jpgdec-smi",
1480				      "jpgdec";
1481			power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1482			iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
1483				 <&iommu M4U_PORT_JPGDEC_BSDMA>;
1484		};
1485
1486		vencltsys: clock-controller@19000000 {
1487			compatible = "mediatek,mt8173-vencltsys", "syscon";
1488			reg = <0 0x19000000 0 0x1000>;
1489			#clock-cells = <1>;
1490		};
1491
1492		larb5: larb@19001000 {
1493			compatible = "mediatek,mt8173-smi-larb";
1494			reg = <0 0x19001000 0 0x1000>;
1495			mediatek,smi = <&smi_common>;
1496			power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1497			clocks = <&vencltsys CLK_VENCLT_CKE1>,
1498				 <&vencltsys CLK_VENCLT_CKE0>;
1499			clock-names = "apb", "smi";
1500		};
1501
1502		vcodec_enc_vp8: vcodec@19002000 {
1503			compatible = "mediatek,mt8173-vcodec-enc-vp8";
1504			reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1505			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1506			iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
1507				 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1508				 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1509				 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1510				 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1511				 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1512				 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1513				 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1514				 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1515			mediatek,vpu = <&vpu>;
1516			clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1517			clock-names = "venc_lt_sel";
1518			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1519			assigned-clock-parents =
1520				 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1521			power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1522		};
1523	};
1524};
1525