1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu-map { 34 cluster0 { 35 core0 { 36 cpu = <&cpu0>; 37 }; 38 core1 { 39 cpu = <&cpu1>; 40 }; 41 }; 42 43 cluster1 { 44 core0 { 45 cpu = <&cpu2>; 46 }; 47 core1 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 }; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 }; 60 61 cpu1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x001>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 }; 68 69 cpu2: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a57"; 72 reg = <0x100>; 73 enable-method = "psci"; 74 cpu-idle-states = <&CPU_SLEEP_0>; 75 }; 76 77 cpu3: cpu@101 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a57"; 80 reg = <0x101>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CPU_SLEEP_0>; 83 }; 84 85 idle-states { 86 entry-method = "psci"; 87 88 CPU_SLEEP_0: cpu-sleep-0 { 89 compatible = "arm,idle-state"; 90 local-timer-stop; 91 entry-latency-us = <639>; 92 exit-latency-us = <680>; 93 min-residency-us = <1088>; 94 arm,psci-suspend-param = <0x0010000>; 95 }; 96 }; 97 }; 98 99 psci { 100 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 101 method = "smc"; 102 cpu_suspend = <0x84000001>; 103 cpu_off = <0x84000002>; 104 cpu_on = <0x84000003>; 105 }; 106 107 clk26m: oscillator@0 { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <26000000>; 111 clock-output-names = "clk26m"; 112 }; 113 114 clk32k: oscillator@1 { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <32000>; 118 clock-output-names = "clk32k"; 119 }; 120 121 cpum_ck: oscillator@2 { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 clock-output-names = "cpum_ck"; 126 }; 127 128 thermal-zones { 129 cpu_thermal: cpu_thermal { 130 polling-delay-passive = <1000>; /* milliseconds */ 131 polling-delay = <1000>; /* milliseconds */ 132 133 thermal-sensors = <&thermal>; 134 sustainable-power = <1500>; /* milliwatts */ 135 136 trips { 137 threshold: trip-point@0 { 138 temperature = <68000>; 139 hysteresis = <2000>; 140 type = "passive"; 141 }; 142 143 target: trip-point@1 { 144 temperature = <85000>; 145 hysteresis = <2000>; 146 type = "passive"; 147 }; 148 149 cpu_crit: cpu_crit@0 { 150 temperature = <115000>; 151 hysteresis = <2000>; 152 type = "critical"; 153 }; 154 }; 155 156 cooling-maps { 157 map@0 { 158 trip = <&target>; 159 cooling-device = <&cpu0 0 0>; 160 contribution = <1024>; 161 }; 162 map@1 { 163 trip = <&target>; 164 cooling-device = <&cpu2 0 0>; 165 contribution = <2048>; 166 }; 167 }; 168 }; 169 }; 170 171 timer { 172 compatible = "arm,armv8-timer"; 173 interrupt-parent = <&gic>; 174 interrupts = <GIC_PPI 13 175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 176 <GIC_PPI 14 177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 178 <GIC_PPI 11 179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 180 <GIC_PPI 10 181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 182 }; 183 184 soc { 185 #address-cells = <2>; 186 #size-cells = <2>; 187 compatible = "simple-bus"; 188 ranges; 189 190 topckgen: clock-controller@10000000 { 191 compatible = "mediatek,mt8173-topckgen"; 192 reg = <0 0x10000000 0 0x1000>; 193 #clock-cells = <1>; 194 }; 195 196 infracfg: power-controller@10001000 { 197 compatible = "mediatek,mt8173-infracfg", "syscon"; 198 reg = <0 0x10001000 0 0x1000>; 199 #clock-cells = <1>; 200 #reset-cells = <1>; 201 }; 202 203 pericfg: power-controller@10003000 { 204 compatible = "mediatek,mt8173-pericfg", "syscon"; 205 reg = <0 0x10003000 0 0x1000>; 206 #clock-cells = <1>; 207 #reset-cells = <1>; 208 }; 209 210 syscfg_pctl_a: syscfg_pctl_a@10005000 { 211 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 212 reg = <0 0x10005000 0 0x1000>; 213 }; 214 215 pio: pinctrl@0x10005000 { 216 compatible = "mediatek,mt8173-pinctrl"; 217 reg = <0 0x1000b000 0 0x1000>; 218 mediatek,pctl-regmap = <&syscfg_pctl_a>; 219 pins-are-numbered; 220 gpio-controller; 221 #gpio-cells = <2>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 227 228 i2c0_pins_a: i2c0 { 229 pins1 { 230 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 231 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 232 bias-disable; 233 }; 234 }; 235 236 i2c1_pins_a: i2c1 { 237 pins1 { 238 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 239 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 240 bias-disable; 241 }; 242 }; 243 244 i2c2_pins_a: i2c2 { 245 pins1 { 246 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 247 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 248 bias-disable; 249 }; 250 }; 251 252 i2c3_pins_a: i2c3 { 253 pins1 { 254 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 255 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 256 bias-disable; 257 }; 258 }; 259 260 i2c4_pins_a: i2c4 { 261 pins1 { 262 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 263 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 264 bias-disable; 265 }; 266 }; 267 268 i2c6_pins_a: i2c6 { 269 pins1 { 270 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 271 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 272 bias-disable; 273 }; 274 }; 275 }; 276 277 scpsys: scpsys@10006000 { 278 compatible = "mediatek,mt8173-scpsys"; 279 #power-domain-cells = <1>; 280 reg = <0 0x10006000 0 0x1000>; 281 clocks = <&clk26m>, 282 <&topckgen CLK_TOP_MM_SEL>, 283 <&topckgen CLK_TOP_VENC_SEL>, 284 <&topckgen CLK_TOP_VENC_LT_SEL>; 285 clock-names = "mfg", "mm", "venc", "venc_lt"; 286 infracfg = <&infracfg>; 287 }; 288 289 watchdog: watchdog@10007000 { 290 compatible = "mediatek,mt8173-wdt", 291 "mediatek,mt6589-wdt"; 292 reg = <0 0x10007000 0 0x100>; 293 }; 294 295 timer: timer@10008000 { 296 compatible = "mediatek,mt8173-timer", 297 "mediatek,mt6577-timer"; 298 reg = <0 0x10008000 0 0x1000>; 299 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 300 clocks = <&infracfg CLK_INFRA_CLK_13M>, 301 <&topckgen CLK_TOP_RTC_SEL>; 302 }; 303 304 pwrap: pwrap@1000d000 { 305 compatible = "mediatek,mt8173-pwrap"; 306 reg = <0 0x1000d000 0 0x1000>; 307 reg-names = "pwrap"; 308 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 309 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 310 reset-names = "pwrap"; 311 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 312 clock-names = "spi", "wrap"; 313 }; 314 315 sysirq: intpol-controller@10200620 { 316 compatible = "mediatek,mt8173-sysirq", 317 "mediatek,mt6577-sysirq"; 318 interrupt-controller; 319 #interrupt-cells = <3>; 320 interrupt-parent = <&gic>; 321 reg = <0 0x10200620 0 0x20>; 322 }; 323 324 iommu: iommu@10205000 { 325 compatible = "mediatek,mt8173-m4u"; 326 reg = <0 0x10205000 0 0x1000>; 327 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 328 clocks = <&infracfg CLK_INFRA_M4U>; 329 clock-names = "bclk"; 330 mediatek,larbs = <&larb0 &larb1 &larb2 331 &larb3 &larb4 &larb5>; 332 #iommu-cells = <1>; 333 }; 334 335 efuse: efuse@10206000 { 336 compatible = "mediatek,mt8173-efuse"; 337 reg = <0 0x10206000 0 0x1000>; 338 }; 339 340 apmixedsys: clock-controller@10209000 { 341 compatible = "mediatek,mt8173-apmixedsys"; 342 reg = <0 0x10209000 0 0x1000>; 343 #clock-cells = <1>; 344 }; 345 346 gic: interrupt-controller@10220000 { 347 compatible = "arm,gic-400"; 348 #interrupt-cells = <3>; 349 interrupt-parent = <&gic>; 350 interrupt-controller; 351 reg = <0 0x10221000 0 0x1000>, 352 <0 0x10222000 0 0x2000>, 353 <0 0x10224000 0 0x2000>, 354 <0 0x10226000 0 0x2000>; 355 interrupts = <GIC_PPI 9 356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 357 }; 358 359 auxadc: auxadc@11001000 { 360 compatible = "mediatek,mt8173-auxadc"; 361 reg = <0 0x11001000 0 0x1000>; 362 }; 363 364 uart0: serial@11002000 { 365 compatible = "mediatek,mt8173-uart", 366 "mediatek,mt6577-uart"; 367 reg = <0 0x11002000 0 0x400>; 368 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 369 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 370 clock-names = "baud", "bus"; 371 status = "disabled"; 372 }; 373 374 uart1: serial@11003000 { 375 compatible = "mediatek,mt8173-uart", 376 "mediatek,mt6577-uart"; 377 reg = <0 0x11003000 0 0x400>; 378 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 379 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 380 clock-names = "baud", "bus"; 381 status = "disabled"; 382 }; 383 384 uart2: serial@11004000 { 385 compatible = "mediatek,mt8173-uart", 386 "mediatek,mt6577-uart"; 387 reg = <0 0x11004000 0 0x400>; 388 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 389 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 390 clock-names = "baud", "bus"; 391 status = "disabled"; 392 }; 393 394 uart3: serial@11005000 { 395 compatible = "mediatek,mt8173-uart", 396 "mediatek,mt6577-uart"; 397 reg = <0 0x11005000 0 0x400>; 398 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 399 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 400 clock-names = "baud", "bus"; 401 status = "disabled"; 402 }; 403 404 i2c0: i2c@11007000 { 405 compatible = "mediatek,mt8173-i2c"; 406 reg = <0 0x11007000 0 0x70>, 407 <0 0x11000100 0 0x80>; 408 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 409 clock-div = <16>; 410 clocks = <&pericfg CLK_PERI_I2C0>, 411 <&pericfg CLK_PERI_AP_DMA>; 412 clock-names = "main", "dma"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2c0_pins_a>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 i2c1: i2c@11008000 { 421 compatible = "mediatek,mt8173-i2c"; 422 reg = <0 0x11008000 0 0x70>, 423 <0 0x11000180 0 0x80>; 424 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 425 clock-div = <16>; 426 clocks = <&pericfg CLK_PERI_I2C1>, 427 <&pericfg CLK_PERI_AP_DMA>; 428 clock-names = "main", "dma"; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&i2c1_pins_a>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 status = "disabled"; 434 }; 435 436 i2c2: i2c@11009000 { 437 compatible = "mediatek,mt8173-i2c"; 438 reg = <0 0x11009000 0 0x70>, 439 <0 0x11000200 0 0x80>; 440 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 441 clock-div = <16>; 442 clocks = <&pericfg CLK_PERI_I2C2>, 443 <&pericfg CLK_PERI_AP_DMA>; 444 clock-names = "main", "dma"; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&i2c2_pins_a>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 spi: spi@1100a000 { 453 compatible = "mediatek,mt8173-spi"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 reg = <0 0x1100a000 0 0x1000>; 457 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 458 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 459 <&topckgen CLK_TOP_SPI_SEL>, 460 <&pericfg CLK_PERI_SPI0>; 461 clock-names = "parent-clk", "sel-clk", "spi-clk"; 462 status = "disabled"; 463 }; 464 465 thermal: thermal@1100b000 { 466 #thermal-sensor-cells = <0>; 467 compatible = "mediatek,mt8173-thermal"; 468 reg = <0 0x1100b000 0 0x1000>; 469 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 470 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 471 clock-names = "therm", "auxadc"; 472 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 473 mediatek,auxadc = <&auxadc>; 474 mediatek,apmixedsys = <&apmixedsys>; 475 }; 476 477 nor_flash: spi@1100d000 { 478 compatible = "mediatek,mt8173-nor"; 479 reg = <0 0x1100d000 0 0xe0>; 480 clocks = <&pericfg CLK_PERI_SPI>, 481 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 482 clock-names = "spi", "sf"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 status = "disabled"; 486 }; 487 488 i2c3: i2c@11010000 { 489 compatible = "mediatek,mt8173-i2c"; 490 reg = <0 0x11010000 0 0x70>, 491 <0 0x11000280 0 0x80>; 492 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 493 clock-div = <16>; 494 clocks = <&pericfg CLK_PERI_I2C3>, 495 <&pericfg CLK_PERI_AP_DMA>; 496 clock-names = "main", "dma"; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&i2c3_pins_a>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 status = "disabled"; 502 }; 503 504 i2c4: i2c@11011000 { 505 compatible = "mediatek,mt8173-i2c"; 506 reg = <0 0x11011000 0 0x70>, 507 <0 0x11000300 0 0x80>; 508 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 509 clock-div = <16>; 510 clocks = <&pericfg CLK_PERI_I2C4>, 511 <&pericfg CLK_PERI_AP_DMA>; 512 clock-names = "main", "dma"; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&i2c4_pins_a>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 status = "disabled"; 518 }; 519 520 i2c6: i2c@11013000 { 521 compatible = "mediatek,mt8173-i2c"; 522 reg = <0 0x11013000 0 0x70>, 523 <0 0x11000080 0 0x80>; 524 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 525 clock-div = <16>; 526 clocks = <&pericfg CLK_PERI_I2C6>, 527 <&pericfg CLK_PERI_AP_DMA>; 528 clock-names = "main", "dma"; 529 pinctrl-names = "default"; 530 pinctrl-0 = <&i2c6_pins_a>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 status = "disabled"; 534 }; 535 536 afe: audio-controller@11220000 { 537 compatible = "mediatek,mt8173-afe-pcm"; 538 reg = <0 0x11220000 0 0x1000>; 539 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 540 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 541 clocks = <&infracfg CLK_INFRA_AUDIO>, 542 <&topckgen CLK_TOP_AUDIO_SEL>, 543 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 544 <&topckgen CLK_TOP_APLL1_DIV0>, 545 <&topckgen CLK_TOP_APLL2_DIV0>, 546 <&topckgen CLK_TOP_I2S0_M_SEL>, 547 <&topckgen CLK_TOP_I2S1_M_SEL>, 548 <&topckgen CLK_TOP_I2S2_M_SEL>, 549 <&topckgen CLK_TOP_I2S3_M_SEL>, 550 <&topckgen CLK_TOP_I2S3_B_SEL>; 551 clock-names = "infra_sys_audio_clk", 552 "top_pdn_audio", 553 "top_pdn_aud_intbus", 554 "bck0", 555 "bck1", 556 "i2s0_m", 557 "i2s1_m", 558 "i2s2_m", 559 "i2s3_m", 560 "i2s3_b"; 561 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 562 <&topckgen CLK_TOP_AUD_2_SEL>; 563 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 564 <&topckgen CLK_TOP_APLL2>; 565 }; 566 567 mmc0: mmc@11230000 { 568 compatible = "mediatek,mt8173-mmc", 569 "mediatek,mt8135-mmc"; 570 reg = <0 0x11230000 0 0x1000>; 571 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 572 clocks = <&pericfg CLK_PERI_MSDC30_0>, 573 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 574 clock-names = "source", "hclk"; 575 status = "disabled"; 576 }; 577 578 mmc1: mmc@11240000 { 579 compatible = "mediatek,mt8173-mmc", 580 "mediatek,mt8135-mmc"; 581 reg = <0 0x11240000 0 0x1000>; 582 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 583 clocks = <&pericfg CLK_PERI_MSDC30_1>, 584 <&topckgen CLK_TOP_AXI_SEL>; 585 clock-names = "source", "hclk"; 586 status = "disabled"; 587 }; 588 589 mmc2: mmc@11250000 { 590 compatible = "mediatek,mt8173-mmc", 591 "mediatek,mt8135-mmc"; 592 reg = <0 0x11250000 0 0x1000>; 593 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 594 clocks = <&pericfg CLK_PERI_MSDC30_2>, 595 <&topckgen CLK_TOP_AXI_SEL>; 596 clock-names = "source", "hclk"; 597 status = "disabled"; 598 }; 599 600 mmc3: mmc@11260000 { 601 compatible = "mediatek,mt8173-mmc", 602 "mediatek,mt8135-mmc"; 603 reg = <0 0x11260000 0 0x1000>; 604 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 605 clocks = <&pericfg CLK_PERI_MSDC30_3>, 606 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 607 clock-names = "source", "hclk"; 608 status = "disabled"; 609 }; 610 611 usb30: usb@11270000 { 612 compatible = "mediatek,mt8173-xhci"; 613 reg = <0 0x11270000 0 0x1000>, 614 <0 0x11280700 0 0x0100>; 615 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 616 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 617 clocks = <&topckgen CLK_TOP_USB30_SEL>, 618 <&pericfg CLK_PERI_USB0>, 619 <&pericfg CLK_PERI_USB1>; 620 clock-names = "sys_ck", 621 "wakeup_deb_p0", 622 "wakeup_deb_p1"; 623 phys = <&phy_port0 PHY_TYPE_USB3>, 624 <&phy_port1 PHY_TYPE_USB2>; 625 mediatek,syscon-wakeup = <&pericfg>; 626 status = "okay"; 627 }; 628 629 u3phy: usb-phy@11290000 { 630 compatible = "mediatek,mt8173-u3phy"; 631 reg = <0 0x11290000 0 0x800>; 632 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 633 clock-names = "u3phya_ref"; 634 #address-cells = <2>; 635 #size-cells = <2>; 636 ranges; 637 status = "okay"; 638 639 phy_port0: port@11290800 { 640 reg = <0 0x11290800 0 0x800>; 641 #phy-cells = <1>; 642 status = "okay"; 643 }; 644 645 phy_port1: port@11291000 { 646 reg = <0 0x11291000 0 0x800>; 647 #phy-cells = <1>; 648 status = "okay"; 649 }; 650 }; 651 652 mmsys: clock-controller@14000000 { 653 compatible = "mediatek,mt8173-mmsys", "syscon"; 654 reg = <0 0x14000000 0 0x1000>; 655 #clock-cells = <1>; 656 }; 657 658 pwm0: pwm@1401e000 { 659 compatible = "mediatek,mt8173-disp-pwm", 660 "mediatek,mt6595-disp-pwm"; 661 reg = <0 0x1401e000 0 0x1000>; 662 #pwm-cells = <2>; 663 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 664 <&mmsys CLK_MM_DISP_PWM0MM>; 665 clock-names = "main", "mm"; 666 status = "disabled"; 667 }; 668 669 pwm1: pwm@1401f000 { 670 compatible = "mediatek,mt8173-disp-pwm", 671 "mediatek,mt6595-disp-pwm"; 672 reg = <0 0x1401f000 0 0x1000>; 673 #pwm-cells = <2>; 674 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 675 <&mmsys CLK_MM_DISP_PWM1MM>; 676 clock-names = "main", "mm"; 677 status = "disabled"; 678 }; 679 680 larb0: larb@14021000 { 681 compatible = "mediatek,mt8173-smi-larb"; 682 reg = <0 0x14021000 0 0x1000>; 683 mediatek,smi = <&smi_common>; 684 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 685 clocks = <&mmsys CLK_MM_SMI_LARB0>, 686 <&mmsys CLK_MM_SMI_LARB0>; 687 clock-names = "apb", "smi"; 688 }; 689 690 smi_common: smi@14022000 { 691 compatible = "mediatek,mt8173-smi-common"; 692 reg = <0 0x14022000 0 0x1000>; 693 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 694 clocks = <&mmsys CLK_MM_SMI_COMMON>, 695 <&mmsys CLK_MM_SMI_COMMON>; 696 clock-names = "apb", "smi"; 697 }; 698 699 larb4: larb@14027000 { 700 compatible = "mediatek,mt8173-smi-larb"; 701 reg = <0 0x14027000 0 0x1000>; 702 mediatek,smi = <&smi_common>; 703 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 704 clocks = <&mmsys CLK_MM_SMI_LARB4>, 705 <&mmsys CLK_MM_SMI_LARB4>; 706 clock-names = "apb", "smi"; 707 }; 708 709 imgsys: clock-controller@15000000 { 710 compatible = "mediatek,mt8173-imgsys", "syscon"; 711 reg = <0 0x15000000 0 0x1000>; 712 #clock-cells = <1>; 713 }; 714 715 larb2: larb@15001000 { 716 compatible = "mediatek,mt8173-smi-larb"; 717 reg = <0 0x15001000 0 0x1000>; 718 mediatek,smi = <&smi_common>; 719 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 720 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 721 <&imgsys CLK_IMG_LARB2_SMI>; 722 clock-names = "apb", "smi"; 723 }; 724 725 vdecsys: clock-controller@16000000 { 726 compatible = "mediatek,mt8173-vdecsys", "syscon"; 727 reg = <0 0x16000000 0 0x1000>; 728 #clock-cells = <1>; 729 }; 730 731 larb1: larb@16010000 { 732 compatible = "mediatek,mt8173-smi-larb"; 733 reg = <0 0x16010000 0 0x1000>; 734 mediatek,smi = <&smi_common>; 735 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 736 clocks = <&vdecsys CLK_VDEC_CKEN>, 737 <&vdecsys CLK_VDEC_LARB_CKEN>; 738 clock-names = "apb", "smi"; 739 }; 740 741 vencsys: clock-controller@18000000 { 742 compatible = "mediatek,mt8173-vencsys", "syscon"; 743 reg = <0 0x18000000 0 0x1000>; 744 #clock-cells = <1>; 745 }; 746 747 larb3: larb@18001000 { 748 compatible = "mediatek,mt8173-smi-larb"; 749 reg = <0 0x18001000 0 0x1000>; 750 mediatek,smi = <&smi_common>; 751 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 752 clocks = <&vencsys CLK_VENC_CKE1>, 753 <&vencsys CLK_VENC_CKE0>; 754 clock-names = "apb", "smi"; 755 }; 756 757 vencltsys: clock-controller@19000000 { 758 compatible = "mediatek,mt8173-vencltsys", "syscon"; 759 reg = <0 0x19000000 0 0x1000>; 760 #clock-cells = <1>; 761 }; 762 763 larb5: larb@19001000 { 764 compatible = "mediatek,mt8173-smi-larb"; 765 reg = <0 0x19001000 0 0x1000>; 766 mediatek,smi = <&smi_common>; 767 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 768 clocks = <&vencltsys CLK_VENCLT_CKE1>, 769 <&vencltsys CLK_VENCLT_CKE0>; 770 clock-names = "apb", "smi"; 771 }; 772 }; 773}; 774 775