1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 ovl0 = &ovl0; 31 ovl1 = &ovl1; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 rdma2 = &rdma2; 35 wdma0 = &wdma0; 36 wdma1 = &wdma1; 37 color0 = &color0; 38 color1 = &color1; 39 split0 = &split0; 40 split1 = &split1; 41 dpi0 = &dpi0; 42 dsi0 = &dsi0; 43 dsi1 = &dsi1; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu-map { 51 cluster0 { 52 core0 { 53 cpu = <&cpu0>; 54 }; 55 core1 { 56 cpu = <&cpu1>; 57 }; 58 }; 59 60 cluster1 { 61 core0 { 62 cpu = <&cpu2>; 63 }; 64 core1 { 65 cpu = <&cpu3>; 66 }; 67 }; 68 }; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x000>; 74 enable-method = "psci"; 75 cpu-idle-states = <&CPU_SLEEP_0>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x001>; 82 enable-method = "psci"; 83 cpu-idle-states = <&CPU_SLEEP_0>; 84 }; 85 86 cpu2: cpu@100 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a57"; 89 reg = <0x100>; 90 enable-method = "psci"; 91 cpu-idle-states = <&CPU_SLEEP_0>; 92 }; 93 94 cpu3: cpu@101 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57"; 97 reg = <0x101>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 }; 101 102 idle-states { 103 entry-method = "psci"; 104 105 CPU_SLEEP_0: cpu-sleep-0 { 106 compatible = "arm,idle-state"; 107 local-timer-stop; 108 entry-latency-us = <639>; 109 exit-latency-us = <680>; 110 min-residency-us = <1088>; 111 arm,psci-suspend-param = <0x0010000>; 112 }; 113 }; 114 }; 115 116 psci { 117 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 118 method = "smc"; 119 cpu_suspend = <0x84000001>; 120 cpu_off = <0x84000002>; 121 cpu_on = <0x84000003>; 122 }; 123 124 clk26m: oscillator@0 { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <26000000>; 128 clock-output-names = "clk26m"; 129 }; 130 131 clk32k: oscillator@1 { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 clock-frequency = <32000>; 135 clock-output-names = "clk32k"; 136 }; 137 138 cpum_ck: oscillator@2 { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 clock-frequency = <0>; 142 clock-output-names = "cpum_ck"; 143 }; 144 145 thermal-zones { 146 cpu_thermal: cpu_thermal { 147 polling-delay-passive = <1000>; /* milliseconds */ 148 polling-delay = <1000>; /* milliseconds */ 149 150 thermal-sensors = <&thermal>; 151 sustainable-power = <1500>; /* milliwatts */ 152 153 trips { 154 threshold: trip-point@0 { 155 temperature = <68000>; 156 hysteresis = <2000>; 157 type = "passive"; 158 }; 159 160 target: trip-point@1 { 161 temperature = <85000>; 162 hysteresis = <2000>; 163 type = "passive"; 164 }; 165 166 cpu_crit: cpu_crit@0 { 167 temperature = <115000>; 168 hysteresis = <2000>; 169 type = "critical"; 170 }; 171 }; 172 173 cooling-maps { 174 map@0 { 175 trip = <&target>; 176 cooling-device = <&cpu0 0 0>; 177 contribution = <1024>; 178 }; 179 map@1 { 180 trip = <&target>; 181 cooling-device = <&cpu2 0 0>; 182 contribution = <2048>; 183 }; 184 }; 185 }; 186 }; 187 188 reserved-memory { 189 #address-cells = <2>; 190 #size-cells = <2>; 191 ranges; 192 vpu_dma_reserved: vpu_dma_mem_region { 193 compatible = "shared-dma-pool"; 194 reg = <0 0xb7000000 0 0x500000>; 195 alignment = <0x1000>; 196 no-map; 197 }; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupt-parent = <&gic>; 203 interrupts = <GIC_PPI 13 204 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 205 <GIC_PPI 14 206 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 207 <GIC_PPI 11 208 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 209 <GIC_PPI 10 210 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 211 }; 212 213 soc { 214 #address-cells = <2>; 215 #size-cells = <2>; 216 compatible = "simple-bus"; 217 ranges; 218 219 topckgen: clock-controller@10000000 { 220 compatible = "mediatek,mt8173-topckgen"; 221 reg = <0 0x10000000 0 0x1000>; 222 #clock-cells = <1>; 223 }; 224 225 infracfg: power-controller@10001000 { 226 compatible = "mediatek,mt8173-infracfg", "syscon"; 227 reg = <0 0x10001000 0 0x1000>; 228 #clock-cells = <1>; 229 #reset-cells = <1>; 230 }; 231 232 pericfg: power-controller@10003000 { 233 compatible = "mediatek,mt8173-pericfg", "syscon"; 234 reg = <0 0x10003000 0 0x1000>; 235 #clock-cells = <1>; 236 #reset-cells = <1>; 237 }; 238 239 syscfg_pctl_a: syscfg_pctl_a@10005000 { 240 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 241 reg = <0 0x10005000 0 0x1000>; 242 }; 243 244 pio: pinctrl@0x10005000 { 245 compatible = "mediatek,mt8173-pinctrl"; 246 reg = <0 0x1000b000 0 0x1000>; 247 mediatek,pctl-regmap = <&syscfg_pctl_a>; 248 pins-are-numbered; 249 gpio-controller; 250 #gpio-cells = <2>; 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 256 257 i2c0_pins_a: i2c0 { 258 pins1 { 259 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 260 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 261 bias-disable; 262 }; 263 }; 264 265 i2c1_pins_a: i2c1 { 266 pins1 { 267 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 268 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 269 bias-disable; 270 }; 271 }; 272 273 i2c2_pins_a: i2c2 { 274 pins1 { 275 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 276 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 277 bias-disable; 278 }; 279 }; 280 281 i2c3_pins_a: i2c3 { 282 pins1 { 283 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 284 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 285 bias-disable; 286 }; 287 }; 288 289 i2c4_pins_a: i2c4 { 290 pins1 { 291 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 292 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 293 bias-disable; 294 }; 295 }; 296 297 i2c6_pins_a: i2c6 { 298 pins1 { 299 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 300 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 301 bias-disable; 302 }; 303 }; 304 }; 305 306 scpsys: scpsys@10006000 { 307 compatible = "mediatek,mt8173-scpsys"; 308 #power-domain-cells = <1>; 309 reg = <0 0x10006000 0 0x1000>; 310 clocks = <&clk26m>, 311 <&topckgen CLK_TOP_MM_SEL>, 312 <&topckgen CLK_TOP_VENC_SEL>, 313 <&topckgen CLK_TOP_VENC_LT_SEL>; 314 clock-names = "mfg", "mm", "venc", "venc_lt"; 315 infracfg = <&infracfg>; 316 }; 317 318 watchdog: watchdog@10007000 { 319 compatible = "mediatek,mt8173-wdt", 320 "mediatek,mt6589-wdt"; 321 reg = <0 0x10007000 0 0x100>; 322 }; 323 324 timer: timer@10008000 { 325 compatible = "mediatek,mt8173-timer", 326 "mediatek,mt6577-timer"; 327 reg = <0 0x10008000 0 0x1000>; 328 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 329 clocks = <&infracfg CLK_INFRA_CLK_13M>, 330 <&topckgen CLK_TOP_RTC_SEL>; 331 }; 332 333 pwrap: pwrap@1000d000 { 334 compatible = "mediatek,mt8173-pwrap"; 335 reg = <0 0x1000d000 0 0x1000>; 336 reg-names = "pwrap"; 337 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 338 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 339 reset-names = "pwrap"; 340 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 341 clock-names = "spi", "wrap"; 342 }; 343 344 vpu: vpu@10020000 { 345 compatible = "mediatek,mt8173-vpu"; 346 reg = <0 0x10020000 0 0x30000>, 347 <0 0x10050000 0 0x100>; 348 reg-names = "tcm", "cfg_reg"; 349 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&topckgen CLK_TOP_SCP_SEL>; 351 clock-names = "main"; 352 memory-region = <&vpu_dma_reserved>; 353 }; 354 355 sysirq: intpol-controller@10200620 { 356 compatible = "mediatek,mt8173-sysirq", 357 "mediatek,mt6577-sysirq"; 358 interrupt-controller; 359 #interrupt-cells = <3>; 360 interrupt-parent = <&gic>; 361 reg = <0 0x10200620 0 0x20>; 362 }; 363 364 iommu: iommu@10205000 { 365 compatible = "mediatek,mt8173-m4u"; 366 reg = <0 0x10205000 0 0x1000>; 367 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 368 clocks = <&infracfg CLK_INFRA_M4U>; 369 clock-names = "bclk"; 370 mediatek,larbs = <&larb0 &larb1 &larb2 371 &larb3 &larb4 &larb5>; 372 #iommu-cells = <1>; 373 }; 374 375 efuse: efuse@10206000 { 376 compatible = "mediatek,mt8173-efuse"; 377 reg = <0 0x10206000 0 0x1000>; 378 }; 379 380 apmixedsys: clock-controller@10209000 { 381 compatible = "mediatek,mt8173-apmixedsys"; 382 reg = <0 0x10209000 0 0x1000>; 383 #clock-cells = <1>; 384 }; 385 386 mipi_tx0: mipi-dphy@10215000 { 387 compatible = "mediatek,mt8173-mipi-tx"; 388 reg = <0 0x10215000 0 0x1000>; 389 clocks = <&clk26m>; 390 clock-output-names = "mipi_tx0_pll"; 391 #clock-cells = <0>; 392 #phy-cells = <0>; 393 status = "disabled"; 394 }; 395 396 mipi_tx1: mipi-dphy@10216000 { 397 compatible = "mediatek,mt8173-mipi-tx"; 398 reg = <0 0x10216000 0 0x1000>; 399 clocks = <&clk26m>; 400 clock-output-names = "mipi_tx1_pll"; 401 #clock-cells = <0>; 402 #phy-cells = <0>; 403 status = "disabled"; 404 }; 405 406 gic: interrupt-controller@10220000 { 407 compatible = "arm,gic-400"; 408 #interrupt-cells = <3>; 409 interrupt-parent = <&gic>; 410 interrupt-controller; 411 reg = <0 0x10221000 0 0x1000>, 412 <0 0x10222000 0 0x2000>, 413 <0 0x10224000 0 0x2000>, 414 <0 0x10226000 0 0x2000>; 415 interrupts = <GIC_PPI 9 416 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 417 }; 418 419 auxadc: auxadc@11001000 { 420 compatible = "mediatek,mt8173-auxadc"; 421 reg = <0 0x11001000 0 0x1000>; 422 }; 423 424 uart0: serial@11002000 { 425 compatible = "mediatek,mt8173-uart", 426 "mediatek,mt6577-uart"; 427 reg = <0 0x11002000 0 0x400>; 428 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 429 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 430 clock-names = "baud", "bus"; 431 status = "disabled"; 432 }; 433 434 uart1: serial@11003000 { 435 compatible = "mediatek,mt8173-uart", 436 "mediatek,mt6577-uart"; 437 reg = <0 0x11003000 0 0x400>; 438 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 439 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 440 clock-names = "baud", "bus"; 441 status = "disabled"; 442 }; 443 444 uart2: serial@11004000 { 445 compatible = "mediatek,mt8173-uart", 446 "mediatek,mt6577-uart"; 447 reg = <0 0x11004000 0 0x400>; 448 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 449 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 450 clock-names = "baud", "bus"; 451 status = "disabled"; 452 }; 453 454 uart3: serial@11005000 { 455 compatible = "mediatek,mt8173-uart", 456 "mediatek,mt6577-uart"; 457 reg = <0 0x11005000 0 0x400>; 458 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 459 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 460 clock-names = "baud", "bus"; 461 status = "disabled"; 462 }; 463 464 i2c0: i2c@11007000 { 465 compatible = "mediatek,mt8173-i2c"; 466 reg = <0 0x11007000 0 0x70>, 467 <0 0x11000100 0 0x80>; 468 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 469 clock-div = <16>; 470 clocks = <&pericfg CLK_PERI_I2C0>, 471 <&pericfg CLK_PERI_AP_DMA>; 472 clock-names = "main", "dma"; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&i2c0_pins_a>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 status = "disabled"; 478 }; 479 480 i2c1: i2c@11008000 { 481 compatible = "mediatek,mt8173-i2c"; 482 reg = <0 0x11008000 0 0x70>, 483 <0 0x11000180 0 0x80>; 484 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 485 clock-div = <16>; 486 clocks = <&pericfg CLK_PERI_I2C1>, 487 <&pericfg CLK_PERI_AP_DMA>; 488 clock-names = "main", "dma"; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&i2c1_pins_a>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 status = "disabled"; 494 }; 495 496 i2c2: i2c@11009000 { 497 compatible = "mediatek,mt8173-i2c"; 498 reg = <0 0x11009000 0 0x70>, 499 <0 0x11000200 0 0x80>; 500 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 501 clock-div = <16>; 502 clocks = <&pericfg CLK_PERI_I2C2>, 503 <&pericfg CLK_PERI_AP_DMA>; 504 clock-names = "main", "dma"; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&i2c2_pins_a>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 status = "disabled"; 510 }; 511 512 spi: spi@1100a000 { 513 compatible = "mediatek,mt8173-spi"; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 reg = <0 0x1100a000 0 0x1000>; 517 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 518 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 519 <&topckgen CLK_TOP_SPI_SEL>, 520 <&pericfg CLK_PERI_SPI0>; 521 clock-names = "parent-clk", "sel-clk", "spi-clk"; 522 status = "disabled"; 523 }; 524 525 thermal: thermal@1100b000 { 526 #thermal-sensor-cells = <0>; 527 compatible = "mediatek,mt8173-thermal"; 528 reg = <0 0x1100b000 0 0x1000>; 529 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 530 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 531 clock-names = "therm", "auxadc"; 532 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 533 mediatek,auxadc = <&auxadc>; 534 mediatek,apmixedsys = <&apmixedsys>; 535 }; 536 537 nor_flash: spi@1100d000 { 538 compatible = "mediatek,mt8173-nor"; 539 reg = <0 0x1100d000 0 0xe0>; 540 clocks = <&pericfg CLK_PERI_SPI>, 541 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 542 clock-names = "spi", "sf"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 status = "disabled"; 546 }; 547 548 i2c3: i2c@11010000 { 549 compatible = "mediatek,mt8173-i2c"; 550 reg = <0 0x11010000 0 0x70>, 551 <0 0x11000280 0 0x80>; 552 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 553 clock-div = <16>; 554 clocks = <&pericfg CLK_PERI_I2C3>, 555 <&pericfg CLK_PERI_AP_DMA>; 556 clock-names = "main", "dma"; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&i2c3_pins_a>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 status = "disabled"; 562 }; 563 564 i2c4: i2c@11011000 { 565 compatible = "mediatek,mt8173-i2c"; 566 reg = <0 0x11011000 0 0x70>, 567 <0 0x11000300 0 0x80>; 568 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 569 clock-div = <16>; 570 clocks = <&pericfg CLK_PERI_I2C4>, 571 <&pericfg CLK_PERI_AP_DMA>; 572 clock-names = "main", "dma"; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&i2c4_pins_a>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 i2c6: i2c@11013000 { 581 compatible = "mediatek,mt8173-i2c"; 582 reg = <0 0x11013000 0 0x70>, 583 <0 0x11000080 0 0x80>; 584 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 585 clock-div = <16>; 586 clocks = <&pericfg CLK_PERI_I2C6>, 587 <&pericfg CLK_PERI_AP_DMA>; 588 clock-names = "main", "dma"; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&i2c6_pins_a>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 status = "disabled"; 594 }; 595 596 afe: audio-controller@11220000 { 597 compatible = "mediatek,mt8173-afe-pcm"; 598 reg = <0 0x11220000 0 0x1000>; 599 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 600 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 601 clocks = <&infracfg CLK_INFRA_AUDIO>, 602 <&topckgen CLK_TOP_AUDIO_SEL>, 603 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 604 <&topckgen CLK_TOP_APLL1_DIV0>, 605 <&topckgen CLK_TOP_APLL2_DIV0>, 606 <&topckgen CLK_TOP_I2S0_M_SEL>, 607 <&topckgen CLK_TOP_I2S1_M_SEL>, 608 <&topckgen CLK_TOP_I2S2_M_SEL>, 609 <&topckgen CLK_TOP_I2S3_M_SEL>, 610 <&topckgen CLK_TOP_I2S3_B_SEL>; 611 clock-names = "infra_sys_audio_clk", 612 "top_pdn_audio", 613 "top_pdn_aud_intbus", 614 "bck0", 615 "bck1", 616 "i2s0_m", 617 "i2s1_m", 618 "i2s2_m", 619 "i2s3_m", 620 "i2s3_b"; 621 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 622 <&topckgen CLK_TOP_AUD_2_SEL>; 623 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 624 <&topckgen CLK_TOP_APLL2>; 625 }; 626 627 mmc0: mmc@11230000 { 628 compatible = "mediatek,mt8173-mmc", 629 "mediatek,mt8135-mmc"; 630 reg = <0 0x11230000 0 0x1000>; 631 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 632 clocks = <&pericfg CLK_PERI_MSDC30_0>, 633 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 634 clock-names = "source", "hclk"; 635 status = "disabled"; 636 }; 637 638 mmc1: mmc@11240000 { 639 compatible = "mediatek,mt8173-mmc", 640 "mediatek,mt8135-mmc"; 641 reg = <0 0x11240000 0 0x1000>; 642 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 643 clocks = <&pericfg CLK_PERI_MSDC30_1>, 644 <&topckgen CLK_TOP_AXI_SEL>; 645 clock-names = "source", "hclk"; 646 status = "disabled"; 647 }; 648 649 mmc2: mmc@11250000 { 650 compatible = "mediatek,mt8173-mmc", 651 "mediatek,mt8135-mmc"; 652 reg = <0 0x11250000 0 0x1000>; 653 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 654 clocks = <&pericfg CLK_PERI_MSDC30_2>, 655 <&topckgen CLK_TOP_AXI_SEL>; 656 clock-names = "source", "hclk"; 657 status = "disabled"; 658 }; 659 660 mmc3: mmc@11260000 { 661 compatible = "mediatek,mt8173-mmc", 662 "mediatek,mt8135-mmc"; 663 reg = <0 0x11260000 0 0x1000>; 664 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 665 clocks = <&pericfg CLK_PERI_MSDC30_3>, 666 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 667 clock-names = "source", "hclk"; 668 status = "disabled"; 669 }; 670 671 usb30: usb@11270000 { 672 compatible = "mediatek,mt8173-xhci"; 673 reg = <0 0x11270000 0 0x1000>, 674 <0 0x11280700 0 0x0100>; 675 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 676 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 677 clocks = <&topckgen CLK_TOP_USB30_SEL>, 678 <&pericfg CLK_PERI_USB0>, 679 <&pericfg CLK_PERI_USB1>; 680 clock-names = "sys_ck", 681 "wakeup_deb_p0", 682 "wakeup_deb_p1"; 683 phys = <&phy_port0 PHY_TYPE_USB3>, 684 <&phy_port1 PHY_TYPE_USB2>; 685 mediatek,syscon-wakeup = <&pericfg>; 686 status = "okay"; 687 }; 688 689 u3phy: usb-phy@11290000 { 690 compatible = "mediatek,mt8173-u3phy"; 691 reg = <0 0x11290000 0 0x800>; 692 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 693 clock-names = "u3phya_ref"; 694 #address-cells = <2>; 695 #size-cells = <2>; 696 ranges; 697 status = "okay"; 698 699 phy_port0: port@11290800 { 700 reg = <0 0x11290800 0 0x800>; 701 #phy-cells = <1>; 702 status = "okay"; 703 }; 704 705 phy_port1: port@11291000 { 706 reg = <0 0x11291000 0 0x800>; 707 #phy-cells = <1>; 708 status = "okay"; 709 }; 710 }; 711 712 mmsys: clock-controller@14000000 { 713 compatible = "mediatek,mt8173-mmsys", "syscon"; 714 reg = <0 0x14000000 0 0x1000>; 715 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 716 #clock-cells = <1>; 717 }; 718 719 ovl0: ovl@1400c000 { 720 compatible = "mediatek,mt8173-disp-ovl"; 721 reg = <0 0x1400c000 0 0x1000>; 722 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 723 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 724 clocks = <&mmsys CLK_MM_DISP_OVL0>; 725 iommus = <&iommu M4U_PORT_DISP_OVL0>; 726 mediatek,larb = <&larb0>; 727 }; 728 729 ovl1: ovl@1400d000 { 730 compatible = "mediatek,mt8173-disp-ovl"; 731 reg = <0 0x1400d000 0 0x1000>; 732 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 733 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 734 clocks = <&mmsys CLK_MM_DISP_OVL1>; 735 iommus = <&iommu M4U_PORT_DISP_OVL1>; 736 mediatek,larb = <&larb4>; 737 }; 738 739 rdma0: rdma@1400e000 { 740 compatible = "mediatek,mt8173-disp-rdma"; 741 reg = <0 0x1400e000 0 0x1000>; 742 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 743 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 744 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 745 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 746 mediatek,larb = <&larb0>; 747 }; 748 749 rdma1: rdma@1400f000 { 750 compatible = "mediatek,mt8173-disp-rdma"; 751 reg = <0 0x1400f000 0 0x1000>; 752 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 753 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 754 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 755 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 756 mediatek,larb = <&larb4>; 757 }; 758 759 rdma2: rdma@14010000 { 760 compatible = "mediatek,mt8173-disp-rdma"; 761 reg = <0 0x14010000 0 0x1000>; 762 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 763 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 764 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 765 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 766 mediatek,larb = <&larb4>; 767 }; 768 769 wdma0: wdma@14011000 { 770 compatible = "mediatek,mt8173-disp-wdma"; 771 reg = <0 0x14011000 0 0x1000>; 772 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 773 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 774 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 775 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 776 mediatek,larb = <&larb0>; 777 }; 778 779 wdma1: wdma@14012000 { 780 compatible = "mediatek,mt8173-disp-wdma"; 781 reg = <0 0x14012000 0 0x1000>; 782 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 783 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 784 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 785 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 786 mediatek,larb = <&larb4>; 787 }; 788 789 color0: color@14013000 { 790 compatible = "mediatek,mt8173-disp-color"; 791 reg = <0 0x14013000 0 0x1000>; 792 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 793 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 794 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 795 }; 796 797 color1: color@14014000 { 798 compatible = "mediatek,mt8173-disp-color"; 799 reg = <0 0x14014000 0 0x1000>; 800 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 801 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 802 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 803 }; 804 805 aal@14015000 { 806 compatible = "mediatek,mt8173-disp-aal"; 807 reg = <0 0x14015000 0 0x1000>; 808 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 809 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 810 clocks = <&mmsys CLK_MM_DISP_AAL>; 811 }; 812 813 gamma@14016000 { 814 compatible = "mediatek,mt8173-disp-gamma"; 815 reg = <0 0x14016000 0 0x1000>; 816 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 817 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 818 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 819 }; 820 821 merge@14017000 { 822 compatible = "mediatek,mt8173-disp-merge"; 823 reg = <0 0x14017000 0 0x1000>; 824 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 825 clocks = <&mmsys CLK_MM_DISP_MERGE>; 826 }; 827 828 split0: split@14018000 { 829 compatible = "mediatek,mt8173-disp-split"; 830 reg = <0 0x14018000 0 0x1000>; 831 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 832 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 833 }; 834 835 split1: split@14019000 { 836 compatible = "mediatek,mt8173-disp-split"; 837 reg = <0 0x14019000 0 0x1000>; 838 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 839 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 840 }; 841 842 ufoe@1401a000 { 843 compatible = "mediatek,mt8173-disp-ufoe"; 844 reg = <0 0x1401a000 0 0x1000>; 845 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 846 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 847 clocks = <&mmsys CLK_MM_DISP_UFOE>; 848 }; 849 850 dsi0: dsi@1401b000 { 851 compatible = "mediatek,mt8173-dsi"; 852 reg = <0 0x1401b000 0 0x1000>; 853 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 854 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 855 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 856 <&mmsys CLK_MM_DSI0_DIGITAL>, 857 <&mipi_tx0>; 858 clock-names = "engine", "digital", "hs"; 859 phys = <&mipi_tx0>; 860 phy-names = "dphy"; 861 status = "disabled"; 862 }; 863 864 dsi1: dsi@1401c000 { 865 compatible = "mediatek,mt8173-dsi"; 866 reg = <0 0x1401c000 0 0x1000>; 867 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 868 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 869 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 870 <&mmsys CLK_MM_DSI1_DIGITAL>, 871 <&mipi_tx1>; 872 clock-names = "engine", "digital", "hs"; 873 phy = <&mipi_tx1>; 874 phy-names = "dphy"; 875 status = "disabled"; 876 }; 877 878 dpi0: dpi@1401d000 { 879 compatible = "mediatek,mt8173-dpi"; 880 reg = <0 0x1401d000 0 0x1000>; 881 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 882 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 883 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 884 <&mmsys CLK_MM_DPI_ENGINE>, 885 <&apmixedsys CLK_APMIXED_TVDPLL>; 886 clock-names = "pixel", "engine", "pll"; 887 status = "disabled"; 888 }; 889 890 pwm0: pwm@1401e000 { 891 compatible = "mediatek,mt8173-disp-pwm", 892 "mediatek,mt6595-disp-pwm"; 893 reg = <0 0x1401e000 0 0x1000>; 894 #pwm-cells = <2>; 895 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 896 <&mmsys CLK_MM_DISP_PWM0MM>; 897 clock-names = "main", "mm"; 898 status = "disabled"; 899 }; 900 901 pwm1: pwm@1401f000 { 902 compatible = "mediatek,mt8173-disp-pwm", 903 "mediatek,mt6595-disp-pwm"; 904 reg = <0 0x1401f000 0 0x1000>; 905 #pwm-cells = <2>; 906 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 907 <&mmsys CLK_MM_DISP_PWM1MM>; 908 clock-names = "main", "mm"; 909 status = "disabled"; 910 }; 911 912 mutex: mutex@14020000 { 913 compatible = "mediatek,mt8173-disp-mutex"; 914 reg = <0 0x14020000 0 0x1000>; 915 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 916 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 917 clocks = <&mmsys CLK_MM_MUTEX_32K>; 918 }; 919 920 larb0: larb@14021000 { 921 compatible = "mediatek,mt8173-smi-larb"; 922 reg = <0 0x14021000 0 0x1000>; 923 mediatek,smi = <&smi_common>; 924 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 925 clocks = <&mmsys CLK_MM_SMI_LARB0>, 926 <&mmsys CLK_MM_SMI_LARB0>; 927 clock-names = "apb", "smi"; 928 }; 929 930 smi_common: smi@14022000 { 931 compatible = "mediatek,mt8173-smi-common"; 932 reg = <0 0x14022000 0 0x1000>; 933 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 934 clocks = <&mmsys CLK_MM_SMI_COMMON>, 935 <&mmsys CLK_MM_SMI_COMMON>; 936 clock-names = "apb", "smi"; 937 }; 938 939 od@14023000 { 940 compatible = "mediatek,mt8173-disp-od"; 941 reg = <0 0x14023000 0 0x1000>; 942 clocks = <&mmsys CLK_MM_DISP_OD>; 943 }; 944 945 larb4: larb@14027000 { 946 compatible = "mediatek,mt8173-smi-larb"; 947 reg = <0 0x14027000 0 0x1000>; 948 mediatek,smi = <&smi_common>; 949 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 950 clocks = <&mmsys CLK_MM_SMI_LARB4>, 951 <&mmsys CLK_MM_SMI_LARB4>; 952 clock-names = "apb", "smi"; 953 }; 954 955 imgsys: clock-controller@15000000 { 956 compatible = "mediatek,mt8173-imgsys", "syscon"; 957 reg = <0 0x15000000 0 0x1000>; 958 #clock-cells = <1>; 959 }; 960 961 larb2: larb@15001000 { 962 compatible = "mediatek,mt8173-smi-larb"; 963 reg = <0 0x15001000 0 0x1000>; 964 mediatek,smi = <&smi_common>; 965 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 966 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 967 <&imgsys CLK_IMG_LARB2_SMI>; 968 clock-names = "apb", "smi"; 969 }; 970 971 vdecsys: clock-controller@16000000 { 972 compatible = "mediatek,mt8173-vdecsys", "syscon"; 973 reg = <0 0x16000000 0 0x1000>; 974 #clock-cells = <1>; 975 }; 976 977 larb1: larb@16010000 { 978 compatible = "mediatek,mt8173-smi-larb"; 979 reg = <0 0x16010000 0 0x1000>; 980 mediatek,smi = <&smi_common>; 981 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 982 clocks = <&vdecsys CLK_VDEC_CKEN>, 983 <&vdecsys CLK_VDEC_LARB_CKEN>; 984 clock-names = "apb", "smi"; 985 }; 986 987 vencsys: clock-controller@18000000 { 988 compatible = "mediatek,mt8173-vencsys", "syscon"; 989 reg = <0 0x18000000 0 0x1000>; 990 #clock-cells = <1>; 991 }; 992 993 larb3: larb@18001000 { 994 compatible = "mediatek,mt8173-smi-larb"; 995 reg = <0 0x18001000 0 0x1000>; 996 mediatek,smi = <&smi_common>; 997 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 998 clocks = <&vencsys CLK_VENC_CKE1>, 999 <&vencsys CLK_VENC_CKE0>; 1000 clock-names = "apb", "smi"; 1001 }; 1002 1003 vcodec_enc: vcodec@18002000 { 1004 compatible = "mediatek,mt8173-vcodec-enc"; 1005 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1006 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1007 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1008 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1009 mediatek,larb = <&larb3>, 1010 <&larb5>; 1011 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1012 <&iommu M4U_PORT_VENC_REC>, 1013 <&iommu M4U_PORT_VENC_BSDMA>, 1014 <&iommu M4U_PORT_VENC_SV_COMV>, 1015 <&iommu M4U_PORT_VENC_RD_COMV>, 1016 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1017 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1018 <&iommu M4U_PORT_VENC_REF_LUMA>, 1019 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1020 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1021 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1022 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1023 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1024 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1025 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1026 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1027 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1028 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1029 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1030 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1031 mediatek,vpu = <&vpu>; 1032 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1033 <&topckgen CLK_TOP_VENC_SEL>, 1034 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1035 <&topckgen CLK_TOP_VENC_LT_SEL>; 1036 clock-names = "venc_sel_src", 1037 "venc_sel", 1038 "venc_lt_sel_src", 1039 "venc_lt_sel"; 1040 }; 1041 1042 vencltsys: clock-controller@19000000 { 1043 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1044 reg = <0 0x19000000 0 0x1000>; 1045 #clock-cells = <1>; 1046 }; 1047 1048 larb5: larb@19001000 { 1049 compatible = "mediatek,mt8173-smi-larb"; 1050 reg = <0 0x19001000 0 0x1000>; 1051 mediatek,smi = <&smi_common>; 1052 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1053 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1054 <&vencltsys CLK_VENCLT_CKE0>; 1055 clock-names = "apb", "smi"; 1056 }; 1057 }; 1058}; 1059 1060