1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	interrupt-parent = <&gic>;
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	system_clk: dummy40m {
16		compatible = "fixed-clock";
17		clock-frequency = <40000000>;
18		#clock-cells = <0>;
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24		cpu0: cpu@0 {
25			device_type = "cpu";
26			compatible = "arm,cortex-a53";
27			enable-method = "psci";
28			reg = <0x0>;
29			#cooling-cells = <2>;
30		};
31
32		cpu1: cpu@1 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a53";
35			enable-method = "psci";
36			reg = <0x1>;
37			#cooling-cells = <2>;
38		};
39
40		cpu2: cpu@2 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a53";
43			enable-method = "psci";
44			reg = <0x2>;
45			#cooling-cells = <2>;
46		};
47
48		cpu3: cpu@3 {
49			device_type = "cpu";
50			enable-method = "psci";
51			compatible = "arm,cortex-a53";
52			reg = <0x3>;
53			#cooling-cells = <2>;
54		};
55	};
56
57	psci {
58		compatible  = "arm,psci-0.2";
59		method      = "smc";
60	};
61
62	reserved-memory {
63		#address-cells = <2>;
64		#size-cells = <2>;
65		ranges;
66		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
67		secmon_reserved: secmon@43000000 {
68			reg = <0 0x43000000 0 0x30000>;
69			no-map;
70		};
71	};
72
73	timer {
74		compatible = "arm,armv8-timer";
75		interrupt-parent = <&gic>;
76		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
77			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
78			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
79			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
80	};
81
82	soc {
83		#address-cells = <2>;
84		#size-cells = <2>;
85		compatible = "simple-bus";
86		ranges;
87
88		gic: interrupt-controller@c000000 {
89			compatible = "arm,gic-v3";
90			#interrupt-cells = <3>;
91			interrupt-parent = <&gic>;
92			interrupt-controller;
93			reg = <0 0x0c000000 0 0x10000>,  /* GICD */
94			      <0 0x0c080000 0 0x80000>,  /* GICR */
95			      <0 0x0c400000 0 0x2000>,   /* GICC */
96			      <0 0x0c410000 0 0x1000>,   /* GICH */
97			      <0 0x0c420000 0 0x2000>;   /* GICV */
98			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
99		};
100
101		watchdog: watchdog@1001c000 {
102			compatible = "mediatek,mt7986-wdt",
103				     "mediatek,mt6589-wdt";
104			reg = <0 0x1001c000 0 0x1000>;
105			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
106			#reset-cells = <1>;
107			status = "disabled";
108		};
109
110		pio: pinctrl@1001f000 {
111			compatible = "mediatek,mt7986a-pinctrl";
112			reg = <0 0x1001f000 0 0x1000>,
113			      <0 0x11c30000 0 0x1000>,
114			      <0 0x11c40000 0 0x1000>,
115			      <0 0x11e20000 0 0x1000>,
116			      <0 0x11e30000 0 0x1000>,
117			      <0 0x11f00000 0 0x1000>,
118			      <0 0x11f10000 0 0x1000>,
119			      <0 0x1000b000 0 0x1000>;
120			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
121				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
122			gpio-controller;
123			#gpio-cells = <2>;
124			gpio-ranges = <&pio 0 0 100>;
125			interrupt-controller;
126			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
127			interrupt-parent = <&gic>;
128			#interrupt-cells = <2>;
129		};
130
131		trng: trng@1020f000 {
132			compatible = "mediatek,mt7986-rng",
133				     "mediatek,mt7623-rng";
134			reg = <0 0x1020f000 0 0x100>;
135			clocks = <&system_clk>;
136			clock-names = "rng";
137			status = "disabled";
138		};
139
140		uart0: serial@11002000 {
141			compatible = "mediatek,mt7986-uart",
142				     "mediatek,mt6577-uart";
143			reg = <0 0x11002000 0 0x400>;
144			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
145			clocks = <&system_clk>;
146			status = "disabled";
147		};
148
149		uart1: serial@11003000 {
150			compatible = "mediatek,mt7986-uart",
151				     "mediatek,mt6577-uart";
152			reg = <0 0x11003000 0 0x400>;
153			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
154			clocks = <&system_clk>;
155			status = "disabled";
156		};
157
158		uart2: serial@11004000 {
159			compatible = "mediatek,mt7986-uart",
160				     "mediatek,mt6577-uart";
161			reg = <0 0x11004000 0 0x400>;
162			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
163			clocks = <&system_clk>;
164			status = "disabled";
165		};
166
167	};
168
169};
170