1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mt7986-clk.h>
10#include <dt-bindings/reset/mt7986-resets.h>
11
12/ {
13	compatible = "mediatek,mt7986a";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	clk40m: oscillator-40m {
19		compatible = "fixed-clock";
20		clock-frequency = <40000000>;
21		#clock-cells = <0>;
22		clock-output-names = "clkxtal";
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28		cpu0: cpu@0 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a53";
31			enable-method = "psci";
32			reg = <0x0>;
33			#cooling-cells = <2>;
34		};
35
36		cpu1: cpu@1 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a53";
39			enable-method = "psci";
40			reg = <0x1>;
41			#cooling-cells = <2>;
42		};
43
44		cpu2: cpu@2 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a53";
47			enable-method = "psci";
48			reg = <0x2>;
49			#cooling-cells = <2>;
50		};
51
52		cpu3: cpu@3 {
53			device_type = "cpu";
54			enable-method = "psci";
55			compatible = "arm,cortex-a53";
56			reg = <0x3>;
57			#cooling-cells = <2>;
58		};
59	};
60
61	psci {
62		compatible = "arm,psci-0.2";
63		method = "smc";
64	};
65
66	reserved-memory {
67		#address-cells = <2>;
68		#size-cells = <2>;
69		ranges;
70		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
71		secmon_reserved: secmon@43000000 {
72			reg = <0 0x43000000 0 0x30000>;
73			no-map;
74		};
75
76		wmcpu_emi: wmcpu-reserved@4fc00000 {
77			no-map;
78			reg = <0 0x4fc00000 0 0x00100000>;
79		};
80
81		wo_emi0: wo-emi@4fd00000 {
82			reg = <0 0x4fd00000 0 0x40000>;
83			no-map;
84		};
85
86		wo_emi1: wo-emi@4fd40000 {
87			reg = <0 0x4fd40000 0 0x40000>;
88			no-map;
89		};
90
91		wo_ilm0: wo-ilm@151e0000 {
92			reg = <0 0x151e0000 0 0x8000>;
93			no-map;
94		};
95
96		wo_ilm1: wo-ilm@151f0000 {
97			reg = <0 0x151f0000 0 0x8000>;
98			no-map;
99		};
100
101		wo_data: wo-data@4fd80000 {
102			reg = <0 0x4fd80000 0 0x240000>;
103			no-map;
104		};
105
106		wo_dlm0: wo-dlm@151e8000 {
107			reg = <0 0x151e8000 0 0x2000>;
108			no-map;
109		};
110
111		wo_dlm1: wo-dlm@151f8000 {
112			reg = <0 0x151f8000 0 0x2000>;
113			no-map;
114		};
115
116		wo_boot: wo-boot@15194000 {
117			reg = <0 0x15194000 0 0x1000>;
118			no-map;
119		};
120
121	};
122
123	timer {
124		compatible = "arm,armv8-timer";
125		interrupt-parent = <&gic>;
126		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
127			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
128			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
129			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
130	};
131
132	soc {
133		#address-cells = <2>;
134		#size-cells = <2>;
135		compatible = "simple-bus";
136		ranges;
137
138		gic: interrupt-controller@c000000 {
139			compatible = "arm,gic-v3";
140			#interrupt-cells = <3>;
141			interrupt-parent = <&gic>;
142			interrupt-controller;
143			reg = <0 0x0c000000 0 0x10000>,  /* GICD */
144			      <0 0x0c080000 0 0x80000>,  /* GICR */
145			      <0 0x0c400000 0 0x2000>,   /* GICC */
146			      <0 0x0c410000 0 0x1000>,   /* GICH */
147			      <0 0x0c420000 0 0x2000>;   /* GICV */
148			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
149		};
150
151		infracfg: infracfg@10001000 {
152			compatible = "mediatek,mt7986-infracfg", "syscon";
153			reg = <0 0x10001000 0 0x1000>;
154			#clock-cells = <1>;
155		};
156
157		wed_pcie: wed-pcie@10003000 {
158			compatible = "mediatek,mt7986-wed-pcie",
159				     "syscon";
160			reg = <0 0x10003000 0 0x10>;
161		};
162
163		topckgen: topckgen@1001b000 {
164			compatible = "mediatek,mt7986-topckgen", "syscon";
165			reg = <0 0x1001B000 0 0x1000>;
166			#clock-cells = <1>;
167		};
168
169		watchdog: watchdog@1001c000 {
170			compatible = "mediatek,mt7986-wdt",
171				     "mediatek,mt6589-wdt";
172			reg = <0 0x1001c000 0 0x1000>;
173			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
174			#reset-cells = <1>;
175			status = "disabled";
176		};
177
178		apmixedsys: apmixedsys@1001e000 {
179			compatible = "mediatek,mt7986-apmixedsys";
180			reg = <0 0x1001E000 0 0x1000>;
181			#clock-cells = <1>;
182		};
183
184		pio: pinctrl@1001f000 {
185			compatible = "mediatek,mt7986a-pinctrl";
186			reg = <0 0x1001f000 0 0x1000>,
187			      <0 0x11c30000 0 0x1000>,
188			      <0 0x11c40000 0 0x1000>,
189			      <0 0x11e20000 0 0x1000>,
190			      <0 0x11e30000 0 0x1000>,
191			      <0 0x11f00000 0 0x1000>,
192			      <0 0x11f10000 0 0x1000>,
193			      <0 0x1000b000 0 0x1000>;
194			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
195				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
196			gpio-controller;
197			#gpio-cells = <2>;
198			gpio-ranges = <&pio 0 0 100>;
199			interrupt-controller;
200			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
201			interrupt-parent = <&gic>;
202			#interrupt-cells = <2>;
203		};
204
205		sgmiisys0: syscon@10060000 {
206			compatible = "mediatek,mt7986-sgmiisys_0",
207				     "syscon";
208			reg = <0 0x10060000 0 0x1000>;
209			#clock-cells = <1>;
210		};
211
212		sgmiisys1: syscon@10070000 {
213			compatible = "mediatek,mt7986-sgmiisys_1",
214				     "syscon";
215			reg = <0 0x10070000 0 0x1000>;
216			#clock-cells = <1>;
217		};
218
219		trng: rng@1020f000 {
220			compatible = "mediatek,mt7986-rng",
221				     "mediatek,mt7623-rng";
222			reg = <0 0x1020f000 0 0x100>;
223			clocks = <&infracfg CLK_INFRA_TRNG_CK>;
224			clock-names = "rng";
225			status = "disabled";
226		};
227
228		crypto: crypto@10320000 {
229			compatible = "inside-secure,safexcel-eip97";
230			reg = <0 0x10320000 0 0x40000>;
231			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
232				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
233				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
234				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
235			interrupt-names = "ring0", "ring1", "ring2", "ring3";
236			clocks = <&infracfg CLK_INFRA_EIP97_CK>;
237			clock-names = "infra_eip97_ck";
238			assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
239			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
240			status = "disabled";
241		};
242
243		uart0: serial@11002000 {
244			compatible = "mediatek,mt7986-uart",
245				     "mediatek,mt6577-uart";
246			reg = <0 0x11002000 0 0x400>;
247			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
248			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
249				 <&infracfg CLK_INFRA_UART0_CK>;
250			clock-names = "baud", "bus";
251			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
252					  <&infracfg CLK_INFRA_UART0_SEL>;
253			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
254						 <&topckgen CLK_TOP_UART_SEL>;
255			status = "disabled";
256		};
257
258		uart1: serial@11003000 {
259			compatible = "mediatek,mt7986-uart",
260				     "mediatek,mt6577-uart";
261			reg = <0 0x11003000 0 0x400>;
262			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
263			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
264				 <&infracfg CLK_INFRA_UART1_CK>;
265			clock-names = "baud", "bus";
266			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
267			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
268			status = "disabled";
269		};
270
271		uart2: serial@11004000 {
272			compatible = "mediatek,mt7986-uart",
273				     "mediatek,mt6577-uart";
274			reg = <0 0x11004000 0 0x400>;
275			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
276			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
277				 <&infracfg CLK_INFRA_UART2_CK>;
278			clock-names = "baud", "bus";
279			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
280			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
281			status = "disabled";
282		};
283
284		i2c0: i2c@11008000 {
285			compatible = "mediatek,mt7986-i2c";
286			reg = <0 0x11008000 0 0x90>,
287			      <0 0x10217080 0 0x80>;
288			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
289			clock-div = <5>;
290			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
291				 <&infracfg CLK_INFRA_AP_DMA_CK>;
292			clock-names = "main", "dma";
293			#address-cells = <1>;
294			#size-cells = <0>;
295			status = "disabled";
296		};
297
298		spi0: spi@1100a000 {
299			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
300			#address-cells = <1>;
301			#size-cells = <0>;
302			reg = <0 0x1100a000 0 0x100>;
303			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
304			clocks = <&topckgen CLK_TOP_MPLL_D2>,
305				 <&topckgen CLK_TOP_SPI_SEL>,
306				 <&infracfg CLK_INFRA_SPI0_CK>,
307				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
308			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
309			status = "disabled";
310		};
311
312		spi1: spi@1100b000 {
313			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
314			#address-cells = <1>;
315			#size-cells = <0>;
316			reg = <0 0x1100b000 0 0x100>;
317			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
318			clocks = <&topckgen CLK_TOP_MPLL_D2>,
319				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
320				 <&infracfg CLK_INFRA_SPI1_CK>,
321				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
322			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
323			status = "disabled";
324		};
325
326		ethsys: syscon@15000000 {
327			 #address-cells = <1>;
328			 #size-cells = <1>;
329			 compatible = "mediatek,mt7986-ethsys",
330				      "syscon";
331			 reg = <0 0x15000000 0 0x1000>;
332			 #clock-cells = <1>;
333			 #reset-cells = <1>;
334		};
335
336		wed0: wed@15010000 {
337			compatible = "mediatek,mt7986-wed",
338				     "syscon";
339			reg = <0 0x15010000 0 0x1000>;
340			interrupt-parent = <&gic>;
341			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
342			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
343					<&wo_data>, <&wo_boot>;
344			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
345					      "wo-data", "wo-boot";
346			mediatek,wo-ccif = <&wo_ccif0>;
347		};
348
349		wed1: wed@15011000 {
350			compatible = "mediatek,mt7986-wed",
351				     "syscon";
352			reg = <0 0x15011000 0 0x1000>;
353			interrupt-parent = <&gic>;
354			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
355			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
356					<&wo_data>, <&wo_boot>;
357			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
358					      "wo-data", "wo-boot";
359			mediatek,wo-ccif = <&wo_ccif1>;
360		};
361
362		wo_ccif0: syscon@151a5000 {
363			compatible = "mediatek,mt7986-wo-ccif", "syscon";
364			reg = <0 0x151a5000 0 0x1000>;
365			interrupt-parent = <&gic>;
366			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
367		};
368
369		wo_ccif1: syscon@151ad000 {
370			compatible = "mediatek,mt7986-wo-ccif", "syscon";
371			reg = <0 0x151ad000 0 0x1000>;
372			interrupt-parent = <&gic>;
373			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
374		};
375
376		eth: ethernet@15100000 {
377			compatible = "mediatek,mt7986-eth";
378			reg = <0 0x15100000 0 0x80000>;
379			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
380				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
381				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
382				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
383			clocks = <&ethsys CLK_ETH_FE_EN>,
384				 <&ethsys CLK_ETH_GP2_EN>,
385				 <&ethsys CLK_ETH_GP1_EN>,
386				 <&ethsys CLK_ETH_WOCPU1_EN>,
387				 <&ethsys CLK_ETH_WOCPU0_EN>,
388				 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
389				 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
390				 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
391				 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
392				 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
393				 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
394				 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
395				 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
396				 <&topckgen CLK_TOP_NETSYS_SEL>,
397				 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
398			clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
399				      "sgmii_tx250m", "sgmii_rx250m",
400				      "sgmii_cdr_ref", "sgmii_cdr_fb",
401				      "sgmii2_tx250m", "sgmii2_rx250m",
402				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
403				      "netsys0", "netsys1";
404			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
405					  <&topckgen CLK_TOP_SGM_325M_SEL>;
406			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
407						 <&apmixedsys CLK_APMIXED_SGMPLL>;
408			mediatek,ethsys = <&ethsys>;
409			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
410			mediatek,wed-pcie = <&wed_pcie>;
411			mediatek,wed = <&wed0>, <&wed1>;
412			#reset-cells = <1>;
413			#address-cells = <1>;
414			#size-cells = <0>;
415			status = "disabled";
416		};
417
418		wifi: wifi@18000000 {
419			compatible = "mediatek,mt7986-wmac";
420			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
421			reset-names = "consys";
422			clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
423				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
424			clock-names = "mcu", "ap2conn";
425			reg = <0 0x18000000 0 0x1000000>,
426			      <0 0x10003000 0 0x1000>,
427			      <0 0x11d10000 0 0x1000>;
428			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
429				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
430				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
431				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
432			memory-region = <&wmcpu_emi>;
433		};
434	};
435
436};
437