1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 * Author: Sam.Shih <sam.shih@mediatek.com> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/mt7986-clk.h> 10#include <dt-bindings/reset/mt7986-resets.h> 11#include <dt-bindings/phy/phy.h> 12 13/ { 14 compatible = "mediatek,mt7986a"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clk40m: oscillator-40m { 20 compatible = "fixed-clock"; 21 clock-frequency = <40000000>; 22 #clock-cells = <0>; 23 clock-output-names = "clkxtal"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 enable-method = "psci"; 33 reg = <0x0>; 34 #cooling-cells = <2>; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 enable-method = "psci"; 41 reg = <0x1>; 42 #cooling-cells = <2>; 43 }; 44 45 cpu2: cpu@2 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 enable-method = "psci"; 49 reg = <0x2>; 50 #cooling-cells = <2>; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 enable-method = "psci"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x3>; 58 #cooling-cells = <2>; 59 }; 60 }; 61 62 psci { 63 compatible = "arm,psci-0.2"; 64 method = "smc"; 65 }; 66 67 reserved-memory { 68 #address-cells = <2>; 69 #size-cells = <2>; 70 ranges; 71 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 72 secmon_reserved: secmon@43000000 { 73 reg = <0 0x43000000 0 0x30000>; 74 no-map; 75 }; 76 77 wmcpu_emi: wmcpu-reserved@4fc00000 { 78 no-map; 79 reg = <0 0x4fc00000 0 0x00100000>; 80 }; 81 82 wo_emi0: wo-emi@4fd00000 { 83 reg = <0 0x4fd00000 0 0x40000>; 84 no-map; 85 }; 86 87 wo_emi1: wo-emi@4fd40000 { 88 reg = <0 0x4fd40000 0 0x40000>; 89 no-map; 90 }; 91 92 wo_ilm0: wo-ilm@151e0000 { 93 reg = <0 0x151e0000 0 0x8000>; 94 no-map; 95 }; 96 97 wo_ilm1: wo-ilm@151f0000 { 98 reg = <0 0x151f0000 0 0x8000>; 99 no-map; 100 }; 101 102 wo_data: wo-data@4fd80000 { 103 reg = <0 0x4fd80000 0 0x240000>; 104 no-map; 105 }; 106 107 wo_dlm0: wo-dlm@151e8000 { 108 reg = <0 0x151e8000 0 0x2000>; 109 no-map; 110 }; 111 112 wo_dlm1: wo-dlm@151f8000 { 113 reg = <0 0x151f8000 0 0x2000>; 114 no-map; 115 }; 116 117 wo_boot: wo-boot@15194000 { 118 reg = <0 0x15194000 0 0x1000>; 119 no-map; 120 }; 121 122 }; 123 124 timer { 125 compatible = "arm,armv8-timer"; 126 interrupt-parent = <&gic>; 127 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 128 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 129 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 130 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 131 }; 132 133 soc { 134 #address-cells = <2>; 135 #size-cells = <2>; 136 compatible = "simple-bus"; 137 ranges; 138 139 gic: interrupt-controller@c000000 { 140 compatible = "arm,gic-v3"; 141 #interrupt-cells = <3>; 142 interrupt-parent = <&gic>; 143 interrupt-controller; 144 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 145 <0 0x0c080000 0 0x80000>, /* GICR */ 146 <0 0x0c400000 0 0x2000>, /* GICC */ 147 <0 0x0c410000 0 0x1000>, /* GICH */ 148 <0 0x0c420000 0 0x2000>; /* GICV */ 149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 150 }; 151 152 infracfg: infracfg@10001000 { 153 compatible = "mediatek,mt7986-infracfg", "syscon"; 154 reg = <0 0x10001000 0 0x1000>; 155 #clock-cells = <1>; 156 #reset-cells = <1>; 157 }; 158 159 wed_pcie: wed-pcie@10003000 { 160 compatible = "mediatek,mt7986-wed-pcie", 161 "syscon"; 162 reg = <0 0x10003000 0 0x10>; 163 }; 164 165 topckgen: topckgen@1001b000 { 166 compatible = "mediatek,mt7986-topckgen", "syscon"; 167 reg = <0 0x1001B000 0 0x1000>; 168 #clock-cells = <1>; 169 }; 170 171 watchdog: watchdog@1001c000 { 172 compatible = "mediatek,mt7986-wdt"; 173 reg = <0 0x1001c000 0 0x1000>; 174 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 175 #reset-cells = <1>; 176 status = "disabled"; 177 }; 178 179 apmixedsys: apmixedsys@1001e000 { 180 compatible = "mediatek,mt7986-apmixedsys"; 181 reg = <0 0x1001E000 0 0x1000>; 182 #clock-cells = <1>; 183 }; 184 185 pio: pinctrl@1001f000 { 186 compatible = "mediatek,mt7986a-pinctrl"; 187 reg = <0 0x1001f000 0 0x1000>, 188 <0 0x11c30000 0 0x1000>, 189 <0 0x11c40000 0 0x1000>, 190 <0 0x11e20000 0 0x1000>, 191 <0 0x11e30000 0 0x1000>, 192 <0 0x11f00000 0 0x1000>, 193 <0 0x11f10000 0 0x1000>, 194 <0 0x1000b000 0 0x1000>; 195 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", 196 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; 197 gpio-controller; 198 #gpio-cells = <2>; 199 gpio-ranges = <&pio 0 0 100>; 200 interrupt-controller; 201 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-parent = <&gic>; 203 #interrupt-cells = <2>; 204 }; 205 206 sgmiisys0: syscon@10060000 { 207 compatible = "mediatek,mt7986-sgmiisys_0", 208 "syscon"; 209 reg = <0 0x10060000 0 0x1000>; 210 #clock-cells = <1>; 211 }; 212 213 sgmiisys1: syscon@10070000 { 214 compatible = "mediatek,mt7986-sgmiisys_1", 215 "syscon"; 216 reg = <0 0x10070000 0 0x1000>; 217 #clock-cells = <1>; 218 }; 219 220 trng: rng@1020f000 { 221 compatible = "mediatek,mt7986-rng", 222 "mediatek,mt7623-rng"; 223 reg = <0 0x1020f000 0 0x100>; 224 clocks = <&infracfg CLK_INFRA_TRNG_CK>; 225 clock-names = "rng"; 226 status = "disabled"; 227 }; 228 229 crypto: crypto@10320000 { 230 compatible = "inside-secure,safexcel-eip97"; 231 reg = <0 0x10320000 0 0x40000>; 232 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-names = "ring0", "ring1", "ring2", "ring3"; 237 clocks = <&infracfg CLK_INFRA_EIP97_CK>; 238 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; 239 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; 240 status = "disabled"; 241 }; 242 243 pwm: pwm@10048000 { 244 compatible = "mediatek,mt7986-pwm"; 245 reg = <0 0x10048000 0 0x1000>; 246 #pwm-cells = <2>; 247 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&topckgen CLK_TOP_PWM_SEL>, 249 <&infracfg CLK_INFRA_PWM_STA>, 250 <&infracfg CLK_INFRA_PWM1_CK>, 251 <&infracfg CLK_INFRA_PWM2_CK>; 252 clock-names = "top", "main", "pwm1", "pwm2"; 253 status = "disabled"; 254 }; 255 256 uart0: serial@11002000 { 257 compatible = "mediatek,mt7986-uart", 258 "mediatek,mt6577-uart"; 259 reg = <0 0x11002000 0 0x400>; 260 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&infracfg CLK_INFRA_UART0_SEL>, 262 <&infracfg CLK_INFRA_UART0_CK>; 263 clock-names = "baud", "bus"; 264 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, 265 <&infracfg CLK_INFRA_UART0_SEL>; 266 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, 267 <&topckgen CLK_TOP_UART_SEL>; 268 status = "disabled"; 269 }; 270 271 uart1: serial@11003000 { 272 compatible = "mediatek,mt7986-uart", 273 "mediatek,mt6577-uart"; 274 reg = <0 0x11003000 0 0x400>; 275 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&infracfg CLK_INFRA_UART1_SEL>, 277 <&infracfg CLK_INFRA_UART1_CK>; 278 clock-names = "baud", "bus"; 279 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; 280 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; 281 status = "disabled"; 282 }; 283 284 uart2: serial@11004000 { 285 compatible = "mediatek,mt7986-uart", 286 "mediatek,mt6577-uart"; 287 reg = <0 0x11004000 0 0x400>; 288 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&infracfg CLK_INFRA_UART2_SEL>, 290 <&infracfg CLK_INFRA_UART2_CK>; 291 clock-names = "baud", "bus"; 292 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; 293 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; 294 status = "disabled"; 295 }; 296 297 i2c0: i2c@11008000 { 298 compatible = "mediatek,mt7986-i2c"; 299 reg = <0 0x11008000 0 0x90>, 300 <0 0x10217080 0 0x80>; 301 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 302 clock-div = <5>; 303 clocks = <&infracfg CLK_INFRA_I2C0_CK>, 304 <&infracfg CLK_INFRA_AP_DMA_CK>; 305 clock-names = "main", "dma"; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 311 spi0: spi@1100a000 { 312 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 reg = <0 0x1100a000 0 0x100>; 316 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&topckgen CLK_TOP_MPLL_D2>, 318 <&topckgen CLK_TOP_SPI_SEL>, 319 <&infracfg CLK_INFRA_SPI0_CK>, 320 <&infracfg CLK_INFRA_SPI0_HCK_CK>; 321 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 322 status = "disabled"; 323 }; 324 325 spi1: spi@1100b000 { 326 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 reg = <0 0x1100b000 0 0x100>; 330 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&topckgen CLK_TOP_MPLL_D2>, 332 <&topckgen CLK_TOP_SPIM_MST_SEL>, 333 <&infracfg CLK_INFRA_SPI1_CK>, 334 <&infracfg CLK_INFRA_SPI1_HCK_CK>; 335 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 336 status = "disabled"; 337 }; 338 339 auxadc: adc@1100d000 { 340 compatible = "mediatek,mt7986-auxadc"; 341 reg = <0 0x1100d000 0 0x1000>; 342 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; 343 clock-names = "main"; 344 #io-channel-cells = <1>; 345 status = "disabled"; 346 }; 347 348 ssusb: usb@11200000 { 349 compatible = "mediatek,mt7986-xhci", 350 "mediatek,mtk-xhci"; 351 reg = <0 0x11200000 0 0x2e00>, 352 <0 0x11203e00 0 0x0100>; 353 reg-names = "mac", "ippc"; 354 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, 356 <&infracfg CLK_INFRA_IUSB_CK>, 357 <&infracfg CLK_INFRA_IUSB_133_CK>, 358 <&infracfg CLK_INFRA_IUSB_66M_CK>, 359 <&topckgen CLK_TOP_U2U3_XHCI_SEL>; 360 clock-names = "sys_ck", 361 "ref_ck", 362 "mcu_ck", 363 "dma_ck", 364 "xhci_ck"; 365 phys = <&u2port0 PHY_TYPE_USB2>, 366 <&u3port0 PHY_TYPE_USB3>, 367 <&u2port1 PHY_TYPE_USB2>; 368 status = "disabled"; 369 }; 370 371 mmc0: mmc@11230000 { 372 compatible = "mediatek,mt7986-mmc"; 373 reg = <0 0x11230000 0 0x1000>, 374 <0 0x11c20000 0 0x1000>; 375 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 376 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, 377 <&topckgen CLK_TOP_EMMC_250M_SEL>; 378 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>, 379 <&topckgen CLK_TOP_NET1PLL_D5_D2>; 380 clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, 381 <&infracfg CLK_INFRA_MSDC_HCK_CK>, 382 <&infracfg CLK_INFRA_MSDC_CK>, 383 <&infracfg CLK_INFRA_MSDC_133M_CK>, 384 <&infracfg CLK_INFRA_MSDC_66M_CK>; 385 clock-names = "source", "hclk", "source_cg", "bus_clk", 386 "sys_cg"; 387 status = "disabled"; 388 }; 389 390 thermal: thermal@1100c800 { 391 #thermal-sensor-cells = <1>; 392 compatible = "mediatek,mt7986-thermal"; 393 reg = <0 0x1100c800 0 0x800>; 394 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&infracfg CLK_INFRA_THERM_CK>, 396 <&infracfg CLK_INFRA_ADC_26M_CK>, 397 <&infracfg CLK_INFRA_ADC_FRC_CK>; 398 clock-names = "therm", "auxadc", "adc_32k"; 399 mediatek,auxadc = <&auxadc>; 400 mediatek,apmixedsys = <&apmixedsys>; 401 nvmem-cells = <&thermal_calibration>; 402 nvmem-cell-names = "calibration-data"; 403 }; 404 405 pcie: pcie@11280000 { 406 compatible = "mediatek,mt7986-pcie", 407 "mediatek,mt8192-pcie"; 408 device_type = "pci"; 409 #address-cells = <3>; 410 #size-cells = <2>; 411 reg = <0x00 0x11280000 0x00 0x4000>; 412 reg-names = "pcie-mac"; 413 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 414 bus-range = <0x00 0xff>; 415 ranges = <0x82000000 0x00 0x20000000 0x00 416 0x20000000 0x00 0x10000000>; 417 clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, 418 <&infracfg CLK_INFRA_IPCIE_CK>, 419 <&infracfg CLK_INFRA_IPCIER_CK>, 420 <&infracfg CLK_INFRA_IPCIEB_CK>; 421 clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; 422 status = "disabled"; 423 424 phys = <&pcie_port PHY_TYPE_PCIE>; 425 phy-names = "pcie-phy"; 426 427 #interrupt-cells = <1>; 428 interrupt-map-mask = <0 0 0 0x7>; 429 interrupt-map = <0 0 0 1 &pcie_intc 0>, 430 <0 0 0 2 &pcie_intc 1>, 431 <0 0 0 3 &pcie_intc 2>, 432 <0 0 0 4 &pcie_intc 3>; 433 pcie_intc: interrupt-controller { 434 #address-cells = <0>; 435 #interrupt-cells = <1>; 436 interrupt-controller; 437 }; 438 }; 439 440 pcie_phy: t-phy { 441 compatible = "mediatek,mt7986-tphy", 442 "mediatek,generic-tphy-v2"; 443 #address-cells = <2>; 444 #size-cells = <2>; 445 ranges; 446 status = "disabled"; 447 448 pcie_port: pcie-phy@11c00000 { 449 reg = <0 0x11c00000 0 0x20000>; 450 clocks = <&clk40m>; 451 clock-names = "ref"; 452 #phy-cells = <1>; 453 }; 454 }; 455 456 efuse: efuse@11d00000 { 457 compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; 458 reg = <0 0x11d00000 0 0x1000>; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 462 thermal_calibration: calib@274 { 463 reg = <0x274 0xc>; 464 }; 465 }; 466 467 usb_phy: t-phy@11e10000 { 468 compatible = "mediatek,mt7986-tphy", 469 "mediatek,generic-tphy-v2"; 470 #address-cells = <1>; 471 #size-cells = <1>; 472 ranges = <0 0 0x11e10000 0x1700>; 473 status = "disabled"; 474 475 u2port0: usb-phy@0 { 476 reg = <0x0 0x700>; 477 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, 478 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; 479 clock-names = "ref", "da_ref"; 480 #phy-cells = <1>; 481 }; 482 483 u3port0: usb-phy@700 { 484 reg = <0x700 0x900>; 485 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; 486 clock-names = "ref"; 487 #phy-cells = <1>; 488 }; 489 490 u2port1: usb-phy@1000 { 491 reg = <0x1000 0x700>; 492 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, 493 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; 494 clock-names = "ref", "da_ref"; 495 #phy-cells = <1>; 496 }; 497 }; 498 499 ethsys: syscon@15000000 { 500 #address-cells = <1>; 501 #size-cells = <1>; 502 compatible = "mediatek,mt7986-ethsys", 503 "syscon"; 504 reg = <0 0x15000000 0 0x1000>; 505 #clock-cells = <1>; 506 #reset-cells = <1>; 507 }; 508 509 wed0: wed@15010000 { 510 compatible = "mediatek,mt7986-wed", 511 "syscon"; 512 reg = <0 0x15010000 0 0x1000>; 513 interrupt-parent = <&gic>; 514 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 515 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, 516 <&wo_data>, <&wo_boot>; 517 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", 518 "wo-data", "wo-boot"; 519 mediatek,wo-ccif = <&wo_ccif0>; 520 }; 521 522 wed1: wed@15011000 { 523 compatible = "mediatek,mt7986-wed", 524 "syscon"; 525 reg = <0 0x15011000 0 0x1000>; 526 interrupt-parent = <&gic>; 527 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 528 memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, 529 <&wo_data>, <&wo_boot>; 530 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", 531 "wo-data", "wo-boot"; 532 mediatek,wo-ccif = <&wo_ccif1>; 533 }; 534 535 wo_ccif0: syscon@151a5000 { 536 compatible = "mediatek,mt7986-wo-ccif", "syscon"; 537 reg = <0 0x151a5000 0 0x1000>; 538 interrupt-parent = <&gic>; 539 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 540 }; 541 542 wo_ccif1: syscon@151ad000 { 543 compatible = "mediatek,mt7986-wo-ccif", "syscon"; 544 reg = <0 0x151ad000 0 0x1000>; 545 interrupt-parent = <&gic>; 546 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 547 }; 548 549 eth: ethernet@15100000 { 550 compatible = "mediatek,mt7986-eth"; 551 reg = <0 0x15100000 0 0x80000>; 552 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <ðsys CLK_ETH_FE_EN>, 557 <ðsys CLK_ETH_GP2_EN>, 558 <ðsys CLK_ETH_GP1_EN>, 559 <ðsys CLK_ETH_WOCPU1_EN>, 560 <ðsys CLK_ETH_WOCPU0_EN>, 561 <&sgmiisys0 CLK_SGMII0_TX250M_EN>, 562 <&sgmiisys0 CLK_SGMII0_RX250M_EN>, 563 <&sgmiisys0 CLK_SGMII0_CDR_REF>, 564 <&sgmiisys0 CLK_SGMII0_CDR_FB>, 565 <&sgmiisys1 CLK_SGMII1_TX250M_EN>, 566 <&sgmiisys1 CLK_SGMII1_RX250M_EN>, 567 <&sgmiisys1 CLK_SGMII1_CDR_REF>, 568 <&sgmiisys1 CLK_SGMII1_CDR_FB>, 569 <&topckgen CLK_TOP_NETSYS_SEL>, 570 <&topckgen CLK_TOP_NETSYS_500M_SEL>; 571 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", 572 "sgmii_tx250m", "sgmii_rx250m", 573 "sgmii_cdr_ref", "sgmii_cdr_fb", 574 "sgmii2_tx250m", "sgmii2_rx250m", 575 "sgmii2_cdr_ref", "sgmii2_cdr_fb", 576 "netsys0", "netsys1"; 577 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, 578 <&topckgen CLK_TOP_SGM_325M_SEL>; 579 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, 580 <&apmixedsys CLK_APMIXED_SGMPLL>; 581 mediatek,ethsys = <ðsys>; 582 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; 583 mediatek,wed-pcie = <&wed_pcie>; 584 mediatek,wed = <&wed0>, <&wed1>; 585 #reset-cells = <1>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 wifi: wifi@18000000 { 592 compatible = "mediatek,mt7986-wmac"; 593 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; 594 reset-names = "consys"; 595 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, 596 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; 597 clock-names = "mcu", "ap2conn"; 598 reg = <0 0x18000000 0 0x1000000>, 599 <0 0x10003000 0 0x1000>, 600 <0 0x11d10000 0 0x1000>; 601 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 605 memory-region = <&wmcpu_emi>; 606 }; 607 }; 608 609 thermal-zones { 610 cpu_thermal: cpu-thermal { 611 polling-delay-passive = <1000>; 612 polling-delay = <1000>; 613 thermal-sensors = <&thermal 0>; 614 615 trips { 616 cpu_trip_crit: crit { 617 temperature = <125000>; 618 hysteresis = <2000>; 619 type = "critical"; 620 }; 621 622 cpu_trip_hot: hot { 623 temperature = <120000>; 624 hysteresis = <2000>; 625 type = "hot"; 626 }; 627 628 cpu_trip_active_high: active-high { 629 temperature = <115000>; 630 hysteresis = <2000>; 631 type = "active"; 632 }; 633 634 cpu_trip_active_med: active-med { 635 temperature = <85000>; 636 hysteresis = <2000>; 637 type = "active"; 638 }; 639 640 cpu_trip_active_low: active-low { 641 temperature = <60000>; 642 hysteresis = <2000>; 643 type = "active"; 644 }; 645 }; 646 }; 647 }; 648}; 649