1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 *	   Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13	compatible = "mediatek,mt7622";
14	interrupt-parent = <&sysirq>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	cpus {
19		#address-cells = <2>;
20		#size-cells = <0>;
21
22		cpu0: cpu@0 {
23			device_type = "cpu";
24			compatible = "arm,cortex-a53", "arm,armv8";
25			reg = <0x0 0x0>;
26			enable-method = "psci";
27			clock-frequency = <1300000000>;
28		};
29
30		cpu1: cpu@1 {
31			device_type = "cpu";
32			compatible = "arm,cortex-a53", "arm,armv8";
33			reg = <0x0 0x1>;
34			enable-method = "psci";
35			clock-frequency = <1300000000>;
36		};
37	};
38
39	uart_clk: dummy25m {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <25000000>;
43	};
44
45	bus_clk: dummy280m {
46		compatible = "fixed-clock";
47		#clock-cells = <0>;
48		clock-frequency = <280000000>;
49	};
50
51	psci {
52		compatible  = "arm,psci-0.2";
53		method      = "smc";
54	};
55
56	reserved-memory {
57		#address-cells = <2>;
58		#size-cells = <2>;
59		ranges;
60
61		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
62		secmon_reserved: secmon@43000000 {
63			reg = <0 0x43000000 0 0x30000>;
64			no-map;
65		};
66	};
67
68	timer {
69		compatible = "arm,armv8-timer";
70		interrupt-parent = <&gic>;
71		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
72			      IRQ_TYPE_LEVEL_HIGH)>,
73			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
74			      IRQ_TYPE_LEVEL_HIGH)>,
75			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
76			      IRQ_TYPE_LEVEL_HIGH)>,
77			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
78			      IRQ_TYPE_LEVEL_HIGH)>;
79	};
80
81	sysirq: interrupt-controller@10200620 {
82		compatible = "mediatek,mt7622-sysirq",
83			     "mediatek,mt6577-sysirq";
84		interrupt-controller;
85		#interrupt-cells = <3>;
86		interrupt-parent = <&gic>;
87		reg = <0 0x10200620 0 0x20>;
88	};
89
90	gic: interrupt-controller@10300000 {
91		compatible = "arm,gic-400";
92		interrupt-controller;
93		#interrupt-cells = <3>;
94		interrupt-parent = <&gic>;
95		reg = <0 0x10310000 0 0x1000>,
96		      <0 0x10320000 0 0x1000>,
97		      <0 0x10340000 0 0x2000>,
98		      <0 0x10360000 0 0x2000>;
99	};
100
101	uart0: serial@11002000 {
102		compatible = "mediatek,mt7622-uart",
103			     "mediatek,mt6577-uart";
104		reg = <0 0x11002000 0 0x400>;
105		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
106		clocks = <&uart_clk>, <&bus_clk>;
107		clock-names = "baud", "bus";
108		status = "disabled";
109	};
110};
111