1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Ming Huang <ming.huang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com> 5 * 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 */ 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/clock/mt7622-clk.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/power/mt7622-power.h> 14#include <dt-bindings/reset/mt7622-reset.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 compatible = "mediatek,mt7622"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpu_opp_table: opp-table { 24 compatible = "operating-points-v2"; 25 opp-shared; 26 opp-300000000 { 27 opp-hz = /bits/ 64 <30000000>; 28 opp-microvolt = <950000>; 29 }; 30 31 opp-437500000 { 32 opp-hz = /bits/ 64 <437500000>; 33 opp-microvolt = <1000000>; 34 }; 35 36 opp-600000000 { 37 opp-hz = /bits/ 64 <600000000>; 38 opp-microvolt = <1050000>; 39 }; 40 41 opp-812500000 { 42 opp-hz = /bits/ 64 <812500000>; 43 opp-microvolt = <1100000>; 44 }; 45 46 opp-1025000000 { 47 opp-hz = /bits/ 64 <1025000000>; 48 opp-microvolt = <1150000>; 49 }; 50 51 opp-1137500000 { 52 opp-hz = /bits/ 64 <1137500000>; 53 opp-microvolt = <1200000>; 54 }; 55 56 opp-1262500000 { 57 opp-hz = /bits/ 64 <1262500000>; 58 opp-microvolt = <1250000>; 59 }; 60 61 opp-1350000000 { 62 opp-hz = /bits/ 64 <1350000000>; 63 opp-microvolt = <1310000>; 64 }; 65 }; 66 67 cpus { 68 #address-cells = <2>; 69 #size-cells = <0>; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 reg = <0x0 0x0>; 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>, 76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; 77 clock-names = "cpu", "intermediate"; 78 operating-points-v2 = <&cpu_opp_table>; 79 #cooling-cells = <2>; 80 enable-method = "psci"; 81 clock-frequency = <1300000000>; 82 }; 83 84 cpu1: cpu@1 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53", "arm,armv8"; 87 reg = <0x0 0x1>; 88 clocks = <&infracfg CLK_INFRA_MUX1_SEL>, 89 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; 90 clock-names = "cpu", "intermediate"; 91 operating-points-v2 = <&cpu_opp_table>; 92 enable-method = "psci"; 93 clock-frequency = <1300000000>; 94 }; 95 }; 96 97 pwrap_clk: dummy40m { 98 compatible = "fixed-clock"; 99 clock-frequency = <40000000>; 100 #clock-cells = <0>; 101 }; 102 103 clk25m: oscillator { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <25000000>; 107 clock-output-names = "clkxtal"; 108 }; 109 110 psci { 111 compatible = "arm,psci-0.2"; 112 method = "smc"; 113 }; 114 115 reserved-memory { 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges; 119 120 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 121 secmon_reserved: secmon@43000000 { 122 reg = <0 0x43000000 0 0x30000>; 123 no-map; 124 }; 125 }; 126 127 thermal-zones { 128 cpu_thermal: cpu-thermal { 129 polling-delay-passive = <1000>; 130 polling-delay = <1000>; 131 132 thermal-sensors = <&thermal 0>; 133 134 trips { 135 cpu_passive: cpu-passive { 136 temperature = <47000>; 137 hysteresis = <2000>; 138 type = "passive"; 139 }; 140 141 cpu_active: cpu-active { 142 temperature = <67000>; 143 hysteresis = <2000>; 144 type = "active"; 145 }; 146 147 cpu_hot: cpu-hot { 148 temperature = <87000>; 149 hysteresis = <2000>; 150 type = "hot"; 151 }; 152 153 cpu-crit { 154 temperature = <107000>; 155 hysteresis = <2000>; 156 type = "critical"; 157 }; 158 }; 159 160 cooling-maps { 161 map0 { 162 trip = <&cpu_passive>; 163 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 164 }; 165 166 map1 { 167 trip = <&cpu_active>; 168 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 169 }; 170 171 map2 { 172 trip = <&cpu_hot>; 173 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 174 }; 175 }; 176 }; 177 }; 178 179 timer { 180 compatible = "arm,armv8-timer"; 181 interrupt-parent = <&gic>; 182 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 183 IRQ_TYPE_LEVEL_HIGH)>, 184 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 185 IRQ_TYPE_LEVEL_HIGH)>, 186 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 187 IRQ_TYPE_LEVEL_HIGH)>, 188 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 189 IRQ_TYPE_LEVEL_HIGH)>; 190 }; 191 192 infracfg: infracfg@10000000 { 193 compatible = "mediatek,mt7622-infracfg", 194 "syscon"; 195 reg = <0 0x10000000 0 0x1000>; 196 #clock-cells = <1>; 197 #reset-cells = <1>; 198 }; 199 200 pwrap: pwrap@10001000 { 201 compatible = "mediatek,mt7622-pwrap"; 202 reg = <0 0x10001000 0 0x250>; 203 reg-names = "pwrap"; 204 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>; 205 clock-names = "spi", "wrap"; 206 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; 207 reset-names = "pwrap"; 208 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 209 status = "disabled"; 210 }; 211 212 pericfg: pericfg@10002000 { 213 compatible = "mediatek,mt7622-pericfg", 214 "syscon"; 215 reg = <0 0x10002000 0 0x1000>; 216 #clock-cells = <1>; 217 #reset-cells = <1>; 218 }; 219 220 scpsys: scpsys@10006000 { 221 compatible = "mediatek,mt7622-scpsys", 222 "syscon"; 223 #power-domain-cells = <1>; 224 reg = <0 0x10006000 0 0x1000>; 225 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>, 226 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>, 227 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>, 228 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; 229 infracfg = <&infracfg>; 230 clocks = <&topckgen CLK_TOP_HIF_SEL>; 231 clock-names = "hif_sel"; 232 }; 233 234 cir: cir@10009000 { 235 compatible = "mediatek,mt7622-cir"; 236 reg = <0 0x10009000 0 0x1000>; 237 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>; 238 clocks = <&infracfg CLK_INFRA_IRRX_PD>, 239 <&topckgen CLK_TOP_AXI_SEL>; 240 clock-names = "clk", "bus"; 241 status = "disabled"; 242 }; 243 244 sysirq: interrupt-controller@10200620 { 245 compatible = "mediatek,mt7622-sysirq", 246 "mediatek,mt6577-sysirq"; 247 interrupt-controller; 248 #interrupt-cells = <3>; 249 interrupt-parent = <&gic>; 250 reg = <0 0x10200620 0 0x20>; 251 }; 252 253 efuse: efuse@10206000 { 254 compatible = "mediatek,mt7622-efuse", 255 "mediatek,efuse"; 256 reg = <0 0x10206000 0 0x1000>; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 260 thermal_calibration: calib@198 { 261 reg = <0x198 0xc>; 262 }; 263 }; 264 265 apmixedsys: apmixedsys@10209000 { 266 compatible = "mediatek,mt7622-apmixedsys", 267 "syscon"; 268 reg = <0 0x10209000 0 0x1000>; 269 #clock-cells = <1>; 270 }; 271 272 topckgen: topckgen@10210000 { 273 compatible = "mediatek,mt7622-topckgen", 274 "syscon"; 275 reg = <0 0x10210000 0 0x1000>; 276 #clock-cells = <1>; 277 }; 278 279 rng: rng@1020f000 { 280 compatible = "mediatek,mt7622-rng", 281 "mediatek,mt7623-rng"; 282 reg = <0 0x1020f000 0 0x1000>; 283 clocks = <&infracfg CLK_INFRA_TRNG>; 284 clock-names = "rng"; 285 }; 286 287 pio: pinctrl@10211000 { 288 compatible = "mediatek,mt7622-pinctrl"; 289 reg = <0 0x10211000 0 0x1000>; 290 gpio-controller; 291 #gpio-cells = <2>; 292 }; 293 294 watchdog: watchdog@10212000 { 295 compatible = "mediatek,mt7622-wdt", 296 "mediatek,mt6589-wdt"; 297 reg = <0 0x10212000 0 0x800>; 298 }; 299 300 rtc: rtc@10212800 { 301 compatible = "mediatek,mt7622-rtc", 302 "mediatek,soc-rtc"; 303 reg = <0 0x10212800 0 0x200>; 304 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 305 clocks = <&topckgen CLK_TOP_RTC>; 306 clock-names = "rtc"; 307 }; 308 309 gic: interrupt-controller@10300000 { 310 compatible = "arm,gic-400"; 311 interrupt-controller; 312 #interrupt-cells = <3>; 313 interrupt-parent = <&gic>; 314 reg = <0 0x10310000 0 0x1000>, 315 <0 0x10320000 0 0x1000>, 316 <0 0x10340000 0 0x2000>, 317 <0 0x10360000 0 0x2000>; 318 }; 319 320 auxadc: adc@11001000 { 321 compatible = "mediatek,mt7622-auxadc"; 322 reg = <0 0x11001000 0 0x1000>; 323 clocks = <&pericfg CLK_PERI_AUXADC_PD>; 324 clock-names = "main"; 325 #io-channel-cells = <1>; 326 }; 327 328 uart0: serial@11002000 { 329 compatible = "mediatek,mt7622-uart", 330 "mediatek,mt6577-uart"; 331 reg = <0 0x11002000 0 0x400>; 332 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 333 clocks = <&topckgen CLK_TOP_UART_SEL>, 334 <&pericfg CLK_PERI_UART1_PD>; 335 clock-names = "baud", "bus"; 336 status = "disabled"; 337 }; 338 339 uart1: serial@11003000 { 340 compatible = "mediatek,mt7622-uart", 341 "mediatek,mt6577-uart"; 342 reg = <0 0x11003000 0 0x400>; 343 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 344 clocks = <&topckgen CLK_TOP_UART_SEL>, 345 <&pericfg CLK_PERI_UART1_PD>; 346 clock-names = "baud", "bus"; 347 status = "disabled"; 348 }; 349 350 uart2: serial@11004000 { 351 compatible = "mediatek,mt7622-uart", 352 "mediatek,mt6577-uart"; 353 reg = <0 0x11004000 0 0x400>; 354 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 355 clocks = <&topckgen CLK_TOP_UART_SEL>, 356 <&pericfg CLK_PERI_UART2_PD>; 357 clock-names = "baud", "bus"; 358 status = "disabled"; 359 }; 360 361 uart3: serial@11005000 { 362 compatible = "mediatek,mt7622-uart", 363 "mediatek,mt6577-uart"; 364 reg = <0 0x11005000 0 0x400>; 365 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 366 clocks = <&topckgen CLK_TOP_UART_SEL>, 367 <&pericfg CLK_PERI_UART3_PD>; 368 clock-names = "baud", "bus"; 369 status = "disabled"; 370 }; 371 372 pwm: pwm@11006000 { 373 compatible = "mediatek,mt7622-pwm"; 374 reg = <0 0x11006000 0 0x1000>; 375 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 376 clocks = <&topckgen CLK_TOP_PWM_SEL>, 377 <&pericfg CLK_PERI_PWM_PD>, 378 <&pericfg CLK_PERI_PWM1_PD>, 379 <&pericfg CLK_PERI_PWM2_PD>, 380 <&pericfg CLK_PERI_PWM3_PD>, 381 <&pericfg CLK_PERI_PWM4_PD>, 382 <&pericfg CLK_PERI_PWM5_PD>, 383 <&pericfg CLK_PERI_PWM6_PD>; 384 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", 385 "pwm5", "pwm6"; 386 status = "disabled"; 387 }; 388 389 i2c0: i2c@11007000 { 390 compatible = "mediatek,mt7622-i2c"; 391 reg = <0 0x11007000 0 0x90>, 392 <0 0x11000100 0 0x80>; 393 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 394 clock-div = <16>; 395 clocks = <&pericfg CLK_PERI_I2C0_PD>, 396 <&pericfg CLK_PERI_AP_DMA_PD>; 397 clock-names = "main", "dma"; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 status = "disabled"; 401 }; 402 403 i2c1: i2c@11008000 { 404 compatible = "mediatek,mt7622-i2c"; 405 reg = <0 0x11008000 0 0x90>, 406 <0 0x11000180 0 0x80>; 407 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 408 clock-div = <16>; 409 clocks = <&pericfg CLK_PERI_I2C1_PD>, 410 <&pericfg CLK_PERI_AP_DMA_PD>; 411 clock-names = "main", "dma"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 status = "disabled"; 415 }; 416 417 i2c2: i2c@11009000 { 418 compatible = "mediatek,mt7622-i2c"; 419 reg = <0 0x11009000 0 0x90>, 420 <0 0x11000200 0 0x80>; 421 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 422 clock-div = <16>; 423 clocks = <&pericfg CLK_PERI_I2C2_PD>, 424 <&pericfg CLK_PERI_AP_DMA_PD>; 425 clock-names = "main", "dma"; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 status = "disabled"; 429 }; 430 431 spi0: spi@1100a000 { 432 compatible = "mediatek,mt7622-spi"; 433 reg = <0 0x1100a000 0 0x100>; 434 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; 435 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 436 <&topckgen CLK_TOP_SPI0_SEL>, 437 <&pericfg CLK_PERI_SPI0_PD>; 438 clock-names = "parent-clk", "sel-clk", "spi-clk"; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 thermal: thermal@1100b000 { 445 #thermal-sensor-cells = <1>; 446 compatible = "mediatek,mt7622-thermal"; 447 reg = <0 0x1100b000 0 0x1000>; 448 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>; 449 clocks = <&pericfg CLK_PERI_THERM_PD>, 450 <&pericfg CLK_PERI_AUXADC_PD>; 451 clock-names = "therm", "auxadc"; 452 resets = <&pericfg MT7622_PERI_THERM_SW_RST>; 453 reset-names = "therm"; 454 mediatek,auxadc = <&auxadc>; 455 mediatek,apmixedsys = <&apmixedsys>; 456 nvmem-cells = <&thermal_calibration>; 457 nvmem-cell-names = "calibration-data"; 458 }; 459 460 btif: serial@1100c000 { 461 compatible = "mediatek,mt7622-btif", 462 "mediatek,mtk-btif"; 463 reg = <0 0x1100c000 0 0x1000>; 464 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 465 clocks = <&pericfg CLK_PERI_BTIF_PD>; 466 clock-names = "main"; 467 reg-shift = <2>; 468 reg-io-width = <4>; 469 status = "disabled"; 470 }; 471 472 nandc: nfi@1100d000 { 473 compatible = "mediatek,mt7622-nfc"; 474 reg = <0 0x1100D000 0 0x1000>; 475 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 476 clocks = <&pericfg CLK_PERI_NFI_PD>, 477 <&pericfg CLK_PERI_SNFI_PD>; 478 clock-names = "nfi_clk", "pad_clk"; 479 ecc-engine = <&bch>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 bch: ecc@1100e000 { 486 compatible = "mediatek,mt7622-ecc"; 487 reg = <0 0x1100e000 0 0x1000>; 488 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; 489 clocks = <&pericfg CLK_PERI_NFIECC_PD>; 490 clock-names = "nfiecc_clk"; 491 status = "disabled"; 492 }; 493 494 nor_flash: spi@11014000 { 495 compatible = "mediatek,mt7622-nor", 496 "mediatek,mt8173-nor"; 497 reg = <0 0x11014000 0 0xe0>; 498 clocks = <&pericfg CLK_PERI_FLASH_PD>, 499 <&topckgen CLK_TOP_FLASH_SEL>; 500 clock-names = "spi", "sf"; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 status = "disabled"; 504 }; 505 506 spi1: spi@11016000 { 507 compatible = "mediatek,mt7622-spi"; 508 reg = <0 0x11016000 0 0x100>; 509 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 510 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 511 <&topckgen CLK_TOP_SPI1_SEL>, 512 <&pericfg CLK_PERI_SPI1_PD>; 513 clock-names = "parent-clk", "sel-clk", "spi-clk"; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 }; 518 519 uart4: serial@11019000 { 520 compatible = "mediatek,mt7622-uart", 521 "mediatek,mt6577-uart"; 522 reg = <0 0x11019000 0 0x400>; 523 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 524 clocks = <&topckgen CLK_TOP_UART_SEL>, 525 <&pericfg CLK_PERI_UART4_PD>; 526 clock-names = "baud", "bus"; 527 status = "disabled"; 528 }; 529 530 audsys: clock-controller@11220000 { 531 compatible = "mediatek,mt7622-audsys", "syscon"; 532 reg = <0 0x11220000 0 0x2000>; 533 #clock-cells = <1>; 534 535 afe: audio-controller { 536 compatible = "mediatek,mt7622-audio"; 537 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>, 538 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 539 interrupt-names = "afe", "asys"; 540 541 clocks = <&infracfg CLK_INFRA_AUDIO_PD>, 542 <&topckgen CLK_TOP_AUD1_SEL>, 543 <&topckgen CLK_TOP_AUD2_SEL>, 544 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>, 545 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>, 546 <&topckgen CLK_TOP_I2S0_MCK_SEL>, 547 <&topckgen CLK_TOP_I2S1_MCK_SEL>, 548 <&topckgen CLK_TOP_I2S2_MCK_SEL>, 549 <&topckgen CLK_TOP_I2S3_MCK_SEL>, 550 <&topckgen CLK_TOP_I2S0_MCK_DIV>, 551 <&topckgen CLK_TOP_I2S1_MCK_DIV>, 552 <&topckgen CLK_TOP_I2S2_MCK_DIV>, 553 <&topckgen CLK_TOP_I2S3_MCK_DIV>, 554 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>, 555 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>, 556 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>, 557 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>, 558 <&audsys CLK_AUDIO_I2SO1>, 559 <&audsys CLK_AUDIO_I2SO2>, 560 <&audsys CLK_AUDIO_I2SO3>, 561 <&audsys CLK_AUDIO_I2SO4>, 562 <&audsys CLK_AUDIO_I2SIN1>, 563 <&audsys CLK_AUDIO_I2SIN2>, 564 <&audsys CLK_AUDIO_I2SIN3>, 565 <&audsys CLK_AUDIO_I2SIN4>, 566 <&audsys CLK_AUDIO_ASRCO1>, 567 <&audsys CLK_AUDIO_ASRCO2>, 568 <&audsys CLK_AUDIO_ASRCO3>, 569 <&audsys CLK_AUDIO_ASRCO4>, 570 <&audsys CLK_AUDIO_AFE>, 571 <&audsys CLK_AUDIO_AFE_CONN>, 572 <&audsys CLK_AUDIO_A1SYS>, 573 <&audsys CLK_AUDIO_A2SYS>; 574 575 clock-names = "infra_sys_audio_clk", 576 "top_audio_mux1_sel", 577 "top_audio_mux2_sel", 578 "top_audio_a1sys_hp", 579 "top_audio_a2sys_hp", 580 "i2s0_src_sel", 581 "i2s1_src_sel", 582 "i2s2_src_sel", 583 "i2s3_src_sel", 584 "i2s0_src_div", 585 "i2s1_src_div", 586 "i2s2_src_div", 587 "i2s3_src_div", 588 "i2s0_mclk_en", 589 "i2s1_mclk_en", 590 "i2s2_mclk_en", 591 "i2s3_mclk_en", 592 "i2so0_hop_ck", 593 "i2so1_hop_ck", 594 "i2so2_hop_ck", 595 "i2so3_hop_ck", 596 "i2si0_hop_ck", 597 "i2si1_hop_ck", 598 "i2si2_hop_ck", 599 "i2si3_hop_ck", 600 "asrc0_out_ck", 601 "asrc1_out_ck", 602 "asrc2_out_ck", 603 "asrc3_out_ck", 604 "audio_afe_pd", 605 "audio_afe_conn_pd", 606 "audio_a1sys_pd", 607 "audio_a2sys_pd"; 608 609 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>, 610 <&topckgen CLK_TOP_A2SYS_HP_SEL>, 611 <&topckgen CLK_TOP_A1SYS_HP_DIV>, 612 <&topckgen CLK_TOP_A2SYS_HP_DIV>; 613 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>, 614 <&topckgen CLK_TOP_AUD2PLL>; 615 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; 616 }; 617 }; 618 619 mmc0: mmc@11230000 { 620 compatible = "mediatek,mt7622-mmc"; 621 reg = <0 0x11230000 0 0x1000>; 622 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 623 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, 624 <&topckgen CLK_TOP_MSDC50_0_SEL>; 625 clock-names = "source", "hclk"; 626 status = "disabled"; 627 }; 628 629 mmc1: mmc@11240000 { 630 compatible = "mediatek,mt7622-mmc"; 631 reg = <0 0x11240000 0 0x1000>; 632 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 633 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, 634 <&topckgen CLK_TOP_AXI_SEL>; 635 clock-names = "source", "hclk"; 636 status = "disabled"; 637 }; 638 639 ssusbsys: ssusbsys@1a000000 { 640 compatible = "mediatek,mt7622-ssusbsys", 641 "syscon"; 642 reg = <0 0x1a000000 0 0x1000>; 643 #clock-cells = <1>; 644 #reset-cells = <1>; 645 }; 646 647 ssusb: usb@1a0c0000 { 648 compatible = "mediatek,mt7622-xhci", 649 "mediatek,mtk-xhci"; 650 reg = <0 0x1a0c0000 0 0x01000>, 651 <0 0x1a0c4700 0 0x0100>; 652 reg-names = "mac", "ippc"; 653 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 654 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; 655 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, 656 <&ssusbsys CLK_SSUSB_REF_EN>, 657 <&ssusbsys CLK_SSUSB_MCU_EN>, 658 <&ssusbsys CLK_SSUSB_DMA_EN>; 659 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 660 phys = <&u2port0 PHY_TYPE_USB2>, 661 <&u3port0 PHY_TYPE_USB3>, 662 <&u2port1 PHY_TYPE_USB2>; 663 664 status = "disabled"; 665 }; 666 667 u3phy: usb-phy@1a0c4000 { 668 compatible = "mediatek,mt7622-u3phy", 669 "mediatek,generic-tphy-v1"; 670 reg = <0 0x1a0c4000 0 0x700>; 671 #address-cells = <2>; 672 #size-cells = <2>; 673 ranges; 674 status = "disabled"; 675 676 u2port0: usb-phy@1a0c4800 { 677 reg = <0 0x1a0c4800 0 0x0100>; 678 #phy-cells = <1>; 679 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; 680 clock-names = "ref"; 681 }; 682 683 u3port0: usb-phy@1a0c4900 { 684 reg = <0 0x1a0c4900 0 0x0700>; 685 #phy-cells = <1>; 686 clocks = <&clk25m>; 687 clock-names = "ref"; 688 }; 689 690 u2port1: usb-phy@1a0c5000 { 691 reg = <0 0x1a0c5000 0 0x0100>; 692 #phy-cells = <1>; 693 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; 694 clock-names = "ref"; 695 }; 696 }; 697 698 pciesys: pciesys@1a100800 { 699 compatible = "mediatek,mt7622-pciesys", 700 "syscon"; 701 reg = <0 0x1a100800 0 0x1000>; 702 #clock-cells = <1>; 703 #reset-cells = <1>; 704 }; 705 706 pcie: pcie@1a140000 { 707 compatible = "mediatek,mt7622-pcie"; 708 device_type = "pci"; 709 reg = <0 0x1a140000 0 0x1000>, 710 <0 0x1a143000 0 0x1000>, 711 <0 0x1a145000 0 0x1000>; 712 reg-names = "subsys", "port0", "port1"; 713 #address-cells = <3>; 714 #size-cells = <2>; 715 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>, 716 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 717 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, 718 <&pciesys CLK_PCIE_P1_MAC_EN>, 719 <&pciesys CLK_PCIE_P0_AHB_EN>, 720 <&pciesys CLK_PCIE_P0_AHB_EN>, 721 <&pciesys CLK_PCIE_P0_AUX_EN>, 722 <&pciesys CLK_PCIE_P1_AUX_EN>, 723 <&pciesys CLK_PCIE_P0_AXI_EN>, 724 <&pciesys CLK_PCIE_P1_AXI_EN>, 725 <&pciesys CLK_PCIE_P0_OBFF_EN>, 726 <&pciesys CLK_PCIE_P1_OBFF_EN>, 727 <&pciesys CLK_PCIE_P0_PIPE_EN>, 728 <&pciesys CLK_PCIE_P1_PIPE_EN>; 729 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", 730 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", 731 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; 732 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 733 bus-range = <0x00 0xff>; 734 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 735 status = "disabled"; 736 737 pcie0: pcie@0,0 { 738 reg = <0x0000 0 0 0 0>; 739 #address-cells = <3>; 740 #size-cells = <2>; 741 #interrupt-cells = <1>; 742 ranges; 743 status = "disabled"; 744 745 num-lanes = <1>; 746 interrupt-map-mask = <0 0 0 7>; 747 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 748 <0 0 0 2 &pcie_intc0 1>, 749 <0 0 0 3 &pcie_intc0 2>, 750 <0 0 0 4 &pcie_intc0 3>; 751 pcie_intc0: interrupt-controller { 752 interrupt-controller; 753 #address-cells = <0>; 754 #interrupt-cells = <1>; 755 }; 756 }; 757 758 pcie1: pcie@1,0 { 759 reg = <0x0800 0 0 0 0>; 760 #address-cells = <3>; 761 #size-cells = <2>; 762 #interrupt-cells = <1>; 763 ranges; 764 status = "disabled"; 765 766 num-lanes = <1>; 767 interrupt-map-mask = <0 0 0 7>; 768 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 769 <0 0 0 2 &pcie_intc1 1>, 770 <0 0 0 3 &pcie_intc1 2>, 771 <0 0 0 4 &pcie_intc1 3>; 772 pcie_intc1: interrupt-controller { 773 interrupt-controller; 774 #address-cells = <0>; 775 #interrupt-cells = <1>; 776 }; 777 }; 778 }; 779 780 sata: sata@1a200000 { 781 compatible = "mediatek,mt7622-ahci", 782 "mediatek,mtk-ahci"; 783 reg = <0 0x1a200000 0 0x1100>; 784 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 785 interrupt-names = "hostc"; 786 clocks = <&pciesys CLK_SATA_AHB_EN>, 787 <&pciesys CLK_SATA_AXI_EN>, 788 <&pciesys CLK_SATA_ASIC_EN>, 789 <&pciesys CLK_SATA_RBC_EN>, 790 <&pciesys CLK_SATA_PM_EN>; 791 clock-names = "ahb", "axi", "asic", "rbc", "pm"; 792 phys = <&sata_port PHY_TYPE_SATA>; 793 phy-names = "sata-phy"; 794 ports-implemented = <0x1>; 795 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 796 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, 797 <&pciesys MT7622_SATA_PHY_SW_RST>, 798 <&pciesys MT7622_SATA_PHY_REG_RST>; 799 reset-names = "axi", "sw", "reg"; 800 mediatek,phy-mode = <&pciesys>; 801 status = "disabled"; 802 }; 803 804 sata_phy: sata-phy@1a243000 { 805 compatible = "mediatek,generic-tphy-v1"; 806 #address-cells = <2>; 807 #size-cells = <2>; 808 ranges; 809 status = "disabled"; 810 811 sata_port: sata-phy@1a243000 { 812 reg = <0 0x1a243000 0 0x0100>; 813 clocks = <&topckgen CLK_TOP_ETH_500M>; 814 clock-names = "ref"; 815 #phy-cells = <1>; 816 }; 817 }; 818 819 ethsys: syscon@1b000000 { 820 compatible = "mediatek,mt7622-ethsys", 821 "syscon"; 822 reg = <0 0x1b000000 0 0x1000>; 823 #clock-cells = <1>; 824 #reset-cells = <1>; 825 }; 826 827 hsdma: dma-controller@1b007000 { 828 compatible = "mediatek,mt7622-hsdma"; 829 reg = <0 0x1b007000 0 0x1000>; 830 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>; 831 clocks = <ðsys CLK_ETH_HSDMA_EN>; 832 clock-names = "hsdma"; 833 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; 834 #dma-cells = <1>; 835 }; 836 837 eth: ethernet@1b100000 { 838 compatible = "mediatek,mt7622-eth", 839 "mediatek,mt2701-eth", 840 "syscon"; 841 reg = <0 0x1b100000 0 0x20000>; 842 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>, 843 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>, 844 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 845 clocks = <&topckgen CLK_TOP_ETH_SEL>, 846 <ðsys CLK_ETH_ESW_EN>, 847 <ðsys CLK_ETH_GP0_EN>, 848 <ðsys CLK_ETH_GP1_EN>, 849 <ðsys CLK_ETH_GP2_EN>, 850 <&sgmiisys CLK_SGMII_TX250M_EN>, 851 <&sgmiisys CLK_SGMII_RX250M_EN>, 852 <&sgmiisys CLK_SGMII_CDR_REF>, 853 <&sgmiisys CLK_SGMII_CDR_FB>, 854 <&topckgen CLK_TOP_SGMIIPLL>, 855 <&apmixedsys CLK_APMIXED_ETH2PLL>; 856 clock-names = "ethif", "esw", "gp0", "gp1", "gp2", 857 "sgmii_tx250m", "sgmii_rx250m", 858 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", 859 "eth2pll"; 860 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; 861 mediatek,ethsys = <ðsys>; 862 mediatek,sgmiisys = <&sgmiisys>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 status = "disabled"; 866 }; 867 868 sgmiisys: sgmiisys@1b128000 { 869 compatible = "mediatek,mt7622-sgmiisys", 870 "syscon"; 871 reg = <0 0x1b128000 0 0x1000>; 872 #clock-cells = <1>; 873 }; 874}; 875