1/*
2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/leds/common.h>
12
13#include "mt7622.dtsi"
14#include "mt6380.dtsi"
15
16/ {
17	model = "Bananapi BPI-R64";
18	chassis-type = "embedded";
19	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	chosen {
26		stdout-path = "serial0:115200n8";
27		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
28	};
29
30	cpus {
31		cpu@0 {
32			proc-supply = <&mt6380_vcpu_reg>;
33			sram-supply = <&mt6380_vm_reg>;
34		};
35
36		cpu@1 {
37			proc-supply = <&mt6380_vcpu_reg>;
38			sram-supply = <&mt6380_vm_reg>;
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		factory-key {
46			label = "factory";
47			linux,code = <BTN_0>;
48			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
49		};
50
51		wps-key {
52			label = "wps";
53			linux,code = <KEY_WPS_BUTTON>;
54			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
55		};
56	};
57
58	leds {
59		compatible = "gpio-leds";
60
61		led-0 {
62			label = "bpi-r64:pio:green";
63			color = <LED_COLOR_ID_GREEN>;
64			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
65			default-state = "off";
66		};
67
68		led-1 {
69			label = "bpi-r64:pio:red";
70			color = <LED_COLOR_ID_RED>;
71			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
72			default-state = "off";
73		};
74	};
75
76	memory@40000000 {
77		reg = <0 0x40000000 0 0x40000000>;
78		device_type = "memory";
79	};
80
81	reg_1p8v: regulator-1p8v {
82		compatible = "regulator-fixed";
83		regulator-name = "fixed-1.8V";
84		regulator-min-microvolt = <1800000>;
85		regulator-max-microvolt = <1800000>;
86		regulator-always-on;
87	};
88
89	reg_3p3v: regulator-3p3v {
90		compatible = "regulator-fixed";
91		regulator-name = "fixed-3.3V";
92		regulator-min-microvolt = <3300000>;
93		regulator-max-microvolt = <3300000>;
94		regulator-boot-on;
95		regulator-always-on;
96	};
97
98	reg_5v: regulator-5v {
99		compatible = "regulator-fixed";
100		regulator-name = "fixed-5V";
101		regulator-min-microvolt = <5000000>;
102		regulator-max-microvolt = <5000000>;
103		regulator-boot-on;
104		regulator-always-on;
105	};
106};
107
108&bch {
109	status = "disabled";
110};
111
112&btif {
113	status = "okay";
114};
115
116&cir {
117	pinctrl-names = "default";
118	pinctrl-0 = <&irrx_pins>;
119	status = "okay";
120};
121
122&eth {
123	status = "okay";
124	gmac0: mac@0 {
125		compatible = "mediatek,eth-mac";
126		reg = <0>;
127		phy-mode = "2500base-x";
128
129		fixed-link {
130			speed = <2500>;
131			full-duplex;
132			pause;
133		};
134	};
135
136	gmac1: mac@1 {
137		compatible = "mediatek,eth-mac";
138		reg = <1>;
139		phy-mode = "rgmii";
140
141		fixed-link {
142			speed = <1000>;
143			full-duplex;
144			pause;
145		};
146	};
147
148	mdio: mdio-bus {
149		#address-cells = <1>;
150		#size-cells = <0>;
151
152		switch@0 {
153			compatible = "mediatek,mt7531";
154			reg = <0>;
155			interrupt-controller;
156			#interrupt-cells = <1>;
157			interrupt-parent = <&pio>;
158			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
159			reset-gpios = <&pio 54 0>;
160
161			ports {
162				#address-cells = <1>;
163				#size-cells = <0>;
164
165				port@0 {
166					reg = <0>;
167					label = "wan";
168				};
169
170				port@1 {
171					reg = <1>;
172					label = "lan0";
173				};
174
175				port@2 {
176					reg = <2>;
177					label = "lan1";
178				};
179
180				port@3 {
181					reg = <3>;
182					label = "lan2";
183				};
184
185				port@4 {
186					reg = <4>;
187					label = "lan3";
188				};
189
190				port@6 {
191					reg = <6>;
192					label = "cpu";
193					ethernet = <&gmac0>;
194					phy-mode = "2500base-x";
195
196					fixed-link {
197						speed = <2500>;
198						full-duplex;
199						pause;
200					};
201				};
202			};
203		};
204
205	};
206};
207
208&i2c1 {
209	pinctrl-names = "default";
210	pinctrl-0 = <&i2c1_pins>;
211	status = "okay";
212};
213
214&i2c2 {
215	pinctrl-names = "default";
216	pinctrl-0 = <&i2c2_pins>;
217	status = "okay";
218};
219
220&mmc0 {
221	pinctrl-names = "default", "state_uhs";
222	pinctrl-0 = <&emmc_pins_default>;
223	pinctrl-1 = <&emmc_pins_uhs>;
224	status = "okay";
225	bus-width = <8>;
226	max-frequency = <50000000>;
227	cap-mmc-highspeed;
228	mmc-hs200-1_8v;
229	vmmc-supply = <&reg_3p3v>;
230	vqmmc-supply = <&reg_1p8v>;
231	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
232	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
233	non-removable;
234};
235
236&mmc1 {
237	pinctrl-names = "default", "state_uhs";
238	pinctrl-0 = <&sd0_pins_default>;
239	pinctrl-1 = <&sd0_pins_uhs>;
240	status = "okay";
241	bus-width = <4>;
242	max-frequency = <50000000>;
243	cap-sd-highspeed;
244	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
245	vmmc-supply = <&reg_3p3v>;
246	vqmmc-supply = <&reg_3p3v>;
247	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
248	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
249};
250
251&nandc {
252	pinctrl-names = "default";
253	pinctrl-0 = <&parallel_nand_pins>;
254	status = "disabled";
255};
256
257&bch {
258	status = "okay";
259};
260
261&snfi {
262	pinctrl-names = "default";
263	pinctrl-0 = <&serial_nand_pins>;
264	status = "okay";
265	flash@0 {
266		compatible = "spi-nand";
267		reg = <0>;
268		spi-tx-bus-width = <4>;
269		spi-rx-bus-width = <4>;
270		nand-ecc-engine = <&snfi>;
271		partitions {
272			compatible = "fixed-partitions";
273			#address-cells = <1>;
274			#size-cells = <1>;
275
276			partition@0 {
277				label = "bl2";
278				reg = <0x0 0x80000>;
279				read-only;
280			};
281
282			partition@80000 {
283				label = "fip";
284				reg = <0x80000 0x200000>;
285				read-only;
286			};
287
288			ubi: partition@280000 {
289				label = "ubi";
290				reg = <0x280000 0x7d80000>;
291			};
292		};
293	};
294};
295
296&pcie0 {
297	pinctrl-names = "default";
298	pinctrl-0 = <&pcie0_pins>;
299	status = "okay";
300};
301
302&pcie1 {
303	pinctrl-names = "default";
304	pinctrl-0 = <&pcie1_pins>;
305	status = "okay";
306};
307
308&pio {
309	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
310	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
311	 */
312	asm_sel {
313		gpio-hog;
314		gpios = <90 GPIO_ACTIVE_HIGH>;
315		output-high;
316	};
317
318	/* eMMC is shared pin with parallel NAND */
319	emmc_pins_default: emmc-pins-default {
320		mux {
321			function = "emmc", "emmc_rst";
322			groups = "emmc";
323		};
324
325		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
326		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
327		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
328		 */
329		conf-cmd-dat {
330			pins = "NDL0", "NDL1", "NDL2",
331			       "NDL3", "NDL4", "NDL5",
332			       "NDL6", "NDL7", "NRB";
333			input-enable;
334			bias-pull-up;
335		};
336
337		conf-clk {
338			pins = "NCLE";
339			bias-pull-down;
340		};
341	};
342
343	emmc_pins_uhs: emmc-pins-uhs {
344		mux {
345			function = "emmc";
346			groups = "emmc";
347		};
348
349		conf-cmd-dat {
350			pins = "NDL0", "NDL1", "NDL2",
351			       "NDL3", "NDL4", "NDL5",
352			       "NDL6", "NDL7", "NRB";
353			input-enable;
354			drive-strength = <4>;
355			bias-pull-up;
356		};
357
358		conf-clk {
359			pins = "NCLE";
360			drive-strength = <4>;
361			bias-pull-down;
362		};
363	};
364
365	eth_pins: eth-pins {
366		mux {
367			function = "eth";
368			groups = "mdc_mdio", "rgmii_via_gmac2";
369		};
370	};
371
372	i2c1_pins: i2c1-pins {
373		mux {
374			function = "i2c";
375			groups = "i2c1_0";
376		};
377	};
378
379	i2c2_pins: i2c2-pins {
380		mux {
381			function = "i2c";
382			groups = "i2c2_0";
383		};
384	};
385
386	i2s1_pins: i2s1-pins {
387		mux {
388			function = "i2s";
389			groups =  "i2s_out_mclk_bclk_ws",
390				  "i2s1_in_data",
391				  "i2s1_out_data";
392		};
393
394		conf {
395			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
396			       "I2S_WS", "I2S_MCLK";
397			drive-strength = <12>;
398			bias-pull-down;
399		};
400	};
401
402	irrx_pins: irrx-pins {
403		mux {
404			function = "ir";
405			groups = "ir_1_rx";
406		};
407	};
408
409	irtx_pins: irtx-pins {
410		mux {
411			function = "ir";
412			groups = "ir_1_tx";
413		};
414	};
415
416	/* Parallel nand is shared pin with eMMC */
417	parallel_nand_pins: parallel-nand-pins {
418		mux {
419			function = "flash";
420			groups = "par_nand";
421		};
422	};
423
424	pcie0_pins: pcie0-pins {
425		mux {
426			function = "pcie";
427			groups = "pcie0_pad_perst",
428				 "pcie0_1_waken",
429				 "pcie0_1_clkreq";
430		};
431	};
432
433	pcie1_pins: pcie1-pins {
434		mux {
435			function = "pcie";
436			groups = "pcie1_pad_perst",
437				 "pcie1_0_waken",
438				 "pcie1_0_clkreq";
439		};
440	};
441
442	pmic_bus_pins: pmic-bus-pins {
443		mux {
444			function = "pmic";
445			groups = "pmic_bus";
446		};
447	};
448
449	pwm_pins: pwm-pins {
450		mux {
451			function = "pwm";
452			groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
453				 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
454				 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
455				 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
456				 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
457				 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
458		};
459	};
460
461	wled_pins: wled-pins {
462		mux {
463			function = "led";
464			groups = "wled";
465		};
466	};
467
468	sd0_pins_default: sd0-pins-default {
469		mux {
470			function = "sd";
471			groups = "sd_0";
472		};
473
474		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
475		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
476		 *  DAT2, DAT3, CMD, CLK for SD respectively.
477		 */
478		conf-cmd-data {
479			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
480			       "I2S2_IN","I2S4_OUT";
481			input-enable;
482			drive-strength = <8>;
483			bias-pull-up;
484		};
485		conf-clk {
486			pins = "I2S3_OUT";
487			drive-strength = <12>;
488			bias-pull-down;
489		};
490		conf-cd {
491			pins = "TXD3";
492			bias-pull-up;
493		};
494	};
495
496	sd0_pins_uhs: sd0-pins-uhs {
497		mux {
498			function = "sd";
499			groups = "sd_0";
500		};
501
502		conf-cmd-data {
503			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
504			       "I2S2_IN","I2S4_OUT";
505			input-enable;
506			bias-pull-up;
507		};
508
509		conf-clk {
510			pins = "I2S3_OUT";
511			bias-pull-down;
512		};
513	};
514
515	/* Serial NAND is shared pin with SPI-NOR */
516	serial_nand_pins: serial-nand-pins {
517		mux {
518			function = "flash";
519			groups = "snfi";
520		};
521	};
522
523	spic0_pins: spic0-pins {
524		mux {
525			function = "spi";
526			groups = "spic0_0";
527		};
528	};
529
530	spic1_pins: spic1-pins {
531		mux {
532			function = "spi";
533			groups = "spic1_0";
534		};
535	};
536
537	/* SPI-NOR is shared pin with serial NAND */
538	spi_nor_pins: spi-nor-pins {
539		mux {
540			function = "flash";
541			groups = "spi_nor";
542		};
543	};
544
545	/* serial NAND is shared pin with SPI-NOR */
546	serial_nand_pins: serial-nand-pins {
547		mux {
548			function = "flash";
549			groups = "snfi";
550		};
551	};
552
553	uart0_pins: uart0-pins {
554		mux {
555			function = "uart";
556			groups = "uart0_0_tx_rx" ;
557		};
558	};
559
560	uart2_pins: uart2-pins {
561		mux {
562			function = "uart";
563			groups = "uart2_1_tx_rx" ;
564		};
565	};
566
567	watchdog_pins: watchdog-pins {
568		mux {
569			function = "watchdog";
570			groups = "watchdog";
571		};
572	};
573};
574
575&pwm {
576	pinctrl-names = "default";
577	pinctrl-0 = <&pwm_pins>;
578	status = "okay";
579};
580
581&pwrap {
582	pinctrl-names = "default";
583	pinctrl-0 = <&pmic_bus_pins>;
584
585	status = "okay";
586};
587
588&sata {
589	status = "disabled";
590};
591
592&sata_phy {
593	status = "disabled";
594};
595
596&spi0 {
597	pinctrl-names = "default";
598	pinctrl-0 = <&spic0_pins>;
599	status = "okay";
600};
601
602&spi1 {
603	pinctrl-names = "default";
604	pinctrl-0 = <&spic1_pins>;
605};
606
607&ssusb {
608	vusb33-supply = <&reg_3p3v>;
609	vbus-supply = <&reg_5v>;
610	status = "okay";
611};
612
613&u3phy {
614	status = "okay";
615};
616
617&uart0 {
618	pinctrl-names = "default";
619	pinctrl-0 = <&uart0_pins>;
620	status = "okay";
621};
622
623&uart2 {
624	pinctrl-names = "default";
625	pinctrl-0 = <&uart2_pins>;
626};
627
628&watchdog {
629	pinctrl-names = "default";
630	pinctrl-0 = <&watchdog_pins>;
631	status = "okay";
632};
633
634&wmac {
635	status = "okay";
636};
637