1/*
2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/gpio/gpio.h>
11
12#include "mt7622.dtsi"
13#include "mt6380.dtsi"
14
15/ {
16	model = "Bananapi BPI-R64";
17	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
18
19	chosen {
20		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
21	};
22
23	cpus {
24		cpu@0 {
25			proc-supply = <&mt6380_vcpu_reg>;
26			sram-supply = <&mt6380_vm_reg>;
27		};
28
29		cpu@1 {
30			proc-supply = <&mt6380_vcpu_reg>;
31			sram-supply = <&mt6380_vm_reg>;
32		};
33	};
34
35	gpio-keys {
36		compatible = "gpio-keys";
37
38		factory {
39			label = "factory";
40			linux,code = <BTN_0>;
41			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
42		};
43
44		wps {
45			label = "wps";
46			linux,code = <KEY_WPS_BUTTON>;
47			gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
48		};
49	};
50
51	leds {
52		compatible = "gpio-leds";
53
54		green {
55			label = "bpi-r64:pio:green";
56			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
57			default-state = "off";
58		};
59
60		red {
61			label = "bpi-r64:pio:red";
62			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
63			default-state = "off";
64		};
65	};
66
67	memory {
68		reg = <0 0x40000000 0 0x40000000>;
69	};
70
71	reg_1p8v: regulator-1p8v {
72		compatible = "regulator-fixed";
73		regulator-name = "fixed-1.8V";
74		regulator-min-microvolt = <1800000>;
75		regulator-max-microvolt = <1800000>;
76		regulator-always-on;
77	};
78
79	reg_3p3v: regulator-3p3v {
80		compatible = "regulator-fixed";
81		regulator-name = "fixed-3.3V";
82		regulator-min-microvolt = <3300000>;
83		regulator-max-microvolt = <3300000>;
84		regulator-boot-on;
85		regulator-always-on;
86	};
87
88	reg_5v: regulator-5v {
89		compatible = "regulator-fixed";
90		regulator-name = "fixed-5V";
91		regulator-min-microvolt = <5000000>;
92		regulator-max-microvolt = <5000000>;
93		regulator-boot-on;
94		regulator-always-on;
95	};
96};
97
98&bch {
99	status = "disabled";
100};
101
102&btif {
103	status = "okay";
104};
105
106&cir {
107	pinctrl-names = "default";
108	pinctrl-0 = <&irrx_pins>;
109	status = "okay";
110};
111
112&eth {
113	pinctrl-names = "default";
114	pinctrl-0 = <&eth_pins>;
115	status = "okay";
116
117	gmac1: mac@1 {
118		compatible = "mediatek,eth-mac";
119		reg = <1>;
120		phy-handle = <&phy5>;
121	};
122
123	mdio-bus {
124		#address-cells = <1>;
125		#size-cells = <0>;
126
127		phy5: ethernet-phy@5 {
128			reg = <5>;
129			phy-mode = "sgmii";
130		};
131	};
132};
133
134&i2c1 {
135	pinctrl-names = "default";
136	pinctrl-0 = <&i2c1_pins>;
137	status = "okay";
138};
139
140&i2c2 {
141	pinctrl-names = "default";
142	pinctrl-0 = <&i2c2_pins>;
143	status = "okay";
144};
145
146&mmc0 {
147	pinctrl-names = "default", "state_uhs";
148	pinctrl-0 = <&emmc_pins_default>;
149	pinctrl-1 = <&emmc_pins_uhs>;
150	status = "okay";
151	bus-width = <8>;
152	max-frequency = <50000000>;
153	cap-mmc-highspeed;
154	mmc-hs200-1_8v;
155	vmmc-supply = <&reg_3p3v>;
156	vqmmc-supply = <&reg_1p8v>;
157	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
158	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
159	non-removable;
160};
161
162&mmc1 {
163	pinctrl-names = "default", "state_uhs";
164	pinctrl-0 = <&sd0_pins_default>;
165	pinctrl-1 = <&sd0_pins_uhs>;
166	status = "okay";
167	bus-width = <4>;
168	max-frequency = <50000000>;
169	cap-sd-highspeed;
170	r_smpl = <1>;
171	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
172	vmmc-supply = <&reg_3p3v>;
173	vqmmc-supply = <&reg_3p3v>;
174	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
175	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
176};
177
178&nandc {
179	pinctrl-names = "default";
180	pinctrl-0 = <&parallel_nand_pins>;
181	status = "disabled";
182};
183
184&nor_flash {
185	pinctrl-names = "default";
186	pinctrl-0 = <&spi_nor_pins>;
187	status = "disabled";
188
189	flash@0 {
190		compatible = "jedec,spi-nor";
191		reg = <0>;
192	};
193};
194
195&pcie {
196	pinctrl-names = "default";
197	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
198	status = "okay";
199
200	pcie@0,0 {
201		status = "okay";
202	};
203
204	pcie@1,0 {
205		status = "okay";
206	};
207};
208
209&pio {
210	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
211	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
212	 */
213	asm_sel {
214		gpio-hog;
215		gpios = <90 GPIO_ACTIVE_HIGH>;
216		output-high;
217	};
218
219	/* eMMC is shared pin with parallel NAND */
220	emmc_pins_default: emmc-pins-default {
221		mux {
222			function = "emmc", "emmc_rst";
223			groups = "emmc";
224		};
225
226		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
227		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
228		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
229		 */
230		conf-cmd-dat {
231			pins = "NDL0", "NDL1", "NDL2",
232			       "NDL3", "NDL4", "NDL5",
233			       "NDL6", "NDL7", "NRB";
234			input-enable;
235			bias-pull-up;
236		};
237
238		conf-clk {
239			pins = "NCLE";
240			bias-pull-down;
241		};
242	};
243
244	emmc_pins_uhs: emmc-pins-uhs {
245		mux {
246			function = "emmc";
247			groups = "emmc";
248		};
249
250		conf-cmd-dat {
251			pins = "NDL0", "NDL1", "NDL2",
252			       "NDL3", "NDL4", "NDL5",
253			       "NDL6", "NDL7", "NRB";
254			input-enable;
255			drive-strength = <4>;
256			bias-pull-up;
257		};
258
259		conf-clk {
260			pins = "NCLE";
261			drive-strength = <4>;
262			bias-pull-down;
263		};
264	};
265
266	eth_pins: eth-pins {
267		mux {
268			function = "eth";
269			groups = "mdc_mdio", "rgmii_via_gmac2";
270		};
271	};
272
273	i2c1_pins: i2c1-pins {
274		mux {
275			function = "i2c";
276			groups =  "i2c1_0";
277		};
278	};
279
280	i2c2_pins: i2c2-pins {
281		mux {
282			function = "i2c";
283			groups =  "i2c2_0";
284		};
285	};
286
287	i2s1_pins: i2s1-pins {
288		mux {
289			function = "i2s";
290			groups =  "i2s_out_mclk_bclk_ws",
291				  "i2s1_in_data",
292				  "i2s1_out_data";
293		};
294
295		conf {
296			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
297			       "I2S_WS", "I2S_MCLK";
298			drive-strength = <12>;
299			bias-pull-down;
300		};
301	};
302
303	irrx_pins: irrx-pins {
304		mux {
305			function = "ir";
306			groups =  "ir_1_rx";
307		};
308	};
309
310	irtx_pins: irtx-pins {
311		mux {
312			function = "ir";
313			groups =  "ir_1_tx";
314		};
315	};
316
317	/* Parallel nand is shared pin with eMMC */
318	parallel_nand_pins: parallel-nand-pins {
319		mux {
320			function = "flash";
321			groups = "par_nand";
322		};
323	};
324
325	pcie0_pins: pcie0-pins {
326		mux {
327			function = "pcie";
328			groups = "pcie0_pad_perst",
329				 "pcie0_1_waken",
330				 "pcie0_1_clkreq";
331		};
332	};
333
334	pcie1_pins: pcie1-pins {
335		mux {
336			function = "pcie";
337			groups = "pcie1_pad_perst",
338				 "pcie1_0_waken",
339				 "pcie1_0_clkreq";
340		};
341	};
342
343	pmic_bus_pins: pmic-bus-pins {
344		mux {
345			function = "pmic";
346			groups = "pmic_bus";
347		};
348	};
349
350	pwm7_pins: pwm1-2-pins {
351		mux {
352			function = "pwm";
353			groups = "pwm_ch7_2";
354		};
355	};
356
357	wled_pins: wled-pins {
358		mux {
359			function = "led";
360			groups = "wled";
361		};
362	};
363
364	sd0_pins_default: sd0-pins-default {
365		mux {
366			function = "sd";
367			groups = "sd_0";
368		};
369
370		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
371		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
372		 *  DAT2, DAT3, CMD, CLK for SD respectively.
373		 */
374		conf-cmd-data {
375			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
376			       "I2S2_IN","I2S4_OUT";
377			input-enable;
378			drive-strength = <8>;
379			bias-pull-up;
380		};
381		conf-clk {
382			pins = "I2S3_OUT";
383			drive-strength = <12>;
384			bias-pull-down;
385		};
386		conf-cd {
387			pins = "TXD3";
388			bias-pull-up;
389		};
390	};
391
392	sd0_pins_uhs: sd0-pins-uhs {
393		mux {
394			function = "sd";
395			groups = "sd_0";
396		};
397
398		conf-cmd-data {
399			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
400			       "I2S2_IN","I2S4_OUT";
401			input-enable;
402			bias-pull-up;
403		};
404
405		conf-clk {
406			pins = "I2S3_OUT";
407			bias-pull-down;
408		};
409	};
410
411	/* Serial NAND is shared pin with SPI-NOR */
412	serial_nand_pins: serial-nand-pins {
413		mux {
414			function = "flash";
415			groups = "snfi";
416		};
417	};
418
419	spic0_pins: spic0-pins {
420		mux {
421			function = "spi";
422			groups = "spic0_0";
423		};
424	};
425
426	spic1_pins: spic1-pins {
427		mux {
428			function = "spi";
429			groups = "spic1_0";
430		};
431	};
432
433	/* SPI-NOR is shared pin with serial NAND */
434	spi_nor_pins: spi-nor-pins {
435		mux {
436			function = "flash";
437			groups = "spi_nor";
438		};
439	};
440
441	/* serial NAND is shared pin with SPI-NOR */
442	serial_nand_pins: serial-nand-pins {
443		mux {
444			function = "flash";
445			groups = "snfi";
446		};
447	};
448
449	uart0_pins: uart0-pins {
450		mux {
451			function = "uart";
452			groups = "uart0_0_tx_rx" ;
453		};
454	};
455
456	uart2_pins: uart2-pins {
457		mux {
458			function = "uart";
459			groups = "uart2_1_tx_rx" ;
460		};
461	};
462
463	watchdog_pins: watchdog-pins {
464		mux {
465			function = "watchdog";
466			groups = "watchdog";
467		};
468	};
469};
470
471&pwm {
472	pinctrl-names = "default";
473	pinctrl-0 = <&pwm7_pins>;
474	status = "okay";
475};
476
477&pwrap {
478	pinctrl-names = "default";
479	pinctrl-0 = <&pmic_bus_pins>;
480
481	status = "okay";
482};
483
484&sata {
485	status = "disable";
486};
487
488&sata_phy {
489	status = "disable";
490};
491
492&spi0 {
493	pinctrl-names = "default";
494	pinctrl-0 = <&spic0_pins>;
495	status = "okay";
496};
497
498&spi1 {
499	pinctrl-names = "default";
500	pinctrl-0 = <&spic1_pins>;
501	status = "okay";
502};
503
504&ssusb {
505	vusb33-supply = <&reg_3p3v>;
506	vbus-supply = <&reg_5v>;
507	status = "okay";
508};
509
510&u3phy {
511	status = "okay";
512};
513
514&uart0 {
515	pinctrl-names = "default";
516	pinctrl-0 = <&uart0_pins>;
517	status = "okay";
518};
519
520&uart2 {
521	pinctrl-names = "default";
522	pinctrl-0 = <&uart2_pins>;
523	status = "okay";
524};
525
526&watchdog {
527	pinctrl-names = "default";
528	pinctrl-0 = <&watchdog_pins>;
529	status = "okay";
530};
531