1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Mars.C <mars.cheng@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
10
11/ {
12	compatible = "mediatek,mt6795";
13	interrupt-parent = <&sysirq>;
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	psci {
18		compatible = "arm,psci-0.2";
19		method = "smc";
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu0: cpu@0 {
27			device_type = "cpu";
28			compatible = "arm,cortex-a53";
29			enable-method = "psci";
30			reg = <0x000>;
31			cci-control-port = <&cci_control2>;
32			next-level-cache = <&l2_0>;
33		};
34
35		cpu1: cpu@1 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a53";
38			enable-method = "psci";
39			reg = <0x001>;
40			cci-control-port = <&cci_control2>;
41			next-level-cache = <&l2_0>;
42		};
43
44		cpu2: cpu@2 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a53";
47			enable-method = "psci";
48			reg = <0x002>;
49			cci-control-port = <&cci_control2>;
50			next-level-cache = <&l2_0>;
51		};
52
53		cpu3: cpu@3 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a53";
56			enable-method = "psci";
57			reg = <0x003>;
58			cci-control-port = <&cci_control2>;
59			next-level-cache = <&l2_0>;
60		};
61
62		cpu4: cpu@100 {
63			device_type = "cpu";
64			compatible = "arm,cortex-a53";
65			enable-method = "psci";
66			reg = <0x100>;
67			cci-control-port = <&cci_control1>;
68			next-level-cache = <&l2_1>;
69		};
70
71		cpu5: cpu@101 {
72			device_type = "cpu";
73			compatible = "arm,cortex-a53";
74			enable-method = "psci";
75			reg = <0x101>;
76			cci-control-port = <&cci_control1>;
77			next-level-cache = <&l2_1>;
78		};
79
80		cpu6: cpu@102 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a53";
83			enable-method = "psci";
84			reg = <0x102>;
85			cci-control-port = <&cci_control1>;
86			next-level-cache = <&l2_1>;
87		};
88
89		cpu7: cpu@103 {
90			device_type = "cpu";
91			compatible = "arm,cortex-a53";
92			enable-method = "psci";
93			reg = <0x103>;
94			cci-control-port = <&cci_control1>;
95			next-level-cache = <&l2_1>;
96		};
97
98		cpu-map {
99			cluster0 {
100				core0 {
101					cpu = <&cpu0>;
102				};
103
104				core1 {
105					cpu = <&cpu1>;
106				};
107
108				core2 {
109					cpu = <&cpu2>;
110				};
111
112				core3 {
113					cpu = <&cpu3>;
114				};
115			};
116
117			cluster1 {
118				core0 {
119					cpu = <&cpu4>;
120				};
121
122				core1 {
123					cpu = <&cpu5>;
124				};
125
126				core2 {
127					cpu = <&cpu6>;
128				};
129
130				core3 {
131					cpu = <&cpu7>;
132				};
133			};
134		};
135
136		l2_0: l2-cache0 {
137			compatible = "cache";
138			cache-level = <2>;
139		};
140
141		l2_1: l2-cache1 {
142			compatible = "cache";
143			cache-level = <2>;
144		};
145	};
146
147	clk26m: oscillator-26m {
148		compatible = "fixed-clock";
149		#clock-cells = <0>;
150		clock-frequency = <26000000>;
151		clock-output-names = "clk26m";
152	};
153
154	clk32k: oscillator-32k {
155		compatible = "fixed-clock";
156		#clock-cells = <0>;
157		clock-frequency = <32000>;
158		clock-output-names = "clk32k";
159	};
160
161	system_clk: dummy13m {
162		compatible = "fixed-clock";
163		clock-frequency = <13000000>;
164		#clock-cells = <0>;
165	};
166
167	pmu {
168		compatible = "arm,cortex-a53-pmu";
169		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
170			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
171			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
172			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
173		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
174	};
175
176	timer {
177		compatible = "arm,armv8-timer";
178		interrupt-parent = <&gic>;
179		interrupts = <GIC_PPI 13
180			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
181			     <GIC_PPI 14
182			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
183			     <GIC_PPI 11
184			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
185			     <GIC_PPI 10
186			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
187	};
188
189	soc {
190		#address-cells = <2>;
191		#size-cells = <2>;
192		compatible = "simple-bus";
193		ranges;
194
195		pio: pinctrl@10005000 {
196			compatible = "mediatek,mt6795-pinctrl";
197			reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
198			reg-names = "base", "eint";
199			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
200				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
201			gpio-controller;
202			#gpio-cells = <2>;
203			gpio-ranges = <&pio 0 0 196>;
204			interrupt-controller;
205			#interrupt-cells = <2>;
206		};
207
208		watchdog: watchdog@10007000 {
209			compatible = "mediatek,mt6795-wdt";
210			reg = <0 0x10007000 0 0x100>;
211			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
212			#reset-cells = <1>;
213			timeout-sec = <20>;
214		};
215
216		timer: timer@10008000 {
217			compatible = "mediatek,mt6795-timer",
218				     "mediatek,mt6577-timer";
219			reg = <0 0x10008000 0 0x1000>;
220			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
221			clocks = <&system_clk>, <&clk32k>;
222		};
223
224		sysirq: intpol-controller@10200620 {
225			compatible = "mediatek,mt6795-sysirq",
226				     "mediatek,mt6577-sysirq";
227			interrupt-controller;
228			#interrupt-cells = <3>;
229			interrupt-parent = <&gic>;
230			reg = <0 0x10200620 0 0x20>;
231		};
232
233		systimer: timer@10200670 {
234			compatible = "mediatek,mt6795-systimer";
235			reg = <0 0x10200670 0 0x10>;
236			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
237			clocks = <&system_clk>;
238			clock-names = "clk13m";
239		};
240
241		gic: interrupt-controller@10221000 {
242			compatible = "arm,gic-400";
243			#interrupt-cells = <3>;
244			interrupt-parent = <&gic>;
245			interrupt-controller;
246			reg = <0 0x10221000 0 0x1000>,
247			      <0 0x10222000 0 0x2000>,
248			      <0 0x10224000 0 0x2000>,
249			      <0 0x10226000 0 0x2000>;
250			interrupts = <GIC_PPI 9
251				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
252		};
253
254		cci: cci@10390000 {
255			compatible = "arm,cci-400";
256			#address-cells = <1>;
257			#size-cells = <1>;
258			reg = <0 0x10390000 0 0x1000>;
259			ranges = <0 0 0x10390000 0x10000>;
260
261			cci_control0: slave-if@1000 {
262				compatible = "arm,cci-400-ctrl-if";
263				interface-type = "ace-lite";
264				reg = <0x1000 0x1000>;
265			};
266
267			cci_control1: slave-if@4000 {
268				compatible = "arm,cci-400-ctrl-if";
269				interface-type = "ace";
270				reg = <0x4000 0x1000>;
271			};
272
273			cci_control2: slave-if@5000 {
274				compatible = "arm,cci-400-ctrl-if";
275				interface-type = "ace";
276				reg = <0x5000 0x1000>;
277			};
278
279			pmu@9000 {
280				compatible = "arm,cci-400-pmu,r1";
281				reg = <0x9000 0x5000>;
282				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
283					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
284					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
285					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
286					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
287			};
288		};
289
290		uart0: serial@11002000 {
291			compatible = "mediatek,mt6795-uart",
292				     "mediatek,mt6577-uart";
293			reg = <0 0x11002000 0 0x400>;
294			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
295			clocks = <&clk26m>;
296			status = "disabled";
297		};
298
299		uart1: serial@11003000 {
300			compatible = "mediatek,mt6795-uart",
301				     "mediatek,mt6577-uart";
302			reg = <0 0x11003000 0 0x400>;
303			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
304			clocks = <&clk26m>;
305			status = "disabled";
306		};
307
308		uart2: serial@11004000 {
309			compatible = "mediatek,mt6795-uart",
310				     "mediatek,mt6577-uart";
311			reg = <0 0x11004000 0 0x400>;
312			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
313			clocks = <&clk26m>;
314			status = "disabled";
315		};
316
317		uart3: serial@11005000 {
318			compatible = "mediatek,mt6795-uart",
319				     "mediatek,mt6577-uart";
320			reg = <0 0x11005000 0 0x400>;
321			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
322			clocks = <&clk26m>;
323			status = "disabled";
324		};
325	};
326};
327