1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: YT Shen <yt.shen@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8#include <dt-bindings/clock/mt2712-clk.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/memory/mt2712-larb-port.h>
12#include <dt-bindings/phy/phy.h>
13#include <dt-bindings/power/mt2712-power.h>
14#include "mt2712-pinfunc.h"
15
16/ {
17	compatible = "mediatek,mt2712";
18	interrupt-parent = <&sysirq>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	cluster0_opp: opp-table-0 {
23		compatible = "operating-points-v2";
24		opp-shared;
25		opp00 {
26			opp-hz = /bits/ 64 <598000000>;
27			opp-microvolt = <1000000>;
28		};
29		opp01 {
30			opp-hz = /bits/ 64 <702000000>;
31			opp-microvolt = <1000000>;
32		};
33		opp02 {
34			opp-hz = /bits/ 64 <793000000>;
35			opp-microvolt = <1000000>;
36		};
37	};
38
39	cluster1_opp: opp-table-1 {
40		compatible = "operating-points-v2";
41		opp-shared;
42		opp00 {
43			opp-hz = /bits/ 64 <598000000>;
44			opp-microvolt = <1000000>;
45		};
46		opp01 {
47			opp-hz = /bits/ 64 <702000000>;
48			opp-microvolt = <1000000>;
49		};
50		opp02 {
51			opp-hz = /bits/ 64 <793000000>;
52			opp-microvolt = <1000000>;
53		};
54		opp03 {
55			opp-hz = /bits/ 64 <897000000>;
56			opp-microvolt = <1000000>;
57		};
58		opp04 {
59			opp-hz = /bits/ 64 <1001000000>;
60			opp-microvolt = <1000000>;
61		};
62	};
63
64	cpus {
65		#address-cells = <1>;
66		#size-cells = <0>;
67
68		cpu-map {
69			cluster0 {
70				core0 {
71					cpu = <&cpu0>;
72				};
73				core1 {
74					cpu = <&cpu1>;
75				};
76			};
77
78			cluster1 {
79				core0 {
80					cpu = <&cpu2>;
81				};
82			};
83		};
84
85		cpu0: cpu@0 {
86			device_type = "cpu";
87			compatible = "arm,cortex-a35";
88			reg = <0x000>;
89			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
90				<&topckgen CLK_TOP_F_MP0_PLL1>;
91			clock-names = "cpu", "intermediate";
92			proc-supply = <&cpus_fixed_vproc0>;
93			operating-points-v2 = <&cluster0_opp>;
94			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
95		};
96
97		cpu1: cpu@1 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a35";
100			reg = <0x001>;
101			enable-method = "psci";
102			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
103				<&topckgen CLK_TOP_F_MP0_PLL1>;
104			clock-names = "cpu", "intermediate";
105			proc-supply = <&cpus_fixed_vproc0>;
106			operating-points-v2 = <&cluster0_opp>;
107			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
108		};
109
110		cpu2: cpu@200 {
111			device_type = "cpu";
112			compatible = "arm,cortex-a72";
113			reg = <0x200>;
114			enable-method = "psci";
115			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
116				<&topckgen CLK_TOP_F_BIG_PLL1>;
117			clock-names = "cpu", "intermediate";
118			proc-supply = <&cpus_fixed_vproc1>;
119			operating-points-v2 = <&cluster1_opp>;
120			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
121		};
122
123		idle-states {
124			entry-method = "psci";
125
126			CPU_SLEEP_0: cpu-sleep-0 {
127				compatible = "arm,idle-state";
128				local-timer-stop;
129				entry-latency-us = <100>;
130				exit-latency-us = <80>;
131				min-residency-us = <2000>;
132				arm,psci-suspend-param = <0x0010000>;
133			};
134
135			CLUSTER_SLEEP_0: cluster-sleep-0 {
136				compatible = "arm,idle-state";
137				local-timer-stop;
138				entry-latency-us = <350>;
139				exit-latency-us = <80>;
140				min-residency-us = <3000>;
141				arm,psci-suspend-param = <0x1010000>;
142			};
143		};
144	};
145
146	psci {
147		compatible = "arm,psci-0.2";
148		method = "smc";
149	};
150
151	baud_clk: dummy26m {
152		compatible = "fixed-clock";
153		clock-frequency = <26000000>;
154		#clock-cells = <0>;
155	};
156
157	sys_clk: dummyclk {
158		compatible = "fixed-clock";
159		clock-frequency = <26000000>;
160		#clock-cells = <0>;
161	};
162
163	clk26m: oscillator@0 {
164		compatible = "fixed-clock";
165		#clock-cells = <0>;
166		clock-frequency = <26000000>;
167		clock-output-names = "clk26m";
168	};
169
170	clk32k: oscillator@1 {
171		compatible = "fixed-clock";
172		#clock-cells = <0>;
173		clock-frequency = <32768>;
174		clock-output-names = "clk32k";
175	};
176
177	clkfpc: oscillator@2 {
178		compatible = "fixed-clock";
179		#clock-cells = <0>;
180		clock-frequency = <50000000>;
181		clock-output-names = "clkfpc";
182	};
183
184	clkaud_ext_i_0: oscillator@3 {
185		compatible = "fixed-clock";
186		#clock-cells = <0>;
187		clock-frequency = <6500000>;
188		clock-output-names = "clkaud_ext_i_0";
189	};
190
191	clkaud_ext_i_1: oscillator@4 {
192		compatible = "fixed-clock";
193		#clock-cells = <0>;
194		clock-frequency = <196608000>;
195		clock-output-names = "clkaud_ext_i_1";
196	};
197
198	clkaud_ext_i_2: oscillator@5 {
199		compatible = "fixed-clock";
200		#clock-cells = <0>;
201		clock-frequency = <180633600>;
202		clock-output-names = "clkaud_ext_i_2";
203	};
204
205	clki2si0_mck_i: oscillator@6 {
206		compatible = "fixed-clock";
207		#clock-cells = <0>;
208		clock-frequency = <30000000>;
209		clock-output-names = "clki2si0_mck_i";
210	};
211
212	clki2si1_mck_i: oscillator@7 {
213		compatible = "fixed-clock";
214		#clock-cells = <0>;
215		clock-frequency = <30000000>;
216		clock-output-names = "clki2si1_mck_i";
217	};
218
219	clki2si2_mck_i: oscillator@8 {
220		compatible = "fixed-clock";
221		#clock-cells = <0>;
222		clock-frequency = <30000000>;
223		clock-output-names = "clki2si2_mck_i";
224	};
225
226	clktdmin_mclk_i: oscillator@9 {
227		compatible = "fixed-clock";
228		#clock-cells = <0>;
229		clock-frequency = <30000000>;
230		clock-output-names = "clktdmin_mclk_i";
231	};
232
233	timer {
234		compatible = "arm,armv8-timer";
235		interrupt-parent = <&gic>;
236		interrupts = <GIC_PPI 13
237			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
238			     <GIC_PPI 14
239			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
240			     <GIC_PPI 11
241			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
242			     <GIC_PPI 10
243			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
244	};
245
246	topckgen: syscon@10000000 {
247		compatible = "mediatek,mt2712-topckgen", "syscon";
248		reg = <0 0x10000000 0 0x1000>;
249		#clock-cells = <1>;
250	};
251
252	infracfg: syscon@10001000 {
253		compatible = "mediatek,mt2712-infracfg", "syscon";
254		reg = <0 0x10001000 0 0x1000>;
255		#clock-cells = <1>;
256	};
257
258	pericfg: syscon@10003000 {
259		compatible = "mediatek,mt2712-pericfg", "syscon";
260		reg = <0 0x10003000 0 0x1000>;
261		#clock-cells = <1>;
262	};
263
264	syscfg_pctl_a: syscfg_pctl_a@10005000 {
265		compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
266		reg = <0 0x10005000 0 0x1000>;
267	};
268
269	pio: pinctrl@10005000 {
270		compatible = "mediatek,mt2712-pinctrl";
271		reg = <0 0x1000b000 0 0x1000>;
272		mediatek,pctl-regmap = <&syscfg_pctl_a>;
273		pins-are-numbered;
274		gpio-controller;
275		#gpio-cells = <2>;
276		interrupt-controller;
277		#interrupt-cells = <2>;
278		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
279	};
280
281	scpsys: power-controller@10006000 {
282		compatible = "mediatek,mt2712-scpsys", "syscon";
283		#power-domain-cells = <1>;
284		reg = <0 0x10006000 0 0x1000>;
285		clocks = <&topckgen CLK_TOP_MM_SEL>,
286			 <&topckgen CLK_TOP_MFG_SEL>,
287			 <&topckgen CLK_TOP_VENC_SEL>,
288			 <&topckgen CLK_TOP_JPGDEC_SEL>,
289			 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
290			 <&topckgen CLK_TOP_VDEC_SEL>;
291		clock-names = "mm", "mfg", "venc",
292			"jpgdec", "audio", "vdec";
293		infracfg = <&infracfg>;
294	};
295
296	uart5: serial@1000f000 {
297		compatible = "mediatek,mt2712-uart",
298			     "mediatek,mt6577-uart";
299		reg = <0 0x1000f000 0 0x400>;
300		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
301		clocks = <&baud_clk>, <&sys_clk>;
302		clock-names = "baud", "bus";
303		dmas = <&apdma 10
304			&apdma 11>;
305		dma-names = "tx", "rx";
306		status = "disabled";
307	};
308
309	rtc: rtc@10011000 {
310		compatible = "mediatek,mt2712-rtc";
311		reg = <0 0x10011000 0 0x1000>;
312		interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
313	};
314
315	spis1: spi@10013000 {
316		compatible = "mediatek,mt2712-spi-slave";
317		reg = <0 0x10013000 0 0x100>;
318		interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
319		clocks = <&infracfg CLK_INFRA_AO_SPI1>;
320		clock-names = "spi";
321		assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
322		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
323		status = "disabled";
324	};
325
326	iommu0: iommu@10205000 {
327		compatible = "mediatek,mt2712-m4u";
328		reg = <0 0x10205000 0 0x1000>;
329		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
330		clocks = <&infracfg CLK_INFRA_M4U>;
331		clock-names = "bclk";
332		mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
333				 <&larb3>, <&larb6>;
334		#iommu-cells = <1>;
335	};
336
337	apmixedsys: syscon@10209000 {
338		compatible = "mediatek,mt2712-apmixedsys", "syscon";
339		reg = <0 0x10209000 0 0x1000>;
340		#clock-cells = <1>;
341	};
342
343	iommu1: iommu@1020a000 {
344		compatible = "mediatek,mt2712-m4u";
345		reg = <0 0x1020a000 0 0x1000>;
346		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
347		clocks = <&infracfg CLK_INFRA_M4U>;
348		clock-names = "bclk";
349		mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
350		#iommu-cells = <1>;
351	};
352
353	mcucfg: syscon@10220000 {
354		compatible = "mediatek,mt2712-mcucfg", "syscon";
355		reg = <0 0x10220000 0 0x1000>;
356		#clock-cells = <1>;
357	};
358
359	sysirq: interrupt-controller@10220a80 {
360		compatible = "mediatek,mt2712-sysirq",
361			     "mediatek,mt6577-sysirq";
362		interrupt-controller;
363		#interrupt-cells = <3>;
364		interrupt-parent = <&gic>;
365		reg = <0 0x10220a80 0 0x40>;
366	};
367
368	gic: interrupt-controller@10510000 {
369		compatible = "arm,gic-400";
370		#interrupt-cells = <3>;
371		interrupt-parent = <&gic>;
372		interrupt-controller;
373		reg = <0 0x10510000 0 0x10000>,
374		      <0 0x10520000 0 0x20000>,
375		      <0 0x10540000 0 0x20000>,
376		      <0 0x10560000 0 0x20000>;
377		interrupts = <GIC_PPI 9
378			 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
379	};
380
381	apdma: dma-controller@11000400 {
382		compatible = "mediatek,mt2712-uart-dma",
383			     "mediatek,mt6577-uart-dma";
384		reg = <0 0x11000400 0 0x80>,
385		      <0 0x11000480 0 0x80>,
386		      <0 0x11000500 0 0x80>,
387		      <0 0x11000580 0 0x80>,
388		      <0 0x11000600 0 0x80>,
389		      <0 0x11000680 0 0x80>,
390		      <0 0x11000700 0 0x80>,
391		      <0 0x11000780 0 0x80>,
392		      <0 0x11000800 0 0x80>,
393		      <0 0x11000880 0 0x80>,
394		      <0 0x11000900 0 0x80>,
395		      <0 0x11000980 0 0x80>;
396		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
397			     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
398			     <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
399			     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
400			     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
401			     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
402			     <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
403			     <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
404			     <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
405			     <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
406			     <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
407			     <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
408		dma-requests = <12>;
409		clocks = <&pericfg CLK_PERI_AP_DMA>;
410		clock-names = "apdma";
411		#dma-cells = <1>;
412	};
413
414	auxadc: adc@11001000 {
415		compatible = "mediatek,mt2712-auxadc";
416		reg = <0 0x11001000 0 0x1000>;
417		clocks = <&pericfg CLK_PERI_AUXADC>;
418		clock-names = "main";
419		#io-channel-cells = <1>;
420		status = "disabled";
421	};
422
423	uart0: serial@11002000 {
424		compatible = "mediatek,mt2712-uart",
425			     "mediatek,mt6577-uart";
426		reg = <0 0x11002000 0 0x400>;
427		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
428		clocks = <&baud_clk>, <&sys_clk>;
429		clock-names = "baud", "bus";
430		dmas = <&apdma 0
431			&apdma 1>;
432		dma-names = "tx", "rx";
433		status = "disabled";
434	};
435
436	uart1: serial@11003000 {
437		compatible = "mediatek,mt2712-uart",
438			     "mediatek,mt6577-uart";
439		reg = <0 0x11003000 0 0x400>;
440		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
441		clocks = <&baud_clk>, <&sys_clk>;
442		clock-names = "baud", "bus";
443		dmas = <&apdma 2
444			&apdma 3>;
445		dma-names = "tx", "rx";
446		status = "disabled";
447	};
448
449	uart2: serial@11004000 {
450		compatible = "mediatek,mt2712-uart",
451			     "mediatek,mt6577-uart";
452		reg = <0 0x11004000 0 0x400>;
453		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
454		clocks = <&baud_clk>, <&sys_clk>;
455		clock-names = "baud", "bus";
456		dmas = <&apdma 4
457			&apdma 5>;
458		dma-names = "tx", "rx";
459		status = "disabled";
460	};
461
462	uart3: serial@11005000 {
463		compatible = "mediatek,mt2712-uart",
464			     "mediatek,mt6577-uart";
465		reg = <0 0x11005000 0 0x400>;
466		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
467		clocks = <&baud_clk>, <&sys_clk>;
468		clock-names = "baud", "bus";
469		dmas = <&apdma 6
470			&apdma 7>;
471		dma-names = "tx", "rx";
472		status = "disabled";
473	};
474
475	pwm: pwm@11006000 {
476		compatible = "mediatek,mt2712-pwm";
477		reg = <0 0x11006000 0 0x1000>;
478		#pwm-cells = <2>;
479		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
480		clocks = <&topckgen CLK_TOP_PWM_SEL>,
481			 <&pericfg CLK_PERI_PWM>,
482			 <&pericfg CLK_PERI_PWM0>,
483			 <&pericfg CLK_PERI_PWM1>,
484			 <&pericfg CLK_PERI_PWM2>,
485			 <&pericfg CLK_PERI_PWM3>,
486			 <&pericfg CLK_PERI_PWM4>,
487			 <&pericfg CLK_PERI_PWM5>,
488			 <&pericfg CLK_PERI_PWM6>,
489			 <&pericfg CLK_PERI_PWM7>;
490		clock-names = "top",
491			      "main",
492			      "pwm1",
493			      "pwm2",
494			      "pwm3",
495			      "pwm4",
496			      "pwm5",
497			      "pwm6",
498			      "pwm7",
499			      "pwm8";
500		status = "disabled";
501	};
502
503	i2c0: i2c@11007000 {
504		compatible = "mediatek,mt2712-i2c";
505		reg = <0 0x11007000 0 0x90>,
506		      <0 0x11000180 0 0x80>;
507		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
508		clock-div = <4>;
509		clocks = <&pericfg CLK_PERI_I2C0>,
510			 <&pericfg CLK_PERI_AP_DMA>;
511		clock-names = "main",
512			      "dma";
513		#address-cells = <1>;
514		#size-cells = <0>;
515		status = "disabled";
516	};
517
518	i2c1: i2c@11008000 {
519		compatible = "mediatek,mt2712-i2c";
520		reg = <0 0x11008000 0 0x90>,
521		      <0 0x11000200 0 0x80>;
522		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
523		clock-div = <4>;
524		clocks = <&pericfg CLK_PERI_I2C1>,
525			 <&pericfg CLK_PERI_AP_DMA>;
526		clock-names = "main",
527			      "dma";
528		#address-cells = <1>;
529		#size-cells = <0>;
530		status = "disabled";
531	};
532
533	i2c2: i2c@11009000 {
534		compatible = "mediatek,mt2712-i2c";
535		reg = <0 0x11009000 0 0x90>,
536		      <0 0x11000280 0 0x80>;
537		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
538		clock-div = <4>;
539		clocks = <&pericfg CLK_PERI_I2C2>,
540			 <&pericfg CLK_PERI_AP_DMA>;
541		clock-names = "main",
542			      "dma";
543		#address-cells = <1>;
544		#size-cells = <0>;
545		status = "disabled";
546	};
547
548	spi0: spi@1100a000 {
549		compatible = "mediatek,mt2712-spi";
550		#address-cells = <1>;
551		#size-cells = <0>;
552		reg = <0 0x1100a000 0 0x100>;
553		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
554		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
555			 <&topckgen CLK_TOP_SPI_SEL>,
556			 <&pericfg CLK_PERI_SPI0>;
557		clock-names = "parent-clk", "sel-clk", "spi-clk";
558		status = "disabled";
559	};
560
561	nandc: nfi@1100e000 {
562		compatible = "mediatek,mt2712-nfc";
563		reg = <0 0x1100e000 0 0x1000>;
564		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
565		clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
566		clock-names = "nfi_clk", "pad_clk";
567		ecc-engine = <&bch>;
568		#address-cells = <1>;
569		#size-cells = <0>;
570		status = "disabled";
571	};
572
573	bch: ecc@1100f000 {
574		compatible = "mediatek,mt2712-ecc";
575		reg = <0 0x1100f000 0 0x1000>;
576		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
577		clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
578		clock-names = "nfiecc_clk";
579		status = "disabled";
580	};
581
582	i2c3: i2c@11010000 {
583		compatible = "mediatek,mt2712-i2c";
584		reg = <0 0x11010000 0 0x90>,
585		      <0 0x11000300 0 0x80>;
586		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
587		clock-div = <4>;
588		clocks = <&pericfg CLK_PERI_I2C3>,
589			 <&pericfg CLK_PERI_AP_DMA>;
590		clock-names = "main",
591			      "dma";
592		#address-cells = <1>;
593		#size-cells = <0>;
594		status = "disabled";
595	};
596
597	i2c4: i2c@11011000 {
598		compatible = "mediatek,mt2712-i2c";
599		reg = <0 0x11011000 0 0x90>,
600		      <0 0x11000380 0 0x80>;
601		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
602		clock-div = <4>;
603		clocks = <&pericfg CLK_PERI_I2C4>,
604			 <&pericfg CLK_PERI_AP_DMA>;
605		clock-names = "main",
606			      "dma";
607		#address-cells = <1>;
608		#size-cells = <0>;
609		status = "disabled";
610	};
611
612	i2c5: i2c@11013000 {
613		compatible = "mediatek,mt2712-i2c";
614		reg = <0 0x11013000 0 0x90>,
615		      <0 0x11000100 0 0x80>;
616		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
617		clock-div = <4>;
618		clocks = <&pericfg CLK_PERI_I2C5>,
619			 <&pericfg CLK_PERI_AP_DMA>;
620		clock-names = "main",
621			      "dma";
622		#address-cells = <1>;
623		#size-cells = <0>;
624		status = "disabled";
625	};
626
627	spi2: spi@11015000 {
628		compatible = "mediatek,mt2712-spi";
629		#address-cells = <1>;
630		#size-cells = <0>;
631		reg = <0 0x11015000 0 0x100>;
632		interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>;
633		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
634			 <&topckgen CLK_TOP_SPI_SEL>,
635			 <&pericfg CLK_PERI_SPI2>;
636		clock-names = "parent-clk", "sel-clk", "spi-clk";
637		status = "disabled";
638	};
639
640	spi3: spi@11016000 {
641		compatible = "mediatek,mt2712-spi";
642		#address-cells = <1>;
643		#size-cells = <0>;
644		reg = <0 0x11016000 0 0x100>;
645		interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
646		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
647			 <&topckgen CLK_TOP_SPI_SEL>,
648			 <&pericfg CLK_PERI_SPI3>;
649		clock-names = "parent-clk", "sel-clk", "spi-clk";
650		status = "disabled";
651	};
652
653	spi4: spi@10012000 {
654		compatible = "mediatek,mt2712-spi";
655		#address-cells = <1>;
656		#size-cells = <0>;
657		reg = <0 0x10012000 0 0x100>;
658		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>;
659		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
660			 <&topckgen CLK_TOP_SPI_SEL>,
661			 <&infracfg CLK_INFRA_AO_SPI0>;
662		clock-names = "parent-clk", "sel-clk", "spi-clk";
663		status = "disabled";
664	};
665
666	spi5: spi@11018000 {
667		compatible = "mediatek,mt2712-spi";
668		#address-cells = <1>;
669		#size-cells = <0>;
670		reg = <0 0x11018000 0 0x100>;
671		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>;
672		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
673			 <&topckgen CLK_TOP_SPI_SEL>,
674			 <&pericfg CLK_PERI_SPI5>;
675		clock-names = "parent-clk", "sel-clk", "spi-clk";
676		status = "disabled";
677	};
678
679	uart4: serial@11019000 {
680		compatible = "mediatek,mt2712-uart",
681			     "mediatek,mt6577-uart";
682		reg = <0 0x11019000 0 0x400>;
683		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
684		clocks = <&baud_clk>, <&sys_clk>;
685		clock-names = "baud", "bus";
686		dmas = <&apdma 8
687			&apdma 9>;
688		dma-names = "tx", "rx";
689		status = "disabled";
690	};
691
692	stmmac_axi_setup: stmmac-axi-config {
693		snps,wr_osr_lmt = <0x7>;
694		snps,rd_osr_lmt = <0x7>;
695		snps,blen = <0 0 0 0 16 8 4>;
696	};
697
698	mtl_rx_setup: rx-queues-config {
699		snps,rx-queues-to-use = <1>;
700		snps,rx-sched-sp;
701		queue0 {
702			snps,dcb-algorithm;
703			snps,map-to-dma-channel = <0x0>;
704			snps,priority = <0x0>;
705		};
706	};
707
708	mtl_tx_setup: tx-queues-config {
709		snps,tx-queues-to-use = <3>;
710		snps,tx-sched-wrr;
711		queue0 {
712			snps,weight = <0x10>;
713			snps,dcb-algorithm;
714			snps,priority = <0x0>;
715		};
716		queue1 {
717			snps,weight = <0x11>;
718			snps,dcb-algorithm;
719			snps,priority = <0x1>;
720		};
721		queue2 {
722			snps,weight = <0x12>;
723			snps,dcb-algorithm;
724			snps,priority = <0x2>;
725		};
726	};
727
728	eth: ethernet@1101c000 {
729		compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
730		reg = <0 0x1101c000 0 0x1300>;
731		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
732		interrupt-names = "macirq";
733		mac-address = [00 55 7b b5 7d f7];
734		clock-names = "axi",
735			      "apb",
736			      "mac_main",
737			      "ptp_ref",
738			      "rmii_internal";
739		clocks = <&pericfg CLK_PERI_GMAC>,
740			 <&pericfg CLK_PERI_GMAC_PCLK>,
741			 <&topckgen CLK_TOP_ETHER_125M_SEL>,
742			 <&topckgen CLK_TOP_ETHER_50M_SEL>,
743			 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
744		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
745				  <&topckgen CLK_TOP_ETHER_50M_SEL>,
746				  <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
747		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
748					 <&topckgen CLK_TOP_APLL1_D3>,
749					 <&topckgen CLK_TOP_ETHERPLL_50M>;
750		power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
751		mediatek,pericfg = <&pericfg>;
752		snps,axi-config = <&stmmac_axi_setup>;
753		snps,mtl-rx-config = <&mtl_rx_setup>;
754		snps,mtl-tx-config = <&mtl_tx_setup>;
755		snps,txpbl = <1>;
756		snps,rxpbl = <1>;
757		clk_csr = <0>;
758		status = "disabled";
759	};
760
761	mmc0: mmc@11230000 {
762		compatible = "mediatek,mt2712-mmc";
763		reg = <0 0x11230000 0 0x1000>;
764		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
765		clocks = <&pericfg CLK_PERI_MSDC30_0>,
766			 <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
767			 <&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
768			 <&pericfg CLK_PERI_MSDC50_0_EN>;
769		clock-names = "source", "hclk", "bus_clk", "source_cg";
770		status = "disabled";
771	};
772
773	mmc1: mmc@11240000 {
774		compatible = "mediatek,mt2712-mmc";
775		reg = <0 0x11240000 0 0x1000>;
776		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
777		clocks = <&pericfg CLK_PERI_MSDC30_1>,
778			 <&topckgen CLK_TOP_AXI_SEL>,
779			 <&pericfg CLK_PERI_MSDC30_1_EN>;
780		clock-names = "source", "hclk", "source_cg";
781		status = "disabled";
782	};
783
784	mmc2: mmc@11250000 {
785		compatible = "mediatek,mt2712-mmc";
786		reg = <0 0x11250000 0 0x1000>;
787		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
788		clocks = <&pericfg CLK_PERI_MSDC30_2>,
789			 <&topckgen CLK_TOP_AXI_SEL>,
790			 <&pericfg CLK_PERI_MSDC30_2_EN>;
791		clock-names = "source", "hclk", "source_cg";
792		status = "disabled";
793	};
794
795	ssusb: usb@11271000 {
796		compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
797		reg = <0 0x11271000 0 0x3000>,
798		      <0 0x11280700 0 0x0100>;
799		reg-names = "mac", "ippc";
800		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
801		phys = <&u2port0 PHY_TYPE_USB2>,
802		       <&u2port1 PHY_TYPE_USB2>;
803		power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
804		clocks = <&topckgen CLK_TOP_USB30_SEL>;
805		clock-names = "sys_ck";
806		mediatek,syscon-wakeup = <&pericfg 0x510 2>;
807		#address-cells = <2>;
808		#size-cells = <2>;
809		ranges;
810		status = "disabled";
811
812		usb_host0: usb@11270000 {
813			compatible = "mediatek,mt2712-xhci",
814				     "mediatek,mtk-xhci";
815			reg = <0 0x11270000 0 0x1000>;
816			reg-names = "mac";
817			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>;
818			power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
819			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
820			clock-names = "sys_ck", "ref_ck";
821			status = "disabled";
822		};
823	};
824
825	u3phy0: t-phy@11290000 {
826		compatible = "mediatek,mt2712-tphy",
827			     "mediatek,generic-tphy-v2";
828		#address-cells = <1>;
829		#size-cells = <1>;
830		ranges = <0 0 0x11290000 0x9000>;
831		status = "okay";
832
833		u2port0: usb-phy@0 {
834			reg = <0x0 0x700>;
835			clocks = <&clk26m>;
836			clock-names = "ref";
837			#phy-cells = <1>;
838			status = "okay";
839		};
840
841		u2port1: usb-phy@8000 {
842			reg = <0x8000 0x700>;
843			clocks = <&clk26m>;
844			clock-names = "ref";
845			#phy-cells = <1>;
846			status = "okay";
847		};
848
849		u3port0: usb-phy@8700 {
850			reg = <0x8700 0x900>;
851			clocks = <&clk26m>;
852			clock-names = "ref";
853			#phy-cells = <1>;
854			status = "okay";
855		};
856	};
857
858	ssusb1: usb@112c1000 {
859		compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
860		reg = <0 0x112c1000 0 0x3000>,
861		      <0 0x112d0700 0 0x0100>;
862		reg-names = "mac", "ippc";
863		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>;
864		phys = <&u2port2 PHY_TYPE_USB2>,
865		       <&u2port3 PHY_TYPE_USB2>,
866		       <&u3port1 PHY_TYPE_USB3>;
867		power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
868		clocks = <&topckgen CLK_TOP_USB30_SEL>;
869		clock-names = "sys_ck";
870		mediatek,syscon-wakeup = <&pericfg 0x514 2>;
871		#address-cells = <2>;
872		#size-cells = <2>;
873		ranges;
874		status = "disabled";
875
876		usb_host1: usb@112c0000 {
877			compatible = "mediatek,mt2712-xhci",
878				     "mediatek,mtk-xhci";
879			reg = <0 0x112c0000 0 0x1000>;
880			reg-names = "mac";
881			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
882			power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
883			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
884			clock-names = "sys_ck", "ref_ck";
885			status = "disabled";
886		};
887	};
888
889	u3phy1: t-phy@112e0000 {
890		compatible = "mediatek,mt2712-tphy",
891			     "mediatek,generic-tphy-v2";
892		#address-cells = <1>;
893		#size-cells = <1>;
894		ranges = <0 0 0x112e0000 0x9000>;
895		status = "okay";
896
897		u2port2: usb-phy@0 {
898			reg = <0x0 0x700>;
899			clocks = <&clk26m>;
900			clock-names = "ref";
901			#phy-cells = <1>;
902			status = "okay";
903		};
904
905		u2port3: usb-phy@8000 {
906			reg = <0x8000 0x700>;
907			clocks = <&clk26m>;
908			clock-names = "ref";
909			#phy-cells = <1>;
910			status = "okay";
911		};
912
913		u3port1: usb-phy@8700 {
914			reg = <0x8700 0x900>;
915			clocks = <&clk26m>;
916			clock-names = "ref";
917			#phy-cells = <1>;
918			status = "okay";
919		};
920	};
921
922	pcie1: pcie@112ff000 {
923		compatible = "mediatek,mt2712-pcie";
924		device_type = "pci";
925		reg = <0 0x112ff000 0 0x1000>;
926		reg-names = "port1";
927		linux,pci-domain = <1>;
928		#address-cells = <3>;
929		#size-cells = <2>;
930		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
931		interrupt-names = "pcie_irq";
932		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
933			 <&pericfg CLK_PERI_PCIE1>;
934		clock-names = "sys_ck1", "ahb_ck1";
935		phys = <&u3port1 PHY_TYPE_PCIE>;
936		phy-names = "pcie-phy1";
937		bus-range = <0x00 0xff>;
938		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
939		status = "disabled";
940
941		#interrupt-cells = <1>;
942		interrupt-map-mask = <0 0 0 7>;
943		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
944				<0 0 0 2 &pcie_intc1 1>,
945				<0 0 0 3 &pcie_intc1 2>,
946				<0 0 0 4 &pcie_intc1 3>;
947		pcie_intc1: interrupt-controller {
948			interrupt-controller;
949			#address-cells = <0>;
950			#interrupt-cells = <1>;
951		};
952	};
953
954	pcie0: pcie@11700000 {
955		compatible = "mediatek,mt2712-pcie";
956		device_type = "pci";
957		reg = <0 0x11700000 0 0x1000>;
958		reg-names = "port0";
959		linux,pci-domain = <0>;
960		#address-cells = <3>;
961		#size-cells = <2>;
962		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
963		interrupt-names = "pcie_irq";
964		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
965			 <&pericfg CLK_PERI_PCIE0>;
966		clock-names = "sys_ck0", "ahb_ck0";
967		phys = <&u3port0 PHY_TYPE_PCIE>;
968		phy-names = "pcie-phy0";
969		bus-range = <0x00 0xff>;
970		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
971		status = "disabled";
972
973		#interrupt-cells = <1>;
974		interrupt-map-mask = <0 0 0 7>;
975		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
976				<0 0 0 2 &pcie_intc0 1>,
977				<0 0 0 3 &pcie_intc0 2>,
978				<0 0 0 4 &pcie_intc0 3>;
979		pcie_intc0: interrupt-controller {
980			interrupt-controller;
981			#address-cells = <0>;
982			#interrupt-cells = <1>;
983		};
984	};
985
986	mfgcfg: syscon@13000000 {
987		compatible = "mediatek,mt2712-mfgcfg", "syscon";
988		reg = <0 0x13000000 0 0x1000>;
989		#clock-cells = <1>;
990	};
991
992	mmsys: syscon@14000000 {
993		compatible = "mediatek,mt2712-mmsys", "syscon";
994		reg = <0 0x14000000 0 0x1000>;
995		#clock-cells = <1>;
996	};
997
998	larb0: larb@14021000 {
999		compatible = "mediatek,mt2712-smi-larb";
1000		reg = <0 0x14021000 0 0x1000>;
1001		mediatek,smi = <&smi_common0>;
1002		mediatek,larb-id = <0>;
1003		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1004		clocks = <&mmsys CLK_MM_SMI_LARB0>,
1005			 <&mmsys CLK_MM_SMI_LARB0>;
1006		clock-names = "apb", "smi";
1007	};
1008
1009	smi_common0: smi@14022000 {
1010		compatible = "mediatek,mt2712-smi-common";
1011		reg = <0 0x14022000 0 0x1000>;
1012		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1013		clocks = <&mmsys CLK_MM_SMI_COMMON>,
1014			 <&mmsys CLK_MM_SMI_COMMON>;
1015		clock-names = "apb", "smi";
1016	};
1017
1018	larb4: larb@14027000 {
1019		compatible = "mediatek,mt2712-smi-larb";
1020		reg = <0 0x14027000 0 0x1000>;
1021		mediatek,smi = <&smi_common1>;
1022		mediatek,larb-id = <4>;
1023		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1024		clocks = <&mmsys CLK_MM_SMI_LARB4>,
1025			 <&mmsys CLK_MM_SMI_LARB4>;
1026		clock-names = "apb", "smi";
1027	};
1028
1029	larb5: larb@14030000 {
1030		compatible = "mediatek,mt2712-smi-larb";
1031		reg = <0 0x14030000 0 0x1000>;
1032		mediatek,smi = <&smi_common1>;
1033		mediatek,larb-id = <5>;
1034		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1035		clocks = <&mmsys CLK_MM_SMI_LARB5>,
1036			 <&mmsys CLK_MM_SMI_LARB5>;
1037		clock-names = "apb", "smi";
1038	};
1039
1040	smi_common1: smi@14031000 {
1041		compatible = "mediatek,mt2712-smi-common";
1042		reg = <0 0x14031000 0 0x1000>;
1043		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1044		clocks = <&mmsys CLK_MM_SMI_COMMON1>,
1045			 <&mmsys CLK_MM_SMI_COMMON1>;
1046		clock-names = "apb", "smi";
1047	};
1048
1049	larb7: larb@14032000 {
1050		compatible = "mediatek,mt2712-smi-larb";
1051		reg = <0 0x14032000 0 0x1000>;
1052		mediatek,smi = <&smi_common1>;
1053		mediatek,larb-id = <7>;
1054		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1055		clocks = <&mmsys CLK_MM_SMI_LARB7>,
1056			 <&mmsys CLK_MM_SMI_LARB7>;
1057		clock-names = "apb", "smi";
1058	};
1059
1060	imgsys: syscon@15000000 {
1061		compatible = "mediatek,mt2712-imgsys", "syscon";
1062		reg = <0 0x15000000 0 0x1000>;
1063		#clock-cells = <1>;
1064	};
1065
1066	larb2: larb@15001000 {
1067		compatible = "mediatek,mt2712-smi-larb";
1068		reg = <0 0x15001000 0 0x1000>;
1069		mediatek,smi = <&smi_common0>;
1070		mediatek,larb-id = <2>;
1071		power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
1072		clocks = <&imgsys CLK_IMG_SMI_LARB2>,
1073			 <&imgsys CLK_IMG_SMI_LARB2>;
1074		clock-names = "apb", "smi";
1075	};
1076
1077	bdpsys: syscon@15010000 {
1078		compatible = "mediatek,mt2712-bdpsys", "syscon";
1079		reg = <0 0x15010000 0 0x1000>;
1080		#clock-cells = <1>;
1081	};
1082
1083	vdecsys: syscon@16000000 {
1084		compatible = "mediatek,mt2712-vdecsys", "syscon";
1085		reg = <0 0x16000000 0 0x1000>;
1086		#clock-cells = <1>;
1087	};
1088
1089	larb1: larb@16010000 {
1090		compatible = "mediatek,mt2712-smi-larb";
1091		reg = <0 0x16010000 0 0x1000>;
1092		mediatek,smi = <&smi_common0>;
1093		mediatek,larb-id = <1>;
1094		power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
1095		clocks = <&vdecsys CLK_VDEC_CKEN>,
1096			 <&vdecsys CLK_VDEC_LARB1_CKEN>;
1097		clock-names = "apb", "smi";
1098	};
1099
1100	vencsys: syscon@18000000 {
1101		compatible = "mediatek,mt2712-vencsys", "syscon";
1102		reg = <0 0x18000000 0 0x1000>;
1103		#clock-cells = <1>;
1104	};
1105
1106	larb3: larb@18001000 {
1107		compatible = "mediatek,mt2712-smi-larb";
1108		reg = <0 0x18001000 0 0x1000>;
1109		mediatek,smi = <&smi_common0>;
1110		mediatek,larb-id = <3>;
1111		power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1112		clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1113			 <&vencsys CLK_VENC_VENC>;
1114		clock-names = "apb", "smi";
1115	};
1116
1117	larb6: larb@18002000 {
1118		compatible = "mediatek,mt2712-smi-larb";
1119		reg = <0 0x18002000 0 0x1000>;
1120		mediatek,smi = <&smi_common0>;
1121		mediatek,larb-id = <6>;
1122		power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1123		clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1124			 <&vencsys CLK_VENC_VENC>;
1125		clock-names = "apb", "smi";
1126	};
1127
1128	jpgdecsys: syscon@19000000 {
1129		compatible = "mediatek,mt2712-jpgdecsys", "syscon";
1130		reg = <0 0x19000000 0 0x1000>;
1131		#clock-cells = <1>;
1132	};
1133};
1134
1135