1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: YT Shen <yt.shen@mediatek.com> 4 * 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 */ 7 8#include <dt-bindings/clock/mt2712-clk.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/memory/mt2712-larb-port.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/power/mt2712-power.h> 14#include "mt2712-pinfunc.h" 15 16/ { 17 compatible = "mediatek,mt2712"; 18 interrupt-parent = <&sysirq>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cluster0_opp: opp_table0 { 23 compatible = "operating-points-v2"; 24 opp-shared; 25 opp00 { 26 opp-hz = /bits/ 64 <598000000>; 27 opp-microvolt = <1000000>; 28 }; 29 opp01 { 30 opp-hz = /bits/ 64 <702000000>; 31 opp-microvolt = <1000000>; 32 }; 33 opp02 { 34 opp-hz = /bits/ 64 <793000000>; 35 opp-microvolt = <1000000>; 36 }; 37 }; 38 39 cluster1_opp: opp_table1 { 40 compatible = "operating-points-v2"; 41 opp-shared; 42 opp00 { 43 opp-hz = /bits/ 64 <598000000>; 44 opp-microvolt = <1000000>; 45 }; 46 opp01 { 47 opp-hz = /bits/ 64 <702000000>; 48 opp-microvolt = <1000000>; 49 }; 50 opp02 { 51 opp-hz = /bits/ 64 <793000000>; 52 opp-microvolt = <1000000>; 53 }; 54 opp03 { 55 opp-hz = /bits/ 64 <897000000>; 56 opp-microvolt = <1000000>; 57 }; 58 opp04 { 59 opp-hz = /bits/ 64 <1001000000>; 60 opp-microvolt = <1000000>; 61 }; 62 }; 63 64 cpus { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&cpu0>; 72 }; 73 core1 { 74 cpu = <&cpu1>; 75 }; 76 }; 77 78 cluster1 { 79 core0 { 80 cpu = <&cpu2>; 81 }; 82 }; 83 }; 84 85 cpu0: cpu@0 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a35"; 88 reg = <0x000>; 89 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 90 <&topckgen CLK_TOP_F_MP0_PLL1>; 91 clock-names = "cpu", "intermediate"; 92 proc-supply = <&cpus_fixed_vproc0>; 93 operating-points-v2 = <&cluster0_opp>; 94 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 95 }; 96 97 cpu1: cpu@1 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a35"; 100 reg = <0x001>; 101 enable-method = "psci"; 102 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 103 <&topckgen CLK_TOP_F_MP0_PLL1>; 104 clock-names = "cpu", "intermediate"; 105 proc-supply = <&cpus_fixed_vproc0>; 106 operating-points-v2 = <&cluster0_opp>; 107 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 108 }; 109 110 cpu2: cpu@200 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a72"; 113 reg = <0x200>; 114 enable-method = "psci"; 115 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 116 <&topckgen CLK_TOP_F_BIG_PLL1>; 117 clock-names = "cpu", "intermediate"; 118 proc-supply = <&cpus_fixed_vproc1>; 119 operating-points-v2 = <&cluster1_opp>; 120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 121 }; 122 123 idle-states { 124 entry-method = "psci"; 125 126 CPU_SLEEP_0: cpu-sleep-0 { 127 compatible = "arm,idle-state"; 128 local-timer-stop; 129 entry-latency-us = <100>; 130 exit-latency-us = <80>; 131 min-residency-us = <2000>; 132 arm,psci-suspend-param = <0x0010000>; 133 }; 134 135 CLUSTER_SLEEP_0: cluster-sleep-0 { 136 compatible = "arm,idle-state"; 137 local-timer-stop; 138 entry-latency-us = <350>; 139 exit-latency-us = <80>; 140 min-residency-us = <3000>; 141 arm,psci-suspend-param = <0x1010000>; 142 }; 143 }; 144 }; 145 146 psci { 147 compatible = "arm,psci-0.2"; 148 method = "smc"; 149 }; 150 151 baud_clk: dummy26m { 152 compatible = "fixed-clock"; 153 clock-frequency = <26000000>; 154 #clock-cells = <0>; 155 }; 156 157 sys_clk: dummyclk { 158 compatible = "fixed-clock"; 159 clock-frequency = <26000000>; 160 #clock-cells = <0>; 161 }; 162 163 clk26m: oscillator@0 { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <26000000>; 167 clock-output-names = "clk26m"; 168 }; 169 170 clk32k: oscillator@1 { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <32768>; 174 clock-output-names = "clk32k"; 175 }; 176 177 clkfpc: oscillator@2 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <50000000>; 181 clock-output-names = "clkfpc"; 182 }; 183 184 clkaud_ext_i_0: oscillator@3 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <6500000>; 188 clock-output-names = "clkaud_ext_i_0"; 189 }; 190 191 clkaud_ext_i_1: oscillator@4 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <196608000>; 195 clock-output-names = "clkaud_ext_i_1"; 196 }; 197 198 clkaud_ext_i_2: oscillator@5 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <180633600>; 202 clock-output-names = "clkaud_ext_i_2"; 203 }; 204 205 clki2si0_mck_i: oscillator@6 { 206 compatible = "fixed-clock"; 207 #clock-cells = <0>; 208 clock-frequency = <30000000>; 209 clock-output-names = "clki2si0_mck_i"; 210 }; 211 212 clki2si1_mck_i: oscillator@7 { 213 compatible = "fixed-clock"; 214 #clock-cells = <0>; 215 clock-frequency = <30000000>; 216 clock-output-names = "clki2si1_mck_i"; 217 }; 218 219 clki2si2_mck_i: oscillator@8 { 220 compatible = "fixed-clock"; 221 #clock-cells = <0>; 222 clock-frequency = <30000000>; 223 clock-output-names = "clki2si2_mck_i"; 224 }; 225 226 clktdmin_mclk_i: oscillator@9 { 227 compatible = "fixed-clock"; 228 #clock-cells = <0>; 229 clock-frequency = <30000000>; 230 clock-output-names = "clktdmin_mclk_i"; 231 }; 232 233 timer { 234 compatible = "arm,armv8-timer"; 235 interrupt-parent = <&gic>; 236 interrupts = <GIC_PPI 13 237 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 14 239 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 11 241 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 242 <GIC_PPI 10 243 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 244 }; 245 246 topckgen: syscon@10000000 { 247 compatible = "mediatek,mt2712-topckgen", "syscon"; 248 reg = <0 0x10000000 0 0x1000>; 249 #clock-cells = <1>; 250 }; 251 252 infracfg: syscon@10001000 { 253 compatible = "mediatek,mt2712-infracfg", "syscon"; 254 reg = <0 0x10001000 0 0x1000>; 255 #clock-cells = <1>; 256 }; 257 258 pericfg: syscon@10003000 { 259 compatible = "mediatek,mt2712-pericfg", "syscon"; 260 reg = <0 0x10003000 0 0x1000>; 261 #clock-cells = <1>; 262 }; 263 264 syscfg_pctl_a: syscfg_pctl_a@10005000 { 265 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; 266 reg = <0 0x10005000 0 0x1000>; 267 }; 268 269 pio: pinctrl@10005000 { 270 compatible = "mediatek,mt2712-pinctrl"; 271 reg = <0 0x1000b000 0 0x1000>; 272 mediatek,pctl-regmap = <&syscfg_pctl_a>; 273 pins-are-numbered; 274 gpio-controller; 275 #gpio-cells = <2>; 276 interrupt-controller; 277 #interrupt-cells = <2>; 278 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 281 scpsys: power-controller@10006000 { 282 compatible = "mediatek,mt2712-scpsys", "syscon"; 283 #power-domain-cells = <1>; 284 reg = <0 0x10006000 0 0x1000>; 285 clocks = <&topckgen CLK_TOP_MM_SEL>, 286 <&topckgen CLK_TOP_MFG_SEL>, 287 <&topckgen CLK_TOP_VENC_SEL>, 288 <&topckgen CLK_TOP_JPGDEC_SEL>, 289 <&topckgen CLK_TOP_A1SYS_HP_SEL>, 290 <&topckgen CLK_TOP_VDEC_SEL>; 291 clock-names = "mm", "mfg", "venc", 292 "jpgdec", "audio", "vdec"; 293 infracfg = <&infracfg>; 294 }; 295 296 uart5: serial@1000f000 { 297 compatible = "mediatek,mt2712-uart", 298 "mediatek,mt6577-uart"; 299 reg = <0 0x1000f000 0 0x400>; 300 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 301 clocks = <&baud_clk>, <&sys_clk>; 302 clock-names = "baud", "bus"; 303 status = "disabled"; 304 }; 305 306 rtc: rtc@10011000 { 307 compatible = "mediatek,mt2712-rtc"; 308 reg = <0 0x10011000 0 0x1000>; 309 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>; 310 }; 311 312 spis1: spi@10013000 { 313 compatible = "mediatek,mt2712-spi-slave"; 314 reg = <0 0x10013000 0 0x100>; 315 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 316 clocks = <&infracfg CLK_INFRA_AO_SPI1>; 317 clock-names = "spi"; 318 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 319 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 320 status = "disabled"; 321 }; 322 323 iommu0: iommu@10205000 { 324 compatible = "mediatek,mt2712-m4u"; 325 reg = <0 0x10205000 0 0x1000>; 326 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; 327 clocks = <&infracfg CLK_INFRA_M4U>; 328 clock-names = "bclk"; 329 mediatek,larbs = <&larb0 &larb1 &larb2 330 &larb3 &larb6>; 331 #iommu-cells = <1>; 332 }; 333 334 apmixedsys: syscon@10209000 { 335 compatible = "mediatek,mt2712-apmixedsys", "syscon"; 336 reg = <0 0x10209000 0 0x1000>; 337 #clock-cells = <1>; 338 }; 339 340 iommu1: iommu@1020a000 { 341 compatible = "mediatek,mt2712-m4u"; 342 reg = <0 0x1020a000 0 0x1000>; 343 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 344 clocks = <&infracfg CLK_INFRA_M4U>; 345 clock-names = "bclk"; 346 mediatek,larbs = <&larb4 &larb5 &larb7>; 347 #iommu-cells = <1>; 348 }; 349 350 mcucfg: syscon@10220000 { 351 compatible = "mediatek,mt2712-mcucfg", "syscon"; 352 reg = <0 0x10220000 0 0x1000>; 353 #clock-cells = <1>; 354 }; 355 356 sysirq: interrupt-controller@10220a80 { 357 compatible = "mediatek,mt2712-sysirq", 358 "mediatek,mt6577-sysirq"; 359 interrupt-controller; 360 #interrupt-cells = <3>; 361 interrupt-parent = <&gic>; 362 reg = <0 0x10220a80 0 0x40>; 363 }; 364 365 gic: interrupt-controller@10510000 { 366 compatible = "arm,gic-400"; 367 #interrupt-cells = <3>; 368 interrupt-parent = <&gic>; 369 interrupt-controller; 370 reg = <0 0x10510000 0 0x10000>, 371 <0 0x10520000 0 0x20000>, 372 <0 0x10540000 0 0x20000>, 373 <0 0x10560000 0 0x20000>; 374 interrupts = <GIC_PPI 9 375 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 376 }; 377 378 auxadc: adc@11001000 { 379 compatible = "mediatek,mt2712-auxadc"; 380 reg = <0 0x11001000 0 0x1000>; 381 clocks = <&pericfg CLK_PERI_AUXADC>; 382 clock-names = "main"; 383 #io-channel-cells = <1>; 384 status = "disabled"; 385 }; 386 387 uart0: serial@11002000 { 388 compatible = "mediatek,mt2712-uart", 389 "mediatek,mt6577-uart"; 390 reg = <0 0x11002000 0 0x400>; 391 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 392 clocks = <&baud_clk>, <&sys_clk>; 393 clock-names = "baud", "bus"; 394 status = "disabled"; 395 }; 396 397 uart1: serial@11003000 { 398 compatible = "mediatek,mt2712-uart", 399 "mediatek,mt6577-uart"; 400 reg = <0 0x11003000 0 0x400>; 401 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 402 clocks = <&baud_clk>, <&sys_clk>; 403 clock-names = "baud", "bus"; 404 status = "disabled"; 405 }; 406 407 uart2: serial@11004000 { 408 compatible = "mediatek,mt2712-uart", 409 "mediatek,mt6577-uart"; 410 reg = <0 0x11004000 0 0x400>; 411 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 412 clocks = <&baud_clk>, <&sys_clk>; 413 clock-names = "baud", "bus"; 414 status = "disabled"; 415 }; 416 417 uart3: serial@11005000 { 418 compatible = "mediatek,mt2712-uart", 419 "mediatek,mt6577-uart"; 420 reg = <0 0x11005000 0 0x400>; 421 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 422 clocks = <&baud_clk>, <&sys_clk>; 423 clock-names = "baud", "bus"; 424 status = "disabled"; 425 }; 426 427 pwm: pwm@11006000 { 428 compatible = "mediatek,mt2712-pwm"; 429 reg = <0 0x11006000 0 0x1000>; 430 #pwm-cells = <2>; 431 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 432 clocks = <&topckgen CLK_TOP_PWM_SEL>, 433 <&pericfg CLK_PERI_PWM>, 434 <&pericfg CLK_PERI_PWM0>, 435 <&pericfg CLK_PERI_PWM1>, 436 <&pericfg CLK_PERI_PWM2>, 437 <&pericfg CLK_PERI_PWM3>, 438 <&pericfg CLK_PERI_PWM4>, 439 <&pericfg CLK_PERI_PWM5>, 440 <&pericfg CLK_PERI_PWM6>, 441 <&pericfg CLK_PERI_PWM7>; 442 clock-names = "top", 443 "main", 444 "pwm1", 445 "pwm2", 446 "pwm3", 447 "pwm4", 448 "pwm5", 449 "pwm6", 450 "pwm7", 451 "pwm8"; 452 status = "disabled"; 453 }; 454 455 i2c0: i2c@11007000 { 456 compatible = "mediatek,mt2712-i2c"; 457 reg = <0 0x11007000 0 0x90>, 458 <0 0x11000180 0 0x80>; 459 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 460 clock-div = <4>; 461 clocks = <&pericfg CLK_PERI_I2C0>, 462 <&pericfg CLK_PERI_AP_DMA>; 463 clock-names = "main", 464 "dma"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 status = "disabled"; 468 }; 469 470 i2c1: i2c@11008000 { 471 compatible = "mediatek,mt2712-i2c"; 472 reg = <0 0x11008000 0 0x90>, 473 <0 0x11000200 0 0x80>; 474 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 475 clock-div = <4>; 476 clocks = <&pericfg CLK_PERI_I2C1>, 477 <&pericfg CLK_PERI_AP_DMA>; 478 clock-names = "main", 479 "dma"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 i2c2: i2c@11009000 { 486 compatible = "mediatek,mt2712-i2c"; 487 reg = <0 0x11009000 0 0x90>, 488 <0 0x11000280 0 0x80>; 489 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 490 clock-div = <4>; 491 clocks = <&pericfg CLK_PERI_I2C2>, 492 <&pericfg CLK_PERI_AP_DMA>; 493 clock-names = "main", 494 "dma"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 status = "disabled"; 498 }; 499 500 spi0: spi@1100a000 { 501 compatible = "mediatek,mt2712-spi"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 reg = <0 0x1100a000 0 0x100>; 505 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; 506 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 507 <&topckgen CLK_TOP_SPI_SEL>, 508 <&pericfg CLK_PERI_SPI0>; 509 clock-names = "parent-clk", "sel-clk", "spi-clk"; 510 status = "disabled"; 511 }; 512 513 nandc: nfi@1100e000 { 514 compatible = "mediatek,mt2712-nfc"; 515 reg = <0 0x1100e000 0 0x1000>; 516 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 517 clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; 518 clock-names = "nfi_clk", "pad_clk"; 519 ecc-engine = <&bch>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 status = "disabled"; 523 }; 524 525 bch: ecc@1100f000 { 526 compatible = "mediatek,mt2712-ecc"; 527 reg = <0 0x1100f000 0 0x1000>; 528 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; 529 clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; 530 clock-names = "nfiecc_clk"; 531 status = "disabled"; 532 }; 533 534 i2c3: i2c@11010000 { 535 compatible = "mediatek,mt2712-i2c"; 536 reg = <0 0x11010000 0 0x90>, 537 <0 0x11000300 0 0x80>; 538 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 539 clock-div = <4>; 540 clocks = <&pericfg CLK_PERI_I2C3>, 541 <&pericfg CLK_PERI_AP_DMA>; 542 clock-names = "main", 543 "dma"; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 status = "disabled"; 547 }; 548 549 i2c4: i2c@11011000 { 550 compatible = "mediatek,mt2712-i2c"; 551 reg = <0 0x11011000 0 0x90>, 552 <0 0x11000380 0 0x80>; 553 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 554 clock-div = <4>; 555 clocks = <&pericfg CLK_PERI_I2C4>, 556 <&pericfg CLK_PERI_AP_DMA>; 557 clock-names = "main", 558 "dma"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 status = "disabled"; 562 }; 563 564 i2c5: i2c@11013000 { 565 compatible = "mediatek,mt2712-i2c"; 566 reg = <0 0x11013000 0 0x90>, 567 <0 0x11000100 0 0x80>; 568 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 569 clock-div = <4>; 570 clocks = <&pericfg CLK_PERI_I2C5>, 571 <&pericfg CLK_PERI_AP_DMA>; 572 clock-names = "main", 573 "dma"; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 status = "disabled"; 577 }; 578 579 spi2: spi@11015000 { 580 compatible = "mediatek,mt2712-spi"; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 reg = <0 0x11015000 0 0x100>; 584 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>; 585 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 586 <&topckgen CLK_TOP_SPI_SEL>, 587 <&pericfg CLK_PERI_SPI2>; 588 clock-names = "parent-clk", "sel-clk", "spi-clk"; 589 status = "disabled"; 590 }; 591 592 spi3: spi@11016000 { 593 compatible = "mediatek,mt2712-spi"; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 reg = <0 0x11016000 0 0x100>; 597 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>; 598 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 599 <&topckgen CLK_TOP_SPI_SEL>, 600 <&pericfg CLK_PERI_SPI3>; 601 clock-names = "parent-clk", "sel-clk", "spi-clk"; 602 status = "disabled"; 603 }; 604 605 spi4: spi@10012000 { 606 compatible = "mediatek,mt2712-spi"; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 reg = <0 0x10012000 0 0x100>; 610 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; 611 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 612 <&topckgen CLK_TOP_SPI_SEL>, 613 <&infracfg CLK_INFRA_AO_SPI0>; 614 clock-names = "parent-clk", "sel-clk", "spi-clk"; 615 status = "disabled"; 616 }; 617 618 spi5: spi@11018000 { 619 compatible = "mediatek,mt2712-spi"; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <0 0x11018000 0 0x100>; 623 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>; 624 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 625 <&topckgen CLK_TOP_SPI_SEL>, 626 <&pericfg CLK_PERI_SPI5>; 627 clock-names = "parent-clk", "sel-clk", "spi-clk"; 628 status = "disabled"; 629 }; 630 631 uart4: serial@11019000 { 632 compatible = "mediatek,mt2712-uart", 633 "mediatek,mt6577-uart"; 634 reg = <0 0x11019000 0 0x400>; 635 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 636 clocks = <&baud_clk>, <&sys_clk>; 637 clock-names = "baud", "bus"; 638 status = "disabled"; 639 }; 640 641 mmc0: mmc@11230000 { 642 compatible = "mediatek,mt2712-mmc"; 643 reg = <0 0x11230000 0 0x1000>; 644 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 645 clocks = <&pericfg CLK_PERI_MSDC30_0>, 646 <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, 647 <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, 648 <&pericfg CLK_PERI_MSDC50_0_EN>; 649 clock-names = "source", "hclk", "bus_clk", "source_cg"; 650 status = "disabled"; 651 }; 652 653 mmc1: mmc@11240000 { 654 compatible = "mediatek,mt2712-mmc"; 655 reg = <0 0x11240000 0 0x1000>; 656 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 657 clocks = <&pericfg CLK_PERI_MSDC30_1>, 658 <&topckgen CLK_TOP_AXI_SEL>, 659 <&pericfg CLK_PERI_MSDC30_1_EN>; 660 clock-names = "source", "hclk", "source_cg"; 661 status = "disabled"; 662 }; 663 664 mmc2: mmc@11250000 { 665 compatible = "mediatek,mt2712-mmc"; 666 reg = <0 0x11250000 0 0x1000>; 667 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 668 clocks = <&pericfg CLK_PERI_MSDC30_2>, 669 <&topckgen CLK_TOP_AXI_SEL>, 670 <&pericfg CLK_PERI_MSDC30_2_EN>; 671 clock-names = "source", "hclk", "source_cg"; 672 status = "disabled"; 673 }; 674 675 ssusb: usb@11271000 { 676 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 677 reg = <0 0x11271000 0 0x3000>, 678 <0 0x11280700 0 0x0100>; 679 reg-names = "mac", "ippc"; 680 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 681 phys = <&u2port0 PHY_TYPE_USB2>, 682 <&u2port1 PHY_TYPE_USB2>; 683 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 684 clocks = <&topckgen CLK_TOP_USB30_SEL>; 685 clock-names = "sys_ck"; 686 mediatek,syscon-wakeup = <&pericfg 0x510 2>; 687 #address-cells = <2>; 688 #size-cells = <2>; 689 ranges; 690 status = "disabled"; 691 692 usb_host0: xhci@11270000 { 693 compatible = "mediatek,mt2712-xhci", 694 "mediatek,mtk-xhci"; 695 reg = <0 0x11270000 0 0x1000>; 696 reg-names = "mac"; 697 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>; 698 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 699 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 700 clock-names = "sys_ck", "ref_ck"; 701 status = "disabled"; 702 }; 703 }; 704 705 u3phy0: usb-phy@11290000 { 706 compatible = "mediatek,mt2712-u3phy"; 707 #address-cells = <2>; 708 #size-cells = <2>; 709 ranges; 710 status = "okay"; 711 712 u2port0: usb-phy@11290000 { 713 reg = <0 0x11290000 0 0x700>; 714 clocks = <&clk26m>; 715 clock-names = "ref"; 716 #phy-cells = <1>; 717 status = "okay"; 718 }; 719 720 u2port1: usb-phy@11298000 { 721 reg = <0 0x11298000 0 0x700>; 722 clocks = <&clk26m>; 723 clock-names = "ref"; 724 #phy-cells = <1>; 725 status = "okay"; 726 }; 727 728 u3port0: usb-phy@11298700 { 729 reg = <0 0x11298700 0 0x900>; 730 clocks = <&clk26m>; 731 clock-names = "ref"; 732 #phy-cells = <1>; 733 status = "okay"; 734 }; 735 }; 736 737 ssusb1: usb@112c1000 { 738 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 739 reg = <0 0x112c1000 0 0x3000>, 740 <0 0x112d0700 0 0x0100>; 741 reg-names = "mac", "ippc"; 742 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>; 743 phys = <&u2port2 PHY_TYPE_USB2>, 744 <&u2port3 PHY_TYPE_USB2>, 745 <&u3port1 PHY_TYPE_USB3>; 746 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 747 clocks = <&topckgen CLK_TOP_USB30_SEL>; 748 clock-names = "sys_ck"; 749 mediatek,syscon-wakeup = <&pericfg 0x514 2>; 750 #address-cells = <2>; 751 #size-cells = <2>; 752 ranges; 753 status = "disabled"; 754 755 usb_host1: xhci@112c0000 { 756 compatible = "mediatek,mt2712-xhci", 757 "mediatek,mtk-xhci"; 758 reg = <0 0x112c0000 0 0x1000>; 759 reg-names = "mac"; 760 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 761 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 762 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 763 clock-names = "sys_ck", "ref_ck"; 764 status = "disabled"; 765 }; 766 }; 767 768 u3phy1: usb-phy@112e0000 { 769 compatible = "mediatek,mt2712-u3phy"; 770 #address-cells = <2>; 771 #size-cells = <2>; 772 ranges; 773 status = "okay"; 774 775 u2port2: usb-phy@112e0000 { 776 reg = <0 0x112e0000 0 0x700>; 777 clocks = <&clk26m>; 778 clock-names = "ref"; 779 #phy-cells = <1>; 780 status = "okay"; 781 }; 782 783 u2port3: usb-phy@112e8000 { 784 reg = <0 0x112e8000 0 0x700>; 785 clocks = <&clk26m>; 786 clock-names = "ref"; 787 #phy-cells = <1>; 788 status = "okay"; 789 }; 790 791 u3port1: usb-phy@112e8700 { 792 reg = <0 0x112e8700 0 0x900>; 793 clocks = <&clk26m>; 794 clock-names = "ref"; 795 #phy-cells = <1>; 796 status = "okay"; 797 }; 798 }; 799 800 pcie: pcie@11700000 { 801 compatible = "mediatek,mt2712-pcie"; 802 device_type = "pci"; 803 reg = <0 0x11700000 0 0x1000>, 804 <0 0x112ff000 0 0x1000>; 805 reg-names = "port0", "port1"; 806 #address-cells = <3>; 807 #size-cells = <2>; 808 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, 811 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, 812 <&pericfg CLK_PERI_PCIE0>, 813 <&pericfg CLK_PERI_PCIE1>; 814 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; 815 phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; 816 phy-names = "pcie-phy0", "pcie-phy1"; 817 bus-range = <0x00 0xff>; 818 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 819 820 pcie0: pcie@0,0 { 821 device_type = "pci"; 822 status = "disabled"; 823 reg = <0x0000 0 0 0 0>; 824 #address-cells = <3>; 825 #size-cells = <2>; 826 #interrupt-cells = <1>; 827 ranges; 828 interrupt-map-mask = <0 0 0 7>; 829 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 830 <0 0 0 2 &pcie_intc0 1>, 831 <0 0 0 3 &pcie_intc0 2>, 832 <0 0 0 4 &pcie_intc0 3>; 833 pcie_intc0: interrupt-controller { 834 interrupt-controller; 835 #address-cells = <0>; 836 #interrupt-cells = <1>; 837 }; 838 }; 839 840 pcie1: pcie@1,0 { 841 device_type = "pci"; 842 status = "disabled"; 843 reg = <0x0800 0 0 0 0>; 844 #address-cells = <3>; 845 #size-cells = <2>; 846 #interrupt-cells = <1>; 847 ranges; 848 interrupt-map-mask = <0 0 0 7>; 849 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 850 <0 0 0 2 &pcie_intc1 1>, 851 <0 0 0 3 &pcie_intc1 2>, 852 <0 0 0 4 &pcie_intc1 3>; 853 pcie_intc1: interrupt-controller { 854 interrupt-controller; 855 #address-cells = <0>; 856 #interrupt-cells = <1>; 857 }; 858 }; 859 }; 860 861 mfgcfg: syscon@13000000 { 862 compatible = "mediatek,mt2712-mfgcfg", "syscon"; 863 reg = <0 0x13000000 0 0x1000>; 864 #clock-cells = <1>; 865 }; 866 867 mmsys: syscon@14000000 { 868 compatible = "mediatek,mt2712-mmsys", "syscon"; 869 reg = <0 0x14000000 0 0x1000>; 870 #clock-cells = <1>; 871 }; 872 873 larb0: larb@14021000 { 874 compatible = "mediatek,mt2712-smi-larb"; 875 reg = <0 0x14021000 0 0x1000>; 876 mediatek,smi = <&smi_common0>; 877 mediatek,larb-id = <0>; 878 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 879 clocks = <&mmsys CLK_MM_SMI_LARB0>, 880 <&mmsys CLK_MM_SMI_LARB0>; 881 clock-names = "apb", "smi"; 882 }; 883 884 smi_common0: smi@14022000 { 885 compatible = "mediatek,mt2712-smi-common"; 886 reg = <0 0x14022000 0 0x1000>; 887 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 888 clocks = <&mmsys CLK_MM_SMI_COMMON>, 889 <&mmsys CLK_MM_SMI_COMMON>; 890 clock-names = "apb", "smi"; 891 }; 892 893 larb4: larb@14027000 { 894 compatible = "mediatek,mt2712-smi-larb"; 895 reg = <0 0x14027000 0 0x1000>; 896 mediatek,smi = <&smi_common1>; 897 mediatek,larb-id = <4>; 898 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 899 clocks = <&mmsys CLK_MM_SMI_LARB4>, 900 <&mmsys CLK_MM_SMI_LARB4>; 901 clock-names = "apb", "smi"; 902 }; 903 904 larb5: larb@14030000 { 905 compatible = "mediatek,mt2712-smi-larb"; 906 reg = <0 0x14030000 0 0x1000>; 907 mediatek,smi = <&smi_common1>; 908 mediatek,larb-id = <5>; 909 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 910 clocks = <&mmsys CLK_MM_SMI_LARB5>, 911 <&mmsys CLK_MM_SMI_LARB5>; 912 clock-names = "apb", "smi"; 913 }; 914 915 smi_common1: smi@14031000 { 916 compatible = "mediatek,mt2712-smi-common"; 917 reg = <0 0x14031000 0 0x1000>; 918 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 919 clocks = <&mmsys CLK_MM_SMI_COMMON1>, 920 <&mmsys CLK_MM_SMI_COMMON1>; 921 clock-names = "apb", "smi"; 922 }; 923 924 larb7: larb@14032000 { 925 compatible = "mediatek,mt2712-smi-larb"; 926 reg = <0 0x14032000 0 0x1000>; 927 mediatek,smi = <&smi_common1>; 928 mediatek,larb-id = <7>; 929 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 930 clocks = <&mmsys CLK_MM_SMI_LARB7>, 931 <&mmsys CLK_MM_SMI_LARB7>; 932 clock-names = "apb", "smi"; 933 }; 934 935 imgsys: syscon@15000000 { 936 compatible = "mediatek,mt2712-imgsys", "syscon"; 937 reg = <0 0x15000000 0 0x1000>; 938 #clock-cells = <1>; 939 }; 940 941 larb2: larb@15001000 { 942 compatible = "mediatek,mt2712-smi-larb"; 943 reg = <0 0x15001000 0 0x1000>; 944 mediatek,smi = <&smi_common0>; 945 mediatek,larb-id = <2>; 946 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; 947 clocks = <&imgsys CLK_IMG_SMI_LARB2>, 948 <&imgsys CLK_IMG_SMI_LARB2>; 949 clock-names = "apb", "smi"; 950 }; 951 952 bdpsys: syscon@15010000 { 953 compatible = "mediatek,mt2712-bdpsys", "syscon"; 954 reg = <0 0x15010000 0 0x1000>; 955 #clock-cells = <1>; 956 }; 957 958 vdecsys: syscon@16000000 { 959 compatible = "mediatek,mt2712-vdecsys", "syscon"; 960 reg = <0 0x16000000 0 0x1000>; 961 #clock-cells = <1>; 962 }; 963 964 larb1: larb@16010000 { 965 compatible = "mediatek,mt2712-smi-larb"; 966 reg = <0 0x16010000 0 0x1000>; 967 mediatek,smi = <&smi_common0>; 968 mediatek,larb-id = <1>; 969 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; 970 clocks = <&vdecsys CLK_VDEC_CKEN>, 971 <&vdecsys CLK_VDEC_LARB1_CKEN>; 972 clock-names = "apb", "smi"; 973 }; 974 975 vencsys: syscon@18000000 { 976 compatible = "mediatek,mt2712-vencsys", "syscon"; 977 reg = <0 0x18000000 0 0x1000>; 978 #clock-cells = <1>; 979 }; 980 981 larb3: larb@18001000 { 982 compatible = "mediatek,mt2712-smi-larb"; 983 reg = <0 0x18001000 0 0x1000>; 984 mediatek,smi = <&smi_common0>; 985 mediatek,larb-id = <3>; 986 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 987 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 988 <&vencsys CLK_VENC_VENC>; 989 clock-names = "apb", "smi"; 990 }; 991 992 larb6: larb@18002000 { 993 compatible = "mediatek,mt2712-smi-larb"; 994 reg = <0 0x18002000 0 0x1000>; 995 mediatek,smi = <&smi_common0>; 996 mediatek,larb-id = <6>; 997 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 998 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 999 <&vencsys CLK_VENC_VENC>; 1000 clock-names = "apb", "smi"; 1001 }; 1002 1003 jpgdecsys: syscon@19000000 { 1004 compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 1005 reg = <0 0x19000000 0 0x1000>; 1006 #clock-cells = <1>; 1007 }; 1008}; 1009 1010