1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Device tree for the CN9131-DB board.
6 */
7
8#include "cn9130-db.dtsi"
9
10/ {
11	compatible = "marvell,cn9131", "marvell,cn9130",
12		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
13
14	aliases {
15		gpio3 = &cp1_gpio1;
16		gpio4 = &cp1_gpio2;
17		ethernet3 = &cp1_eth0;
18		ethernet4 = &cp1_eth1;
19	};
20
21	cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
22		compatible = "regulator-fixed";
23		pinctrl-names = "default";
24		pinctrl-0 = <&cp1_xhci0_vbus_pins>;
25		regulator-name = "cp1-xhci0-vbus";
26		regulator-min-microvolt = <5000000>;
27		regulator-max-microvolt = <5000000>;
28		enable-active-high;
29		gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
30	};
31
32	cp1_usb3_0_phy0: cp1_usb3_phy0 {
33		compatible = "usb-nop-xceiv";
34		vcc-supply = <&cp1_reg_usb3_vbus0>;
35	};
36
37	cp1_sfp_eth1: sfp-eth1 {
38		compatible = "sff,sfp";
39		i2c-bus = <&cp1_i2c0>;
40		los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
41		mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
42		tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
43		tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
44		pinctrl-names = "default";
45		pinctrl-0 = <&cp1_sfp_pins>;
46		/*
47		 * SFP cages are unconnected on early PCBs because of an the I2C
48		 * lanes not being connected. Prevent the port for being
49		 * unusable by disabling the SFP node.
50		 */
51		status = "disabled";
52	};
53};
54
55/*
56 * Instantiate the first slave CP115
57 */
58
59#define CP11X_NAME		cp1
60#define CP11X_BASE		f4000000
61#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
62#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
63#define CP11X_PCIE0_BASE	f4600000
64#define CP11X_PCIE1_BASE	f4620000
65#define CP11X_PCIE2_BASE	f4640000
66
67#include "armada-cp115.dtsi"
68
69#undef CP11X_NAME
70#undef CP11X_BASE
71#undef CP11X_PCIEx_MEM_BASE
72#undef CP11X_PCIEx_MEM_SIZE
73#undef CP11X_PCIE0_BASE
74#undef CP11X_PCIE1_BASE
75#undef CP11X_PCIE2_BASE
76
77&cp1_crypto {
78	status = "disabled";
79};
80
81&cp1_ethernet {
82	status = "okay";
83};
84
85/* CON50 */
86&cp1_eth0 {
87	status = "okay";
88	phy-mode = "10gbase-r";
89	/* Generic PHY, providing serdes lanes */
90	phys = <&cp1_comphy4 0>;
91	managed = "in-band-status";
92	sfp = <&cp1_sfp_eth1>;
93};
94
95&cp1_gpio1 {
96	status = "okay";
97};
98
99&cp1_gpio2 {
100	status = "okay";
101};
102
103&cp1_i2c0 {
104	status = "okay";
105	pinctrl-names = "default";
106	pinctrl-0 = <&cp1_i2c0_pins>;
107	clock-frequency = <100000>;
108};
109
110/* CON40 */
111&cp1_pcie0 {
112	pinctrl-names = "default";
113	pinctrl-0 = <&cp1_pcie_reset_pins>;
114	num-lanes = <2>;
115	num-viewport = <8>;
116	marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
117	status = "okay";
118	/* Generic PHY, providing serdes lanes */
119	phys = <&cp1_comphy0 0
120		&cp1_comphy1 0>;
121};
122
123&cp1_sata0 {
124	status = "okay";
125
126	/* CON32 */
127	sata-port@1 {
128		/* Generic PHY, providing serdes lanes */
129		phys = <&cp1_comphy5 1>;
130	};
131};
132
133/* U24 */
134&cp1_spi1 {
135	status = "okay";
136	pinctrl-names = "default";
137	pinctrl-0 = <&cp1_spi0_pins>;
138	reg = <0x700680 0x50>;
139
140	spi-flash@0 {
141		#address-cells = <0x1>;
142		#size-cells = <0x1>;
143		compatible = "jedec,spi-nor";
144		reg = <0x0>;
145		/* On-board MUX does not allow higher frequencies */
146		spi-max-frequency = <40000000>;
147
148		partitions {
149			compatible = "fixed-partitions";
150			#address-cells = <1>;
151			#size-cells = <1>;
152
153			partition@0 {
154				label = "U-Boot-1";
155				reg = <0x0 0x200000>;
156			};
157
158			partition@400000 {
159				label = "Filesystem-1";
160				reg = <0x200000 0xe00000>;
161			};
162		};
163	};
164
165};
166
167&cp1_syscon0 {
168	cp1_pinctrl: pinctrl {
169		compatible = "marvell,cp115-standalone-pinctrl";
170
171		cp1_i2c0_pins: cp1-i2c-pins-0 {
172			marvell,pins = "mpp37", "mpp38";
173			marvell,function = "i2c0";
174		};
175		cp1_spi0_pins: cp1-spi-pins-0 {
176			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
177			marvell,function = "spi1";
178		};
179		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
180			marvell,pins = "mpp3";
181			marvell,function = "gpio";
182		};
183		cp1_sfp_pins: sfp-pins {
184			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
185			marvell,function = "gpio";
186		};
187		cp1_pcie_reset_pins: cp1-pcie-reset-pins {
188			marvell,pins = "mpp0";
189			marvell,function = "gpio";
190		};
191	};
192};
193
194/* CON58 */
195&cp1_utmi {
196	status = "okay";
197};
198
199&cp1_usb3_1 {
200	status = "okay";
201	usb-phy = <&cp1_usb3_0_phy0>;
202	/* Generic PHY, providing serdes lanes */
203	phys = <&cp1_comphy3 1>, <&cp1_utmi1>;
204	phy-names = "usb", "utmi";
205	dr_mode = "host";
206};
207