1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 */
5
6#include "cn9130.dtsi" /* include SoC device tree */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	chosen {
12		stdout-path = "serial0:115200n8";
13	};
14
15	aliases {
16		i2c0 = &cp0_i2c0;
17		ethernet0 = &cp0_eth0;
18		ethernet1 = &cp0_eth1;
19		ethernet2 = &cp0_eth2;
20	};
21
22	memory@0 {
23		device_type = "memory";
24		reg = <0x0 0x0 0x0 0x80000000>;
25	};
26
27	ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
28		compatible = "regulator-gpio";
29		regulator-name = "ap0_mmc_vccq";
30		regulator-min-microvolt = <1800000>;
31		regulator-max-microvolt = <3300000>;
32		gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
33		states = <1800000 0x1
34			  3300000 0x0>;
35	};
36
37	cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
38		compatible = "regulator-fixed";
39		regulator-name = "cp0-xhci1-vbus";
40		regulator-min-microvolt = <5000000>;
41		regulator-max-microvolt = <5000000>;
42		enable-active-high;
43		gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
44	};
45
46	cp0_usb3_0_phy0: cp0_usb3_phy0 {
47		compatible = "usb-nop-xceiv";
48	};
49
50	cp0_usb3_0_phy1: cp0_usb3_phy1 {
51		compatible = "usb-nop-xceiv";
52		vcc-supply = <&cp0_reg_usb3_vbus1>;
53	};
54
55	cp0_reg_sd_vccq: cp0_sd_vccq@0 {
56		compatible = "regulator-gpio";
57		regulator-name = "cp0_sd_vccq";
58		regulator-min-microvolt = <1800000>;
59		regulator-max-microvolt = <3300000>;
60		gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
61		states = <1800000 0x1
62			  3300000 0x0>;
63	};
64
65	cp0_reg_sd_vcc: cp0_sd_vcc@0 {
66		compatible = "regulator-fixed";
67		regulator-name = "cp0_sd_vcc";
68		regulator-min-microvolt = <3300000>;
69		regulator-max-microvolt = <3300000>;
70		gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
71		enable-active-high;
72		regulator-always-on;
73	};
74};
75
76&uart0 {
77	status = "okay";
78};
79
80/* on-board eMMC U6 */
81&ap_sdhci0 {
82	pinctrl-names = "default";
83	bus-width = <8>;
84	status = "okay";
85	mmc-ddr-1_8v;
86	vqmmc-supply = <&ap0_reg_mmc_vccq>;
87};
88
89&cp0_syscon0 {
90	cp0_pinctrl: pinctrl {
91		compatible = "marvell,cp115-standalone-pinctrl";
92
93		cp0_i2c0_pins: cp0-i2c-pins-0 {
94			marvell,pins = "mpp37", "mpp38";
95			marvell,function = "i2c0";
96		};
97		cp0_i2c1_pins: cp0-i2c-pins-1 {
98			marvell,pins = "mpp35", "mpp36";
99			marvell,function = "i2c1";
100		};
101		cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
102			marvell,pins = "mpp55";
103			marvell,function = "gpio";
104		};
105		cp0_sdhci_pins: cp0-sdhi-pins-0 {
106			marvell,pins = "mpp56", "mpp57", "mpp58",
107				       "mpp59", "mpp60", "mpp61";
108			marvell,function = "sdio";
109		};
110		cp0_spi0_pins: cp0-spi-pins-0 {
111			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
112			marvell,function = "spi1";
113		};
114	};
115};
116
117&cp0_i2c0 {
118	pinctrl-names = "default";
119	pinctrl-0 = <&cp0_i2c0_pins>;
120	status = "okay";
121	clock-frequency = <100000>;
122	expander0: mcp23x17@20 {
123		compatible = "microchip,mcp23017";
124		gpio-controller;
125		#gpio-cells = <2>;
126		reg = <0x20>;
127		status = "okay";
128	};
129};
130
131&cp0_i2c1 {
132	pinctrl-names = "default";
133	pinctrl-0 = <&cp0_i2c1_pins>;
134	clock-frequency = <100000>;
135	status = "okay";
136};
137
138
139&cp0_sdhci0 {
140	pinctrl-names = "default";
141	pinctrl-0 = <&cp0_sdhci_pins
142		     &cp0_sdhci_cd_pins_crb>;
143	bus-width = <4>;
144	cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
145	vqmmc-supply = <&cp0_reg_sd_vccq>;
146	vmmc-supply = <&cp0_reg_sd_vcc>;
147	status = "okay";
148};
149
150&cp0_spi1 {
151	pinctrl-names = "default";
152	pinctrl-0 = <&cp0_spi0_pins>;
153	reg = <0x700680 0x50>,		/* control */
154	      <0x2000000 0x1000000>;	/* CS0 */
155	status = "okay";
156
157	spi-flash@0 {
158		#address-cells = <0x1>;
159		#size-cells = <0x1>;
160		compatible = "jedec,spi-nor";
161		reg = <0x0>;
162		/* On-board MUX does not allow higher frequencies */
163		spi-max-frequency = <40000000>;
164
165		partitions {
166			compatible = "fixed-partitions";
167			#address-cells = <1>;
168			#size-cells = <1>;
169
170			partition@0 {
171				label = "U-Boot";
172				reg = <0x0 0x200000>;
173			};
174
175			partition@400000 {
176				label = "Filesystem";
177				reg = <0x200000 0xe00000>;
178			};
179		};
180	};
181};
182
183&cp0_mdio {
184	status = "okay";
185	phy0: ethernet-phy@0 {
186		reg = <0>;
187	};
188};
189
190&cp0_xmdio {
191	status = "okay";
192	nbaset_phy0: ethernet-phy@0 {
193		compatible = "ethernet-phy-ieee802.3-c45";
194		reg = <0>;
195	};
196};
197
198&cp0_ethernet {
199	status = "okay";
200};
201
202&cp0_eth0 {
203	/* This port is connected to 88E6393X switch */
204	status = "okay";
205	phy-mode = "10gbase-r";
206	managed = "in-band-status";
207	phys = <&cp0_comphy4 0>;
208};
209
210&cp0_eth1 {
211	status = "okay";
212	phy = <&phy0>;
213	phy-mode = "rgmii-id";
214};
215
216&cp0_eth2 {
217	/* This port uses "2500base-t" phy-mode */
218	status = "disabled";
219	phy = <&nbaset_phy0>;
220	phys = <&cp0_comphy5 2>;
221};
222
223