1*5c0ee547SKonstantin Porotchkin// SPDX-License-Identifier: GPL-2.0+ 2*5c0ee547SKonstantin Porotchkin/* 3*5c0ee547SKonstantin Porotchkin * Copyright (C) 2020 Marvell International Ltd. 4*5c0ee547SKonstantin Porotchkin */ 5*5c0ee547SKonstantin Porotchkin 6*5c0ee547SKonstantin Porotchkin#include "cn9130.dtsi" /* include SoC device tree */ 7*5c0ee547SKonstantin Porotchkin 8*5c0ee547SKonstantin Porotchkin#include <dt-bindings/gpio/gpio.h> 9*5c0ee547SKonstantin Porotchkin 10*5c0ee547SKonstantin Porotchkin/ { 11*5c0ee547SKonstantin Porotchkin chosen { 12*5c0ee547SKonstantin Porotchkin stdout-path = "serial0:115200n8"; 13*5c0ee547SKonstantin Porotchkin }; 14*5c0ee547SKonstantin Porotchkin 15*5c0ee547SKonstantin Porotchkin aliases { 16*5c0ee547SKonstantin Porotchkin i2c0 = &cp0_i2c0; 17*5c0ee547SKonstantin Porotchkin ethernet0 = &cp0_eth0; 18*5c0ee547SKonstantin Porotchkin ethernet1 = &cp0_eth1; 19*5c0ee547SKonstantin Porotchkin ethernet2 = &cp0_eth2; 20*5c0ee547SKonstantin Porotchkin }; 21*5c0ee547SKonstantin Porotchkin 22*5c0ee547SKonstantin Porotchkin memory@00000000 { 23*5c0ee547SKonstantin Porotchkin device_type = "memory"; 24*5c0ee547SKonstantin Porotchkin reg = <0x0 0x0 0x0 0x80000000>; 25*5c0ee547SKonstantin Porotchkin }; 26*5c0ee547SKonstantin Porotchkin 27*5c0ee547SKonstantin Porotchkin ap0_reg_mmc_vccq: ap0_mmc_vccq@0 { 28*5c0ee547SKonstantin Porotchkin compatible = "regulator-gpio"; 29*5c0ee547SKonstantin Porotchkin regulator-name = "ap0_mmc_vccq"; 30*5c0ee547SKonstantin Porotchkin regulator-min-microvolt = <1800000>; 31*5c0ee547SKonstantin Porotchkin regulator-max-microvolt = <3300000>; 32*5c0ee547SKonstantin Porotchkin gpios = <&expander0 5 GPIO_ACTIVE_HIGH>; 33*5c0ee547SKonstantin Porotchkin states = <1800000 0x1 34*5c0ee547SKonstantin Porotchkin 3300000 0x0>; 35*5c0ee547SKonstantin Porotchkin }; 36*5c0ee547SKonstantin Porotchkin 37*5c0ee547SKonstantin Porotchkin cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { 38*5c0ee547SKonstantin Porotchkin compatible = "regulator-fixed"; 39*5c0ee547SKonstantin Porotchkin regulator-name = "cp0-xhci1-vbus"; 40*5c0ee547SKonstantin Porotchkin regulator-min-microvolt = <5000000>; 41*5c0ee547SKonstantin Porotchkin regulator-max-microvolt = <5000000>; 42*5c0ee547SKonstantin Porotchkin enable-active-high; 43*5c0ee547SKonstantin Porotchkin gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; 44*5c0ee547SKonstantin Porotchkin }; 45*5c0ee547SKonstantin Porotchkin 46*5c0ee547SKonstantin Porotchkin cp0_usb3_0_phy0: cp0_usb3_phy0 { 47*5c0ee547SKonstantin Porotchkin compatible = "usb-nop-xceiv"; 48*5c0ee547SKonstantin Porotchkin }; 49*5c0ee547SKonstantin Porotchkin 50*5c0ee547SKonstantin Porotchkin cp0_usb3_0_phy1: cp0_usb3_phy1 { 51*5c0ee547SKonstantin Porotchkin compatible = "usb-nop-xceiv"; 52*5c0ee547SKonstantin Porotchkin vcc-supply = <&cp0_reg_usb3_vbus1>; 53*5c0ee547SKonstantin Porotchkin }; 54*5c0ee547SKonstantin Porotchkin 55*5c0ee547SKonstantin Porotchkin cp0_reg_sd_vccq: cp0_sd_vccq@0 { 56*5c0ee547SKonstantin Porotchkin compatible = "regulator-gpio"; 57*5c0ee547SKonstantin Porotchkin regulator-name = "cp0_sd_vccq"; 58*5c0ee547SKonstantin Porotchkin regulator-min-microvolt = <1800000>; 59*5c0ee547SKonstantin Porotchkin regulator-max-microvolt = <3300000>; 60*5c0ee547SKonstantin Porotchkin gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>; 61*5c0ee547SKonstantin Porotchkin states = <1800000 0x1 62*5c0ee547SKonstantin Porotchkin 3300000 0x0>; 63*5c0ee547SKonstantin Porotchkin }; 64*5c0ee547SKonstantin Porotchkin 65*5c0ee547SKonstantin Porotchkin cp0_reg_sd_vcc: cp0_sd_vcc@0 { 66*5c0ee547SKonstantin Porotchkin compatible = "regulator-fixed"; 67*5c0ee547SKonstantin Porotchkin regulator-name = "cp0_sd_vcc"; 68*5c0ee547SKonstantin Porotchkin regulator-min-microvolt = <3300000>; 69*5c0ee547SKonstantin Porotchkin regulator-max-microvolt = <3300000>; 70*5c0ee547SKonstantin Porotchkin gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; 71*5c0ee547SKonstantin Porotchkin enable-active-high; 72*5c0ee547SKonstantin Porotchkin regulator-always-on; 73*5c0ee547SKonstantin Porotchkin }; 74*5c0ee547SKonstantin Porotchkin}; 75*5c0ee547SKonstantin Porotchkin 76*5c0ee547SKonstantin Porotchkin&uart0 { 77*5c0ee547SKonstantin Porotchkin status = "okay"; 78*5c0ee547SKonstantin Porotchkin}; 79*5c0ee547SKonstantin Porotchkin 80*5c0ee547SKonstantin Porotchkin/* on-board eMMC U6 */ 81*5c0ee547SKonstantin Porotchkin&ap_sdhci0 { 82*5c0ee547SKonstantin Porotchkin pinctrl-names = "default"; 83*5c0ee547SKonstantin Porotchkin bus-width = <8>; 84*5c0ee547SKonstantin Porotchkin status = "okay"; 85*5c0ee547SKonstantin Porotchkin mmc-ddr-1_8v; 86*5c0ee547SKonstantin Porotchkin vqmmc-supply = <&ap0_reg_mmc_vccq>; 87*5c0ee547SKonstantin Porotchkin}; 88*5c0ee547SKonstantin Porotchkin 89*5c0ee547SKonstantin Porotchkin&cp0_syscon0 { 90*5c0ee547SKonstantin Porotchkin cp0_pinctrl: pinctrl { 91*5c0ee547SKonstantin Porotchkin compatible = "marvell,cp115-standalone-pinctrl"; 92*5c0ee547SKonstantin Porotchkin 93*5c0ee547SKonstantin Porotchkin cp0_i2c0_pins: cp0-i2c-pins-0 { 94*5c0ee547SKonstantin Porotchkin marvell,pins = "mpp37", "mpp38"; 95*5c0ee547SKonstantin Porotchkin marvell,function = "i2c0"; 96*5c0ee547SKonstantin Porotchkin }; 97*5c0ee547SKonstantin Porotchkin cp0_i2c1_pins: cp0-i2c-pins-1 { 98*5c0ee547SKonstantin Porotchkin marvell,pins = "mpp35", "mpp36"; 99*5c0ee547SKonstantin Porotchkin marvell,function = "i2c1"; 100*5c0ee547SKonstantin Porotchkin }; 101*5c0ee547SKonstantin Porotchkin cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb { 102*5c0ee547SKonstantin Porotchkin marvell,pins = "mpp55"; 103*5c0ee547SKonstantin Porotchkin marvell,function = "gpio"; 104*5c0ee547SKonstantin Porotchkin }; 105*5c0ee547SKonstantin Porotchkin cp0_sdhci_pins: cp0-sdhi-pins-0 { 106*5c0ee547SKonstantin Porotchkin marvell,pins = "mpp56", "mpp57", "mpp58", 107*5c0ee547SKonstantin Porotchkin "mpp59", "mpp60", "mpp61"; 108*5c0ee547SKonstantin Porotchkin marvell,function = "sdio"; 109*5c0ee547SKonstantin Porotchkin }; 110*5c0ee547SKonstantin Porotchkin cp0_spi0_pins: cp0-spi-pins-0 { 111*5c0ee547SKonstantin Porotchkin marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; 112*5c0ee547SKonstantin Porotchkin marvell,function = "spi1"; 113*5c0ee547SKonstantin Porotchkin }; 114*5c0ee547SKonstantin Porotchkin }; 115*5c0ee547SKonstantin Porotchkin}; 116*5c0ee547SKonstantin Porotchkin 117*5c0ee547SKonstantin Porotchkin&cp0_i2c0 { 118*5c0ee547SKonstantin Porotchkin pinctrl-names = "default"; 119*5c0ee547SKonstantin Porotchkin pinctrl-0 = <&cp0_i2c0_pins>; 120*5c0ee547SKonstantin Porotchkin status = "okay"; 121*5c0ee547SKonstantin Porotchkin clock-frequency = <100000>; 122*5c0ee547SKonstantin Porotchkin expander0: mcp23x17@20 { 123*5c0ee547SKonstantin Porotchkin compatible = "microchip,mcp23017"; 124*5c0ee547SKonstantin Porotchkin gpio-controller; 125*5c0ee547SKonstantin Porotchkin #gpio-cells = <2>; 126*5c0ee547SKonstantin Porotchkin reg = <0x20>; 127*5c0ee547SKonstantin Porotchkin status = "okay"; 128*5c0ee547SKonstantin Porotchkin }; 129*5c0ee547SKonstantin Porotchkin}; 130*5c0ee547SKonstantin Porotchkin 131*5c0ee547SKonstantin Porotchkin&cp0_i2c1 { 132*5c0ee547SKonstantin Porotchkin pinctrl-names = "default"; 133*5c0ee547SKonstantin Porotchkin pinctrl-0 = <&cp0_i2c1_pins>; 134*5c0ee547SKonstantin Porotchkin clock-frequency = <100000>; 135*5c0ee547SKonstantin Porotchkin status = "okay"; 136*5c0ee547SKonstantin Porotchkin}; 137*5c0ee547SKonstantin Porotchkin 138*5c0ee547SKonstantin Porotchkin 139*5c0ee547SKonstantin Porotchkin&cp0_sdhci0 { 140*5c0ee547SKonstantin Porotchkin pinctrl-names = "default"; 141*5c0ee547SKonstantin Porotchkin pinctrl-0 = <&cp0_sdhci_pins 142*5c0ee547SKonstantin Porotchkin &cp0_sdhci_cd_pins_crb>; 143*5c0ee547SKonstantin Porotchkin bus-width = <4>; 144*5c0ee547SKonstantin Porotchkin cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>; 145*5c0ee547SKonstantin Porotchkin vqmmc-supply = <&cp0_reg_sd_vccq>; 146*5c0ee547SKonstantin Porotchkin vmmc-supply = <&cp0_reg_sd_vcc>; 147*5c0ee547SKonstantin Porotchkin status = "okay"; 148*5c0ee547SKonstantin Porotchkin}; 149*5c0ee547SKonstantin Porotchkin 150*5c0ee547SKonstantin Porotchkin&cp0_spi1 { 151*5c0ee547SKonstantin Porotchkin pinctrl-names = "default"; 152*5c0ee547SKonstantin Porotchkin pinctrl-0 = <&cp0_spi0_pins>; 153*5c0ee547SKonstantin Porotchkin reg = <0x700680 0x50>, /* control */ 154*5c0ee547SKonstantin Porotchkin <0x2000000 0x1000000>; /* CS0 */ 155*5c0ee547SKonstantin Porotchkin status = "okay"; 156*5c0ee547SKonstantin Porotchkin 157*5c0ee547SKonstantin Porotchkin spi-flash@0 { 158*5c0ee547SKonstantin Porotchkin #address-cells = <0x1>; 159*5c0ee547SKonstantin Porotchkin #size-cells = <0x1>; 160*5c0ee547SKonstantin Porotchkin compatible = "jedec,spi-nor"; 161*5c0ee547SKonstantin Porotchkin reg = <0x0>; 162*5c0ee547SKonstantin Porotchkin /* On-board MUX does not allow higher frequencies */ 163*5c0ee547SKonstantin Porotchkin spi-max-frequency = <40000000>; 164*5c0ee547SKonstantin Porotchkin 165*5c0ee547SKonstantin Porotchkin partitions { 166*5c0ee547SKonstantin Porotchkin compatible = "fixed-partitions"; 167*5c0ee547SKonstantin Porotchkin #address-cells = <1>; 168*5c0ee547SKonstantin Porotchkin #size-cells = <1>; 169*5c0ee547SKonstantin Porotchkin 170*5c0ee547SKonstantin Porotchkin partition@0 { 171*5c0ee547SKonstantin Porotchkin label = "U-Boot"; 172*5c0ee547SKonstantin Porotchkin reg = <0x0 0x200000>; 173*5c0ee547SKonstantin Porotchkin }; 174*5c0ee547SKonstantin Porotchkin 175*5c0ee547SKonstantin Porotchkin partition@400000 { 176*5c0ee547SKonstantin Porotchkin label = "Filesystem"; 177*5c0ee547SKonstantin Porotchkin reg = <0x200000 0xe00000>; 178*5c0ee547SKonstantin Porotchkin }; 179*5c0ee547SKonstantin Porotchkin }; 180*5c0ee547SKonstantin Porotchkin }; 181*5c0ee547SKonstantin Porotchkin}; 182*5c0ee547SKonstantin Porotchkin 183*5c0ee547SKonstantin Porotchkin&cp0_mdio { 184*5c0ee547SKonstantin Porotchkin status = "okay"; 185*5c0ee547SKonstantin Porotchkin phy0: ethernet-phy@0 { 186*5c0ee547SKonstantin Porotchkin reg = <0>; 187*5c0ee547SKonstantin Porotchkin }; 188*5c0ee547SKonstantin Porotchkin}; 189*5c0ee547SKonstantin Porotchkin 190*5c0ee547SKonstantin Porotchkin&cp0_xmdio { 191*5c0ee547SKonstantin Porotchkin status = "okay"; 192*5c0ee547SKonstantin Porotchkin nbaset_phy0: ethernet-phy@0 { 193*5c0ee547SKonstantin Porotchkin compatible = "ethernet-phy-ieee802.3-c45"; 194*5c0ee547SKonstantin Porotchkin reg = <0>; 195*5c0ee547SKonstantin Porotchkin }; 196*5c0ee547SKonstantin Porotchkin}; 197*5c0ee547SKonstantin Porotchkin 198*5c0ee547SKonstantin Porotchkin&cp0_ethernet { 199*5c0ee547SKonstantin Porotchkin status = "okay"; 200*5c0ee547SKonstantin Porotchkin}; 201*5c0ee547SKonstantin Porotchkin 202*5c0ee547SKonstantin Porotchkin&cp0_eth0 { 203*5c0ee547SKonstantin Porotchkin /* This port is connected to 88E6393X switch */ 204*5c0ee547SKonstantin Porotchkin status = "okay"; 205*5c0ee547SKonstantin Porotchkin phy-mode = "10gbase-kr"; 206*5c0ee547SKonstantin Porotchkin managed = "in-band-status"; 207*5c0ee547SKonstantin Porotchkin phys = <&cp0_comphy4 0>; 208*5c0ee547SKonstantin Porotchkin}; 209*5c0ee547SKonstantin Porotchkin 210*5c0ee547SKonstantin Porotchkin&cp0_eth1 { 211*5c0ee547SKonstantin Porotchkin status = "okay"; 212*5c0ee547SKonstantin Porotchkin phy = <&phy0>; 213*5c0ee547SKonstantin Porotchkin phy-mode = "rgmii-id"; 214*5c0ee547SKonstantin Porotchkin}; 215*5c0ee547SKonstantin Porotchkin 216*5c0ee547SKonstantin Porotchkin&cp0_eth2 { 217*5c0ee547SKonstantin Porotchkin /* This port uses "2500base-t" phy-mode */ 218*5c0ee547SKonstantin Porotchkin status = "disabled"; 219*5c0ee547SKonstantin Porotchkin phy = <&nbaset_phy0>; 220*5c0ee547SKonstantin Porotchkin phys = <&cp0_comphy5 2>; 221*5c0ee547SKonstantin Porotchkin}; 222*5c0ee547SKonstantin Porotchkin 223