1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada CP11x.
6 */
7
8#include <dt-bindings/interrupt-controller/mvebu-icu.h>
9#include <dt-bindings/thermal/thermal.h>
10
11#include "armada-common.dtsi"
12
13#define CP11X_PCIEx_CONF_BASE(iface)	(CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
14
15/ {
16	/*
17	 * The contents of the node are defined below, in order to
18	 * save one indentation level
19	 */
20	CP11X_NAME: CP11X_NAME { };
21
22	/*
23	 * CPs only have one sensor in the thermal IC.
24	 *
25	 * The cooling maps are empty as there are no cooling devices.
26	 */
27	thermal-zones {
28		CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
29			polling-delay-passive = <0>; /* Interrupt driven */
30			polling-delay = <0>; /* Interrupt driven */
31
32			thermal-sensors = <&CP11X_LABEL(thermal) 0>;
33
34			trips {
35				CP11X_LABEL(crit): crit {
36					temperature = <100000>; /* mC degrees */
37					hysteresis = <2000>; /* mC degrees */
38					type = "critical";
39				};
40			};
41
42			cooling-maps { };
43		};
44	};
45};
46
47&CP11X_NAME {
48	#address-cells = <2>;
49	#size-cells = <2>;
50	compatible = "simple-bus";
51	interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
52	ranges;
53
54	config-space@CP11X_BASE {
55		#address-cells = <1>;
56		#size-cells = <1>;
57		compatible = "simple-bus";
58		ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
59
60		CP11X_LABEL(ethernet): ethernet@0 {
61			compatible = "marvell,armada-7k-pp22";
62			reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
63			clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
64				 <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
65				 <&CP11X_LABEL(clk) 1 18>;
66			clock-names = "pp_clk", "gop_clk",
67				      "mg_clk", "mg_core_clk", "axi_clk";
68			marvell,system-controller = <&CP11X_LABEL(syscon0)>;
69			status = "disabled";
70			dma-coherent;
71
72			CP11X_LABEL(eth0): eth0 {
73				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
74					<43 IRQ_TYPE_LEVEL_HIGH>,
75					<47 IRQ_TYPE_LEVEL_HIGH>,
76					<51 IRQ_TYPE_LEVEL_HIGH>,
77					<55 IRQ_TYPE_LEVEL_HIGH>,
78					<59 IRQ_TYPE_LEVEL_HIGH>,
79					<63 IRQ_TYPE_LEVEL_HIGH>,
80					<67 IRQ_TYPE_LEVEL_HIGH>,
81					<71 IRQ_TYPE_LEVEL_HIGH>,
82					<129 IRQ_TYPE_LEVEL_HIGH>;
83				interrupt-names = "hif0", "hif1", "hif2",
84					"hif3", "hif4", "hif5", "hif6", "hif7",
85					"hif8", "link";
86				port-id = <0>;
87				gop-port-id = <0>;
88				status = "disabled";
89			};
90
91			CP11X_LABEL(eth1): eth1 {
92				interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
93					<44 IRQ_TYPE_LEVEL_HIGH>,
94					<48 IRQ_TYPE_LEVEL_HIGH>,
95					<52 IRQ_TYPE_LEVEL_HIGH>,
96					<56 IRQ_TYPE_LEVEL_HIGH>,
97					<60 IRQ_TYPE_LEVEL_HIGH>,
98					<64 IRQ_TYPE_LEVEL_HIGH>,
99					<68 IRQ_TYPE_LEVEL_HIGH>,
100					<72 IRQ_TYPE_LEVEL_HIGH>,
101					<128 IRQ_TYPE_LEVEL_HIGH>;
102				interrupt-names = "hif0", "hif1", "hif2",
103					"hif3", "hif4", "hif5", "hif6", "hif7",
104					"hif8", "link";
105				port-id = <1>;
106				gop-port-id = <2>;
107				status = "disabled";
108			};
109
110			CP11X_LABEL(eth2): eth2 {
111				interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
112					<45 IRQ_TYPE_LEVEL_HIGH>,
113					<49 IRQ_TYPE_LEVEL_HIGH>,
114					<53 IRQ_TYPE_LEVEL_HIGH>,
115					<57 IRQ_TYPE_LEVEL_HIGH>,
116					<61 IRQ_TYPE_LEVEL_HIGH>,
117					<65 IRQ_TYPE_LEVEL_HIGH>,
118					<69 IRQ_TYPE_LEVEL_HIGH>,
119					<73 IRQ_TYPE_LEVEL_HIGH>,
120					<127 IRQ_TYPE_LEVEL_HIGH>;
121				interrupt-names = "hif0", "hif1", "hif2",
122					"hif3", "hif4", "hif5", "hif6", "hif7",
123					"hif8", "link";
124				port-id = <2>;
125				gop-port-id = <3>;
126				status = "disabled";
127			};
128		};
129
130		CP11X_LABEL(comphy): phy@120000 {
131			compatible = "marvell,comphy-cp110";
132			reg = <0x120000 0x6000>;
133			marvell,system-controller = <&CP11X_LABEL(syscon0)>;
134			clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
135				 <&CP11X_LABEL(clk) 1 18>;
136			clock-names = "mg_clk", "mg_core_clk", "axi_clk";
137			#address-cells = <1>;
138			#size-cells = <0>;
139
140			CP11X_LABEL(comphy0): phy@0 {
141				reg = <0>;
142				#phy-cells = <1>;
143			};
144
145			CP11X_LABEL(comphy1): phy@1 {
146				reg = <1>;
147				#phy-cells = <1>;
148			};
149
150			CP11X_LABEL(comphy2): phy@2 {
151				reg = <2>;
152				#phy-cells = <1>;
153			};
154
155			CP11X_LABEL(comphy3): phy@3 {
156				reg = <3>;
157				#phy-cells = <1>;
158			};
159
160			CP11X_LABEL(comphy4): phy@4 {
161				reg = <4>;
162				#phy-cells = <1>;
163			};
164
165			CP11X_LABEL(comphy5): phy@5 {
166				reg = <5>;
167				#phy-cells = <1>;
168			};
169		};
170
171		CP11X_LABEL(mdio): mdio@12a200 {
172			#address-cells = <1>;
173			#size-cells = <0>;
174			compatible = "marvell,orion-mdio";
175			reg = <0x12a200 0x10>;
176			clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
177				 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
178			status = "disabled";
179		};
180
181		CP11X_LABEL(xmdio): mdio@12a600 {
182			#address-cells = <1>;
183			#size-cells = <0>;
184			compatible = "marvell,xmdio";
185			reg = <0x12a600 0x10>;
186			clocks = <&CP11X_LABEL(clk) 1 5>,
187				 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
188			status = "disabled";
189		};
190
191		CP11X_LABEL(icu): interrupt-controller@1e0000 {
192			compatible = "marvell,cp110-icu";
193			reg = <0x1e0000 0x440>;
194			#address-cells = <1>;
195			#size-cells = <1>;
196
197			CP11X_LABEL(icu_nsr): interrupt-controller@10 {
198				compatible = "marvell,cp110-icu-nsr";
199				reg = <0x10 0x20>;
200				#interrupt-cells = <2>;
201				interrupt-controller;
202				msi-parent = <&gicp>;
203			};
204
205			CP11X_LABEL(icu_sei): interrupt-controller@50 {
206				compatible = "marvell,cp110-icu-sei";
207				reg = <0x50 0x10>;
208				#interrupt-cells = <2>;
209				interrupt-controller;
210				msi-parent = <&sei>;
211			};
212		};
213
214		CP11X_LABEL(rtc): rtc@284000 {
215			compatible = "marvell,armada-8k-rtc";
216			reg = <0x284000 0x20>, <0x284080 0x24>;
217			reg-names = "rtc", "rtc-soc";
218			interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
219		};
220
221		CP11X_LABEL(syscon0): system-controller@440000 {
222			compatible = "syscon", "simple-mfd";
223			reg = <0x440000 0x2000>;
224
225			CP11X_LABEL(clk): clock {
226				compatible = "marvell,cp110-clock";
227				#clock-cells = <2>;
228			};
229
230			CP11X_LABEL(gpio1): gpio@100 {
231				compatible = "marvell,armada-8k-gpio";
232				offset = <0x100>;
233				ngpios = <32>;
234				gpio-controller;
235				#gpio-cells = <2>;
236				gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
237				marvell,pwm-offset = <0x1f0>;
238				#pwm-cells = <2>;
239				interrupt-controller;
240				interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
241					<85 IRQ_TYPE_LEVEL_HIGH>,
242					<84 IRQ_TYPE_LEVEL_HIGH>,
243					<83 IRQ_TYPE_LEVEL_HIGH>;
244				#interrupt-cells = <2>;
245				clock-names = "core", "axi";
246				clocks = <&CP11X_LABEL(clk) 1 21>,
247					 <&CP11X_LABEL(clk) 1 17>;
248				status = "disabled";
249			};
250
251			CP11X_LABEL(gpio2): gpio@140 {
252				compatible = "marvell,armada-8k-gpio";
253				offset = <0x140>;
254				ngpios = <31>;
255				gpio-controller;
256				#gpio-cells = <2>;
257				gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
258				marvell,pwm-offset = <0x1f0>;
259				#pwm-cells = <2>;
260				interrupt-controller;
261				interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
262					<81 IRQ_TYPE_LEVEL_HIGH>,
263					<80 IRQ_TYPE_LEVEL_HIGH>,
264					<79 IRQ_TYPE_LEVEL_HIGH>;
265				#interrupt-cells = <2>;
266				clock-names = "core", "axi";
267				clocks = <&CP11X_LABEL(clk) 1 21>,
268					 <&CP11X_LABEL(clk) 1 17>;
269				status = "disabled";
270			};
271		};
272
273		CP11X_LABEL(syscon1): system-controller@400000 {
274			compatible = "syscon", "simple-mfd";
275			reg = <0x400000 0x1000>;
276			#address-cells = <1>;
277			#size-cells = <1>;
278
279			CP11X_LABEL(thermal): thermal-sensor@70 {
280				compatible = "marvell,armada-cp110-thermal";
281				reg = <0x70 0x10>;
282				interrupts-extended =
283					<&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
284				#thermal-sensor-cells = <1>;
285			};
286		};
287
288		CP11X_LABEL(usb3_0): usb@500000 {
289			compatible = "marvell,armada-8k-xhci",
290			"generic-xhci";
291			reg = <0x500000 0x4000>;
292			dma-coherent;
293			interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
294			clock-names = "core", "reg";
295			clocks = <&CP11X_LABEL(clk) 1 22>,
296				 <&CP11X_LABEL(clk) 1 16>;
297			status = "disabled";
298		};
299
300		CP11X_LABEL(usb3_1): usb@510000 {
301			compatible = "marvell,armada-8k-xhci",
302			"generic-xhci";
303			reg = <0x510000 0x4000>;
304			dma-coherent;
305			interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
306			clock-names = "core", "reg";
307			clocks = <&CP11X_LABEL(clk) 1 23>,
308				 <&CP11X_LABEL(clk) 1 16>;
309			status = "disabled";
310		};
311
312		CP11X_LABEL(sata0): sata@540000 {
313			compatible = "marvell,armada-8k-ahci",
314			"generic-ahci";
315			reg = <0x540000 0x30000>;
316			dma-coherent;
317			interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
318			clocks = <&CP11X_LABEL(clk) 1 15>,
319				 <&CP11X_LABEL(clk) 1 16>;
320			#address-cells = <1>;
321			#size-cells = <0>;
322			status = "disabled";
323
324			sata-port@0 {
325				reg = <0>;
326			};
327
328			sata-port@1 {
329				reg = <1>;
330			};
331		};
332
333		CP11X_LABEL(xor0): xor@6a0000 {
334			compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
335			reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
336			dma-coherent;
337			msi-parent = <&gic_v2m0>;
338			clock-names = "core", "reg";
339			clocks = <&CP11X_LABEL(clk) 1 8>,
340				 <&CP11X_LABEL(clk) 1 14>;
341		};
342
343		CP11X_LABEL(xor1): xor@6c0000 {
344			compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
345			reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
346			dma-coherent;
347			msi-parent = <&gic_v2m0>;
348			clock-names = "core", "reg";
349			clocks = <&CP11X_LABEL(clk) 1 7>,
350				 <&CP11X_LABEL(clk) 1 14>;
351		};
352
353		CP11X_LABEL(spi0): spi@700600 {
354			compatible = "marvell,armada-380-spi";
355			reg = <0x700600 0x50>;
356			#address-cells = <0x1>;
357			#size-cells = <0x0>;
358			clock-names = "core", "axi";
359			clocks = <&CP11X_LABEL(clk) 1 21>,
360				 <&CP11X_LABEL(clk) 1 17>;
361			status = "disabled";
362		};
363
364		CP11X_LABEL(spi1): spi@700680 {
365			compatible = "marvell,armada-380-spi";
366			reg = <0x700680 0x50>;
367			#address-cells = <1>;
368			#size-cells = <0>;
369			clock-names = "core", "axi";
370			clocks = <&CP11X_LABEL(clk) 1 21>,
371				 <&CP11X_LABEL(clk) 1 17>;
372			status = "disabled";
373		};
374
375		CP11X_LABEL(i2c0): i2c@701000 {
376			compatible = "marvell,mv78230-i2c";
377			reg = <0x701000 0x20>;
378			#address-cells = <1>;
379			#size-cells = <0>;
380			interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
381			clock-names = "core", "reg";
382			clocks = <&CP11X_LABEL(clk) 1 21>,
383				 <&CP11X_LABEL(clk) 1 17>;
384			status = "disabled";
385		};
386
387		CP11X_LABEL(i2c1): i2c@701100 {
388			compatible = "marvell,mv78230-i2c";
389			reg = <0x701100 0x20>;
390			#address-cells = <1>;
391			#size-cells = <0>;
392			interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
393			clock-names = "core", "reg";
394			clocks = <&CP11X_LABEL(clk) 1 21>,
395				 <&CP11X_LABEL(clk) 1 17>;
396			status = "disabled";
397		};
398
399		CP11X_LABEL(uart0): serial@702000 {
400			compatible = "snps,dw-apb-uart";
401			reg = <0x702000 0x100>;
402			reg-shift = <2>;
403			interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
404			reg-io-width = <1>;
405			clock-names = "baudclk", "apb_pclk";
406			clocks = <&CP11X_LABEL(clk) 1 21>,
407				 <&CP11X_LABEL(clk) 1 17>;
408			status = "disabled";
409		};
410
411		CP11X_LABEL(uart1): serial@702100 {
412			compatible = "snps,dw-apb-uart";
413			reg = <0x702100 0x100>;
414			reg-shift = <2>;
415			interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
416			reg-io-width = <1>;
417			clock-names = "baudclk", "apb_pclk";
418			clocks = <&CP11X_LABEL(clk) 1 21>,
419				 <&CP11X_LABEL(clk) 1 17>;
420			status = "disabled";
421		};
422
423		CP11X_LABEL(uart2): serial@702200 {
424			compatible = "snps,dw-apb-uart";
425			reg = <0x702200 0x100>;
426			reg-shift = <2>;
427			interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
428			reg-io-width = <1>;
429			clock-names = "baudclk", "apb_pclk";
430			clocks = <&CP11X_LABEL(clk) 1 21>,
431				 <&CP11X_LABEL(clk) 1 17>;
432			status = "disabled";
433		};
434
435		CP11X_LABEL(uart3): serial@702300 {
436			compatible = "snps,dw-apb-uart";
437			reg = <0x702300 0x100>;
438			reg-shift = <2>;
439			interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
440			reg-io-width = <1>;
441			clock-names = "baudclk", "apb_pclk";
442			clocks = <&CP11X_LABEL(clk) 1 21>,
443				 <&CP11X_LABEL(clk) 1 17>;
444			status = "disabled";
445		};
446
447		CP11X_LABEL(nand_controller): nand@720000 {
448			/*
449			 * Due to the limitation of the pins available
450			 * this controller is only usable on the CPM
451			 * for A7K and on the CPS for A8K.
452			 */
453			compatible = "marvell,armada-8k-nand-controller",
454				"marvell,armada370-nand-controller";
455			reg = <0x720000 0x54>;
456			#address-cells = <1>;
457			#size-cells = <0>;
458			interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
459			clock-names = "core", "reg";
460			clocks = <&CP11X_LABEL(clk) 1 2>,
461				 <&CP11X_LABEL(clk) 1 17>;
462			marvell,system-controller = <&CP11X_LABEL(syscon0)>;
463			status = "disabled";
464		};
465
466		CP11X_LABEL(trng): trng@760000 {
467			compatible = "marvell,armada-8k-rng",
468			"inside-secure,safexcel-eip76";
469			reg = <0x760000 0x7d>;
470			interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
471			clock-names = "core", "reg";
472			clocks = <&CP11X_LABEL(clk) 1 25>,
473				 <&CP11X_LABEL(clk) 1 17>;
474			status = "okay";
475		};
476
477		CP11X_LABEL(sdhci0): sdhci@780000 {
478			compatible = "marvell,armada-cp110-sdhci";
479			reg = <0x780000 0x300>;
480			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
481			clock-names = "core", "axi";
482			clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
483			dma-coherent;
484			status = "disabled";
485		};
486
487		CP11X_LABEL(crypto): crypto@800000 {
488			compatible = "inside-secure,safexcel-eip197b";
489			reg = <0x800000 0x200000>;
490			interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
491				<88 IRQ_TYPE_LEVEL_HIGH>,
492				<89 IRQ_TYPE_LEVEL_HIGH>,
493				<90 IRQ_TYPE_LEVEL_HIGH>,
494				<91 IRQ_TYPE_LEVEL_HIGH>,
495				<92 IRQ_TYPE_LEVEL_HIGH>;
496			interrupt-names = "mem", "ring0", "ring1",
497				"ring2", "ring3", "eip";
498			clock-names = "core", "reg";
499			clocks = <&CP11X_LABEL(clk) 1 26>,
500				 <&CP11X_LABEL(clk) 1 17>;
501			dma-coherent;
502		};
503	};
504
505	CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
506		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
507		reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
508		      <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
509		reg-names = "ctrl", "config";
510		#address-cells = <3>;
511		#size-cells = <2>;
512		#interrupt-cells = <1>;
513		device_type = "pci";
514		dma-coherent;
515		msi-parent = <&gic_v2m0>;
516
517		bus-range = <0 0xff>;
518		/* non-prefetchable memory */
519		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0  CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
520		interrupt-map-mask = <0 0 0 0>;
521		interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
522		interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
523		num-lanes = <1>;
524		clock-names = "core", "reg";
525		clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
526		status = "disabled";
527	};
528
529	CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
530		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
531		reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
532		      <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
533		reg-names = "ctrl", "config";
534		#address-cells = <3>;
535		#size-cells = <2>;
536		#interrupt-cells = <1>;
537		device_type = "pci";
538		dma-coherent;
539		msi-parent = <&gic_v2m0>;
540
541		bus-range = <0 0xff>;
542		/* non-prefetchable memory */
543		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0  CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
544		interrupt-map-mask = <0 0 0 0>;
545		interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
546		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
547
548		num-lanes = <1>;
549		clock-names = "core", "reg";
550		clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
551		status = "disabled";
552	};
553
554	CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
555		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
556		reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
557		      <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
558		reg-names = "ctrl", "config";
559		#address-cells = <3>;
560		#size-cells = <2>;
561		#interrupt-cells = <1>;
562		device_type = "pci";
563		dma-coherent;
564		msi-parent = <&gic_v2m0>;
565
566		bus-range = <0 0xff>;
567		/* non-prefetchable memory */
568		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0  CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
569		interrupt-map-mask = <0 0 0 0>;
570		interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
571		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
572
573		num-lanes = <1>;
574		clock-names = "core", "reg";
575		clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
576		status = "disabled";
577	};
578};
579