1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada AP806. 45 */ 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49/dts-v1/; 50 51/ { 52 model = "Marvell Armada AP806"; 53 compatible = "marvell,armada-ap806"; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 57 aliases { 58 serial0 = &uart0; 59 serial1 = &uart1; 60 gpio0 = &ap_gpio; 61 spi0 = &spi0; 62 }; 63 64 psci { 65 compatible = "arm,psci-0.2"; 66 method = "smc"; 67 }; 68 69 ap806 { 70 #address-cells = <2>; 71 #size-cells = <2>; 72 compatible = "simple-bus"; 73 interrupt-parent = <&gic>; 74 ranges; 75 76 config-space@f0000000 { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 compatible = "simple-bus"; 80 ranges = <0x0 0x0 0xf0000000 0x1000000>; 81 82 gic: interrupt-controller@210000 { 83 compatible = "arm,gic-400"; 84 #interrupt-cells = <3>; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges; 88 interrupt-controller; 89 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 90 reg = <0x210000 0x10000>, 91 <0x220000 0x20000>, 92 <0x240000 0x20000>, 93 <0x260000 0x20000>; 94 95 gic_v2m0: v2m@280000 { 96 compatible = "arm,gic-v2m-frame"; 97 msi-controller; 98 reg = <0x280000 0x1000>; 99 arm,msi-base-spi = <160>; 100 arm,msi-num-spis = <32>; 101 }; 102 gic_v2m1: v2m@290000 { 103 compatible = "arm,gic-v2m-frame"; 104 msi-controller; 105 reg = <0x290000 0x1000>; 106 arm,msi-base-spi = <192>; 107 arm,msi-num-spis = <32>; 108 }; 109 gic_v2m2: v2m@2a0000 { 110 compatible = "arm,gic-v2m-frame"; 111 msi-controller; 112 reg = <0x2a0000 0x1000>; 113 arm,msi-base-spi = <224>; 114 arm,msi-num-spis = <32>; 115 }; 116 gic_v2m3: v2m@2b0000 { 117 compatible = "arm,gic-v2m-frame"; 118 msi-controller; 119 reg = <0x2b0000 0x1000>; 120 arm,msi-base-spi = <256>; 121 arm,msi-num-spis = <32>; 122 }; 123 }; 124 125 timer { 126 compatible = "arm,armv8-timer"; 127 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 129 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 131 }; 132 133 pmu { 134 compatible = "arm,cortex-a72-pmu"; 135 interrupt-parent = <&pic>; 136 interrupts = <17>; 137 }; 138 139 odmi: odmi@300000 { 140 compatible = "marvell,odmi-controller"; 141 interrupt-controller; 142 msi-controller; 143 marvell,odmi-frames = <4>; 144 reg = <0x300000 0x4000>, 145 <0x304000 0x4000>, 146 <0x308000 0x4000>, 147 <0x30C000 0x4000>; 148 marvell,spi-base = <128>, <136>, <144>, <152>; 149 }; 150 151 gicp: gicp@3f0040 { 152 compatible = "marvell,ap806-gicp"; 153 reg = <0x3f0040 0x10>; 154 marvell,spi-ranges = <64 64>, <288 64>; 155 msi-controller; 156 }; 157 158 pic: interrupt-controller@3f0100 { 159 compatible = "marvell,armada-8k-pic"; 160 reg = <0x3f0100 0x10>; 161 #interrupt-cells = <1>; 162 interrupt-controller; 163 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 xor@400000 { 167 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 168 reg = <0x400000 0x1000>, 169 <0x410000 0x1000>; 170 msi-parent = <&gic_v2m0>; 171 clocks = <&ap_clk 3>; 172 dma-coherent; 173 }; 174 175 xor@420000 { 176 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 177 reg = <0x420000 0x1000>, 178 <0x430000 0x1000>; 179 msi-parent = <&gic_v2m0>; 180 clocks = <&ap_clk 3>; 181 dma-coherent; 182 }; 183 184 xor@440000 { 185 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 186 reg = <0x440000 0x1000>, 187 <0x450000 0x1000>; 188 msi-parent = <&gic_v2m0>; 189 clocks = <&ap_clk 3>; 190 dma-coherent; 191 }; 192 193 xor@460000 { 194 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 195 reg = <0x460000 0x1000>, 196 <0x470000 0x1000>; 197 msi-parent = <&gic_v2m0>; 198 clocks = <&ap_clk 3>; 199 dma-coherent; 200 }; 201 202 spi0: spi@510600 { 203 compatible = "marvell,armada-380-spi"; 204 reg = <0x510600 0x50>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&ap_clk 3>; 209 status = "disabled"; 210 }; 211 212 i2c0: i2c@511000 { 213 compatible = "marvell,mv78230-i2c"; 214 reg = <0x511000 0x20>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 218 timeout-ms = <1000>; 219 clocks = <&ap_clk 3>; 220 status = "disabled"; 221 }; 222 223 uart0: serial@512000 { 224 compatible = "snps,dw-apb-uart"; 225 reg = <0x512000 0x100>; 226 reg-shift = <2>; 227 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 228 reg-io-width = <1>; 229 clocks = <&ap_clk 3>; 230 status = "disabled"; 231 }; 232 233 uart1: serial@512100 { 234 compatible = "snps,dw-apb-uart"; 235 reg = <0x512100 0x100>; 236 reg-shift = <2>; 237 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 238 reg-io-width = <1>; 239 clocks = <&ap_clk 3>; 240 status = "disabled"; 241 242 }; 243 244 watchdog: watchdog@610000 { 245 compatible = "arm,sbsa-gwdt"; 246 reg = <0x610000 0x1000>, <0x600000 0x1000>; 247 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 248 }; 249 250 ap_sdhci0: sdhci@6e0000 { 251 compatible = "marvell,armada-ap806-sdhci"; 252 reg = <0x6e0000 0x300>; 253 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 254 clock-names = "core"; 255 clocks = <&ap_clk 4>; 256 dma-coherent; 257 marvell,xenon-phy-slow-mode; 258 status = "disabled"; 259 }; 260 261 ap_syscon: system-controller@6f4000 { 262 compatible = "syscon", "simple-mfd"; 263 reg = <0x6f4000 0x2000>; 264 265 ap_clk: clock { 266 compatible = "marvell,ap806-clock"; 267 #clock-cells = <1>; 268 }; 269 270 ap_pinctrl: pinctrl { 271 compatible = "marvell,ap806-pinctrl"; 272 273 uart0_pins: uart0-pins { 274 marvell,pins = "mpp11", "mpp19"; 275 marvell,function = "uart0"; 276 }; 277 }; 278 279 ap_gpio: gpio@1040 { 280 compatible = "marvell,armada-8k-gpio"; 281 offset = <0x1040>; 282 ngpios = <20>; 283 gpio-controller; 284 #gpio-cells = <2>; 285 gpio-ranges = <&ap_pinctrl 0 0 20>; 286 }; 287 }; 288 289 ap_thermal: thermal@6f808c { 290 compatible = "marvell,armada-ap806-thermal"; 291 reg = <0x6f808c 0x4>, 292 <0x6f8084 0x8>; 293 }; 294 }; 295 }; 296}; 297