1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada AP806.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/thermal/thermal.h>
10
11/dts-v1/;
12
13/ {
14	model = "Marvell Armada AP806";
15	compatible = "marvell,armada-ap806";
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	aliases {
20		serial0 = &uart0;
21		serial1 = &uart1;
22		gpio0 = &ap_gpio;
23		spi0 = &spi0;
24	};
25
26	psci {
27		compatible = "arm,psci-0.2";
28		method = "smc";
29	};
30
31	ap806 {
32		#address-cells = <2>;
33		#size-cells = <2>;
34		compatible = "simple-bus";
35		interrupt-parent = <&gic>;
36		ranges;
37
38		config-space@f0000000 {
39			#address-cells = <1>;
40			#size-cells = <1>;
41			compatible = "simple-bus";
42			ranges = <0x0 0x0 0xf0000000 0x1000000>;
43
44			gic: interrupt-controller@210000 {
45				compatible = "arm,gic-400";
46				#interrupt-cells = <3>;
47				#address-cells = <1>;
48				#size-cells = <1>;
49				ranges;
50				interrupt-controller;
51				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
52				reg = <0x210000 0x10000>,
53				      <0x220000 0x20000>,
54				      <0x240000 0x20000>,
55				      <0x260000 0x20000>;
56
57				gic_v2m0: v2m@280000 {
58					compatible = "arm,gic-v2m-frame";
59					msi-controller;
60					reg = <0x280000 0x1000>;
61					arm,msi-base-spi = <160>;
62					arm,msi-num-spis = <32>;
63				};
64				gic_v2m1: v2m@290000 {
65					compatible = "arm,gic-v2m-frame";
66					msi-controller;
67					reg = <0x290000 0x1000>;
68					arm,msi-base-spi = <192>;
69					arm,msi-num-spis = <32>;
70				};
71				gic_v2m2: v2m@2a0000 {
72					compatible = "arm,gic-v2m-frame";
73					msi-controller;
74					reg = <0x2a0000 0x1000>;
75					arm,msi-base-spi = <224>;
76					arm,msi-num-spis = <32>;
77				};
78				gic_v2m3: v2m@2b0000 {
79					compatible = "arm,gic-v2m-frame";
80					msi-controller;
81					reg = <0x2b0000 0x1000>;
82					arm,msi-base-spi = <256>;
83					arm,msi-num-spis = <32>;
84				};
85			};
86
87			timer {
88				compatible = "arm,armv8-timer";
89				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93			};
94
95			pmu {
96				compatible = "arm,cortex-a72-pmu";
97				interrupt-parent = <&pic>;
98				interrupts = <17>;
99			};
100
101			odmi: odmi@300000 {
102				compatible = "marvell,odmi-controller";
103				interrupt-controller;
104				msi-controller;
105				marvell,odmi-frames = <4>;
106				reg = <0x300000 0x4000>,
107				      <0x304000 0x4000>,
108				      <0x308000 0x4000>,
109				      <0x30C000 0x4000>;
110				marvell,spi-base = <128>, <136>, <144>, <152>;
111			};
112
113			gicp: gicp@3f0040 {
114				compatible = "marvell,ap806-gicp";
115				reg = <0x3f0040 0x10>;
116				marvell,spi-ranges = <64 64>, <288 64>;
117				msi-controller;
118			};
119
120			pic: interrupt-controller@3f0100 {
121				compatible = "marvell,armada-8k-pic";
122				reg = <0x3f0100 0x10>;
123				#interrupt-cells = <1>;
124				interrupt-controller;
125				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
126			};
127
128			sei: interrupt-controller@3f0200 {
129				compatible = "marvell,ap806-sei";
130				reg = <0x3f0200 0x40>;
131				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
132				#interrupt-cells = <1>;
133				interrupt-controller;
134				msi-controller;
135			};
136
137			xor@400000 {
138				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
139				reg = <0x400000 0x1000>,
140				      <0x410000 0x1000>;
141				msi-parent = <&gic_v2m0>;
142				clocks = <&ap_clk 3>;
143				dma-coherent;
144			};
145
146			xor@420000 {
147				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
148				reg = <0x420000 0x1000>,
149				      <0x430000 0x1000>;
150				msi-parent = <&gic_v2m0>;
151				clocks = <&ap_clk 3>;
152				dma-coherent;
153			};
154
155			xor@440000 {
156				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
157				reg = <0x440000 0x1000>,
158				      <0x450000 0x1000>;
159				msi-parent = <&gic_v2m0>;
160				clocks = <&ap_clk 3>;
161				dma-coherent;
162			};
163
164			xor@460000 {
165				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
166				reg = <0x460000 0x1000>,
167				      <0x470000 0x1000>;
168				msi-parent = <&gic_v2m0>;
169				clocks = <&ap_clk 3>;
170				dma-coherent;
171			};
172
173			spi0: spi@510600 {
174				compatible = "marvell,armada-380-spi";
175				reg = <0x510600 0x50>;
176				#address-cells = <1>;
177				#size-cells = <0>;
178				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
179				clocks = <&ap_clk 3>;
180				status = "disabled";
181			};
182
183			i2c0: i2c@511000 {
184				compatible = "marvell,mv78230-i2c";
185				reg = <0x511000 0x20>;
186				#address-cells = <1>;
187				#size-cells = <0>;
188				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
189				timeout-ms = <1000>;
190				clocks = <&ap_clk 3>;
191				status = "disabled";
192			};
193
194			uart0: serial@512000 {
195				compatible = "snps,dw-apb-uart";
196				reg = <0x512000 0x100>;
197				reg-shift = <2>;
198				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
199				reg-io-width = <1>;
200				clocks = <&ap_clk 3>;
201				status = "disabled";
202			};
203
204			uart1: serial@512100 {
205				compatible = "snps,dw-apb-uart";
206				reg = <0x512100 0x100>;
207				reg-shift = <2>;
208				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
209				reg-io-width = <1>;
210				clocks = <&ap_clk 3>;
211				status = "disabled";
212
213			};
214
215			watchdog: watchdog@610000 {
216				compatible = "arm,sbsa-gwdt";
217				reg = <0x610000 0x1000>, <0x600000 0x1000>;
218				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
219			};
220
221			ap_sdhci0: sdhci@6e0000 {
222				compatible = "marvell,armada-ap806-sdhci";
223				reg = <0x6e0000 0x300>;
224				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
225				clock-names = "core";
226				clocks = <&ap_clk 4>;
227				dma-coherent;
228				marvell,xenon-phy-slow-mode;
229				status = "disabled";
230			};
231
232			ap_syscon: system-controller@6f4000 {
233				compatible = "syscon", "simple-mfd";
234				reg = <0x6f4000 0x2000>;
235
236				ap_clk: clock {
237					compatible = "marvell,ap806-clock";
238					#clock-cells = <1>;
239				};
240
241				ap_pinctrl: pinctrl {
242					compatible = "marvell,ap806-pinctrl";
243
244					uart0_pins: uart0-pins {
245						marvell,pins = "mpp11", "mpp19";
246						marvell,function = "uart0";
247					};
248				};
249
250				ap_gpio: gpio@1040 {
251					compatible = "marvell,armada-8k-gpio";
252					offset = <0x1040>;
253					ngpios = <20>;
254					gpio-controller;
255					#gpio-cells = <2>;
256					gpio-ranges = <&ap_pinctrl 0 0 20>;
257				};
258			};
259
260			ap_syscon1: system-controller@6f8000 {
261				compatible = "syscon", "simple-mfd";
262				reg = <0x6f8000 0x1000>;
263				#address-cells = <1>;
264				#size-cells = <1>;
265
266				ap_thermal: thermal-sensor@80 {
267					compatible = "marvell,armada-ap806-thermal";
268					reg = <0x80 0x10>;
269					#thermal-sensor-cells = <1>;
270				};
271			};
272		};
273	};
274
275	/*
276	 * The thermal IP features one internal sensor plus, if applicable, one
277	 * remote channel wired to one sensor per CPU.
278	 *
279	 * The cooling maps are always empty as there are no cooling devices.
280	 */
281	thermal-zones {
282		ap_thermal_ic: ap-thermal-ic {
283			polling-delay-passive = <1000>;
284			polling-delay = <1000>;
285
286			thermal-sensors = <&ap_thermal 0>;
287
288			trips {	};
289			cooling-maps { };
290		};
291
292		ap_thermal_cpu1: ap-thermal-cpu1 {
293			polling-delay-passive = <1000>;
294			polling-delay = <1000>;
295
296			thermal-sensors = <&ap_thermal 1>;
297
298			trips { };
299			cooling-maps { };
300		};
301
302		ap_thermal_cpu2: ap-thermal-cpu2 {
303			polling-delay-passive = <1000>;
304			polling-delay = <1000>;
305
306			thermal-sensors = <&ap_thermal 2>;
307
308			trips { };
309			cooling-maps { };
310		};
311
312		ap_thermal_cpu3: ap-thermal-cpu3 {
313			polling-delay-passive = <1000>;
314			polling-delay = <1000>;
315
316			thermal-sensors = <&ap_thermal 3>;
317
318			trips { };
319			cooling-maps { };
320		};
321
322		ap_thermal_cpu4: ap-thermal-cpu4 {
323			polling-delay-passive = <1000>;
324			polling-delay = <1000>;
325
326			thermal-sensors = <&ap_thermal 4>;
327
328			trips { };
329			cooling-maps { };
330		};
331	};
332};
333