1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada AP806. 45 */ 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49/dts-v1/; 50 51/ { 52 model = "Marvell Armada AP806"; 53 compatible = "marvell,armada-ap806"; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 57 aliases { 58 serial0 = &uart0; 59 serial1 = &uart1; 60 gpio0 = &ap_gpio; 61 }; 62 63 psci { 64 compatible = "arm,psci-0.2"; 65 method = "smc"; 66 }; 67 68 ap806 { 69 #address-cells = <2>; 70 #size-cells = <2>; 71 compatible = "simple-bus"; 72 interrupt-parent = <&gic>; 73 ranges; 74 75 config-space@f0000000 { 76 #address-cells = <1>; 77 #size-cells = <1>; 78 compatible = "simple-bus"; 79 ranges = <0x0 0x0 0xf0000000 0x1000000>; 80 81 gic: interrupt-controller@210000 { 82 compatible = "arm,gic-400"; 83 #interrupt-cells = <3>; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges; 87 interrupt-controller; 88 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 89 reg = <0x210000 0x10000>, 90 <0x220000 0x20000>, 91 <0x240000 0x20000>, 92 <0x260000 0x20000>; 93 94 gic_v2m0: v2m@280000 { 95 compatible = "arm,gic-v2m-frame"; 96 msi-controller; 97 reg = <0x280000 0x1000>; 98 arm,msi-base-spi = <160>; 99 arm,msi-num-spis = <32>; 100 }; 101 gic_v2m1: v2m@290000 { 102 compatible = "arm,gic-v2m-frame"; 103 msi-controller; 104 reg = <0x290000 0x1000>; 105 arm,msi-base-spi = <192>; 106 arm,msi-num-spis = <32>; 107 }; 108 gic_v2m2: v2m@2a0000 { 109 compatible = "arm,gic-v2m-frame"; 110 msi-controller; 111 reg = <0x2a0000 0x1000>; 112 arm,msi-base-spi = <224>; 113 arm,msi-num-spis = <32>; 114 }; 115 gic_v2m3: v2m@2b0000 { 116 compatible = "arm,gic-v2m-frame"; 117 msi-controller; 118 reg = <0x2b0000 0x1000>; 119 arm,msi-base-spi = <256>; 120 arm,msi-num-spis = <32>; 121 }; 122 }; 123 124 timer { 125 compatible = "arm,armv8-timer"; 126 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 130 }; 131 132 pmu { 133 compatible = "arm,cortex-a72-pmu"; 134 interrupt-parent = <&pic>; 135 interrupts = <17>; 136 }; 137 138 odmi: odmi@300000 { 139 compatible = "marvell,odmi-controller"; 140 interrupt-controller; 141 msi-controller; 142 marvell,odmi-frames = <4>; 143 reg = <0x300000 0x4000>, 144 <0x304000 0x4000>, 145 <0x308000 0x4000>, 146 <0x30C000 0x4000>; 147 marvell,spi-base = <128>, <136>, <144>, <152>; 148 }; 149 150 gicp: gicp@3f0040 { 151 compatible = "marvell,ap806-gicp"; 152 reg = <0x3f0040 0x10>; 153 marvell,spi-ranges = <64 64>, <288 64>; 154 msi-controller; 155 }; 156 157 pic: interrupt-controller@3f0100 { 158 compatible = "marvell,armada-8k-pic"; 159 reg = <0x3f0100 0x10>; 160 #interrupt-cells = <1>; 161 interrupt-controller; 162 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 163 }; 164 165 xor@400000 { 166 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 167 reg = <0x400000 0x1000>, 168 <0x410000 0x1000>; 169 msi-parent = <&gic_v2m0>; 170 clocks = <&ap_clk 3>; 171 dma-coherent; 172 }; 173 174 xor@420000 { 175 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 176 reg = <0x420000 0x1000>, 177 <0x430000 0x1000>; 178 msi-parent = <&gic_v2m0>; 179 clocks = <&ap_clk 3>; 180 dma-coherent; 181 }; 182 183 xor@440000 { 184 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 185 reg = <0x440000 0x1000>, 186 <0x450000 0x1000>; 187 msi-parent = <&gic_v2m0>; 188 clocks = <&ap_clk 3>; 189 dma-coherent; 190 }; 191 192 xor@460000 { 193 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 194 reg = <0x460000 0x1000>, 195 <0x470000 0x1000>; 196 msi-parent = <&gic_v2m0>; 197 clocks = <&ap_clk 3>; 198 dma-coherent; 199 }; 200 201 spi0: spi@510600 { 202 compatible = "marvell,armada-380-spi"; 203 reg = <0x510600 0x50>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 cell-index = <0>; 207 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&ap_clk 3>; 209 status = "disabled"; 210 }; 211 212 i2c0: i2c@511000 { 213 compatible = "marvell,mv78230-i2c"; 214 reg = <0x511000 0x20>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 218 timeout-ms = <1000>; 219 clocks = <&ap_clk 3>; 220 status = "disabled"; 221 }; 222 223 uart0: serial@512000 { 224 compatible = "snps,dw-apb-uart"; 225 reg = <0x512000 0x100>; 226 reg-shift = <2>; 227 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 228 reg-io-width = <1>; 229 clocks = <&ap_clk 3>; 230 status = "disabled"; 231 }; 232 233 uart1: serial@512100 { 234 compatible = "snps,dw-apb-uart"; 235 reg = <0x512100 0x100>; 236 reg-shift = <2>; 237 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 238 reg-io-width = <1>; 239 clocks = <&ap_clk 3>; 240 status = "disabled"; 241 242 }; 243 244 ap_sdhci0: sdhci@6e0000 { 245 compatible = "marvell,armada-ap806-sdhci"; 246 reg = <0x6e0000 0x300>; 247 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 248 clock-names = "core"; 249 clocks = <&ap_clk 4>; 250 dma-coherent; 251 marvell,xenon-phy-slow-mode; 252 status = "disabled"; 253 }; 254 255 ap_syscon: system-controller@6f4000 { 256 compatible = "syscon", "simple-mfd"; 257 reg = <0x6f4000 0x2000>; 258 259 ap_clk: clock { 260 compatible = "marvell,ap806-clock"; 261 #clock-cells = <1>; 262 }; 263 264 ap_pinctrl: pinctrl { 265 compatible = "marvell,ap806-pinctrl"; 266 }; 267 268 ap_gpio: gpio@1040 { 269 compatible = "marvell,armada-8k-gpio"; 270 offset = <0x1040>; 271 ngpios = <20>; 272 gpio-controller; 273 #gpio-cells = <2>; 274 gpio-ranges = <&ap_pinctrl 0 0 20>; 275 }; 276 }; 277 }; 278 }; 279}; 280