1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada AP806. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/thermal.h> 10 11/dts-v1/; 12 13/ { 14 model = "Marvell Armada AP806"; 15 compatible = "marvell,armada-ap806"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 serial0 = &uart0; 21 serial1 = &uart1; 22 gpio0 = &ap_gpio; 23 spi0 = &spi0; 24 }; 25 26 psci { 27 compatible = "arm,psci-0.2"; 28 method = "smc"; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 idle_states { 36 entry_method = "arm,pcsi"; 37 38 CPU_SLEEP_0: cpu-sleep-0 { 39 compatible = "arm,idle-state"; 40 local-timer-stop; 41 arm,psci-suspend-param = <0x0010000>; 42 entry-latency-us = <80>; 43 exit-latency-us = <160>; 44 min-residency-us = <320>; 45 }; 46 47 CLUSTER_SLEEP_0: cluster-sleep-0 { 48 compatible = "arm,idle-state"; 49 local-timer-stop; 50 arm,psci-suspend-param = <0x1010000>; 51 entry-latency-us = <500>; 52 exit-latency-us = <1000>; 53 min-residency-us = <2500>; 54 }; 55 }; 56 }; 57 58 ap806 { 59 #address-cells = <2>; 60 #size-cells = <2>; 61 compatible = "simple-bus"; 62 interrupt-parent = <&gic>; 63 ranges; 64 65 config-space@f0000000 { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 compatible = "simple-bus"; 69 ranges = <0x0 0x0 0xf0000000 0x1000000>; 70 71 gic: interrupt-controller@210000 { 72 compatible = "arm,gic-400"; 73 #interrupt-cells = <3>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 interrupt-controller; 78 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 79 reg = <0x210000 0x10000>, 80 <0x220000 0x20000>, 81 <0x240000 0x20000>, 82 <0x260000 0x20000>; 83 84 gic_v2m0: v2m@280000 { 85 compatible = "arm,gic-v2m-frame"; 86 msi-controller; 87 reg = <0x280000 0x1000>; 88 arm,msi-base-spi = <160>; 89 arm,msi-num-spis = <32>; 90 }; 91 gic_v2m1: v2m@290000 { 92 compatible = "arm,gic-v2m-frame"; 93 msi-controller; 94 reg = <0x290000 0x1000>; 95 arm,msi-base-spi = <192>; 96 arm,msi-num-spis = <32>; 97 }; 98 gic_v2m2: v2m@2a0000 { 99 compatible = "arm,gic-v2m-frame"; 100 msi-controller; 101 reg = <0x2a0000 0x1000>; 102 arm,msi-base-spi = <224>; 103 arm,msi-num-spis = <32>; 104 }; 105 gic_v2m3: v2m@2b0000 { 106 compatible = "arm,gic-v2m-frame"; 107 msi-controller; 108 reg = <0x2b0000 0x1000>; 109 arm,msi-base-spi = <256>; 110 arm,msi-num-spis = <32>; 111 }; 112 }; 113 114 timer { 115 compatible = "arm,armv8-timer"; 116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 118 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 120 }; 121 122 pmu { 123 compatible = "arm,cortex-a72-pmu"; 124 interrupt-parent = <&pic>; 125 interrupts = <17>; 126 }; 127 128 odmi: odmi@300000 { 129 compatible = "marvell,odmi-controller"; 130 interrupt-controller; 131 msi-controller; 132 marvell,odmi-frames = <4>; 133 reg = <0x300000 0x4000>, 134 <0x304000 0x4000>, 135 <0x308000 0x4000>, 136 <0x30C000 0x4000>; 137 marvell,spi-base = <128>, <136>, <144>, <152>; 138 }; 139 140 gicp: gicp@3f0040 { 141 compatible = "marvell,ap806-gicp"; 142 reg = <0x3f0040 0x10>; 143 marvell,spi-ranges = <64 64>, <288 64>; 144 msi-controller; 145 }; 146 147 pic: interrupt-controller@3f0100 { 148 compatible = "marvell,armada-8k-pic"; 149 reg = <0x3f0100 0x10>; 150 #interrupt-cells = <1>; 151 interrupt-controller; 152 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 153 }; 154 155 sei: interrupt-controller@3f0200 { 156 compatible = "marvell,ap806-sei"; 157 reg = <0x3f0200 0x40>; 158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 159 #interrupt-cells = <1>; 160 interrupt-controller; 161 msi-controller; 162 }; 163 164 xor@400000 { 165 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 166 reg = <0x400000 0x1000>, 167 <0x410000 0x1000>; 168 msi-parent = <&gic_v2m0>; 169 clocks = <&ap_clk 3>; 170 dma-coherent; 171 }; 172 173 xor@420000 { 174 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 175 reg = <0x420000 0x1000>, 176 <0x430000 0x1000>; 177 msi-parent = <&gic_v2m0>; 178 clocks = <&ap_clk 3>; 179 dma-coherent; 180 }; 181 182 xor@440000 { 183 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 184 reg = <0x440000 0x1000>, 185 <0x450000 0x1000>; 186 msi-parent = <&gic_v2m0>; 187 clocks = <&ap_clk 3>; 188 dma-coherent; 189 }; 190 191 xor@460000 { 192 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 193 reg = <0x460000 0x1000>, 194 <0x470000 0x1000>; 195 msi-parent = <&gic_v2m0>; 196 clocks = <&ap_clk 3>; 197 dma-coherent; 198 }; 199 200 spi0: spi@510600 { 201 compatible = "marvell,armada-380-spi"; 202 reg = <0x510600 0x50>; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&ap_clk 3>; 207 status = "disabled"; 208 }; 209 210 i2c0: i2c@511000 { 211 compatible = "marvell,mv78230-i2c"; 212 reg = <0x511000 0x20>; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 216 timeout-ms = <1000>; 217 clocks = <&ap_clk 3>; 218 status = "disabled"; 219 }; 220 221 uart0: serial@512000 { 222 compatible = "snps,dw-apb-uart"; 223 reg = <0x512000 0x100>; 224 reg-shift = <2>; 225 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 226 reg-io-width = <1>; 227 clocks = <&ap_clk 3>; 228 status = "disabled"; 229 }; 230 231 uart1: serial@512100 { 232 compatible = "snps,dw-apb-uart"; 233 reg = <0x512100 0x100>; 234 reg-shift = <2>; 235 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 236 reg-io-width = <1>; 237 clocks = <&ap_clk 3>; 238 status = "disabled"; 239 240 }; 241 242 watchdog: watchdog@610000 { 243 compatible = "arm,sbsa-gwdt"; 244 reg = <0x610000 0x1000>, <0x600000 0x1000>; 245 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 246 }; 247 248 ap_sdhci0: sdhci@6e0000 { 249 compatible = "marvell,armada-ap806-sdhci"; 250 reg = <0x6e0000 0x300>; 251 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 252 clock-names = "core"; 253 clocks = <&ap_clk 4>; 254 dma-coherent; 255 marvell,xenon-phy-slow-mode; 256 status = "disabled"; 257 }; 258 259 ap_syscon: system-controller@6f4000 { 260 compatible = "syscon", "simple-mfd"; 261 reg = <0x6f4000 0x2000>; 262 263 ap_clk: clock { 264 compatible = "marvell,ap806-clock"; 265 #clock-cells = <1>; 266 }; 267 268 ap_pinctrl: pinctrl { 269 compatible = "marvell,ap806-pinctrl"; 270 271 uart0_pins: uart0-pins { 272 marvell,pins = "mpp11", "mpp19"; 273 marvell,function = "uart0"; 274 }; 275 }; 276 277 ap_gpio: gpio@1040 { 278 compatible = "marvell,armada-8k-gpio"; 279 offset = <0x1040>; 280 ngpios = <20>; 281 gpio-controller; 282 #gpio-cells = <2>; 283 gpio-ranges = <&ap_pinctrl 0 0 20>; 284 }; 285 }; 286 287 ap_syscon1: system-controller@6f8000 { 288 compatible = "syscon", "simple-mfd"; 289 reg = <0x6f8000 0x1000>; 290 #address-cells = <1>; 291 #size-cells = <1>; 292 293 ap_thermal: thermal-sensor@80 { 294 compatible = "marvell,armada-ap806-thermal"; 295 reg = <0x80 0x10>; 296 #thermal-sensor-cells = <1>; 297 }; 298 }; 299 }; 300 }; 301 302 /* 303 * The thermal IP features one internal sensor plus, if applicable, one 304 * remote channel wired to one sensor per CPU. 305 * 306 * The cooling maps are always empty as there are no cooling devices. 307 */ 308 thermal-zones { 309 ap_thermal_ic: ap-thermal-ic { 310 polling-delay-passive = <1000>; 311 polling-delay = <1000>; 312 313 thermal-sensors = <&ap_thermal 0>; 314 315 trips { }; 316 cooling-maps { }; 317 }; 318 319 ap_thermal_cpu1: ap-thermal-cpu1 { 320 polling-delay-passive = <1000>; 321 polling-delay = <1000>; 322 323 thermal-sensors = <&ap_thermal 1>; 324 325 trips { }; 326 cooling-maps { }; 327 }; 328 329 ap_thermal_cpu2: ap-thermal-cpu2 { 330 polling-delay-passive = <1000>; 331 polling-delay = <1000>; 332 333 thermal-sensors = <&ap_thermal 2>; 334 335 trips { }; 336 cooling-maps { }; 337 }; 338 339 ap_thermal_cpu3: ap-thermal-cpu3 { 340 polling-delay-passive = <1000>; 341 polling-delay = <1000>; 342 343 thermal-sensors = <&ap_thermal 3>; 344 345 trips { }; 346 cooling-maps { }; 347 }; 348 349 ap_thermal_cpu4: ap-thermal-cpu4 { 350 polling-delay-passive = <1000>; 351 polling-delay = <1000>; 352 353 thermal-sensors = <&ap_thermal 4>; 354 355 trips { }; 356 cooling-maps { }; 357 }; 358 }; 359}; 360