1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada 8040 Development board platform
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include "armada-8040.dtsi"
10
11/ {
12	model = "Marvell Armada 8040 DB board";
13	compatible = "marvell,armada8040-db", "marvell,armada8040",
14		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	memory@0 {
21		device_type = "memory";
22		reg = <0x0 0x0 0x0 0x80000000>;
23	};
24
25	aliases {
26		ethernet0 = &cp0_eth0;
27		ethernet1 = &cp0_eth2;
28		ethernet2 = &cp1_eth0;
29		ethernet3 = &cp1_eth1;
30		i2c1 = &cp0_i2c0;
31		i2c2 = &cp1_i2c0;
32	};
33
34	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
35		compatible = "regulator-fixed";
36		regulator-name = "cp0-usb3h0-vbus";
37		regulator-min-microvolt = <5000000>;
38		regulator-max-microvolt = <5000000>;
39		enable-active-high;
40		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
41	};
42
43	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
44		compatible = "regulator-fixed";
45		regulator-name = "cp0-usb3h1-vbus";
46		regulator-min-microvolt = <5000000>;
47		regulator-max-microvolt = <5000000>;
48		enable-active-high;
49		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
50	};
51
52	cp0_usb3_0_phy: cp0-usb3-0-phy {
53		compatible = "usb-nop-xceiv";
54		vcc-supply = <&cp0_reg_usb3_0_vbus>;
55	};
56
57	cp0_usb3_1_phy: cp0-usb3-1-phy {
58		compatible = "usb-nop-xceiv";
59		vcc-supply = <&cp0_reg_usb3_1_vbus>;
60	};
61
62	cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
63		compatible = "regulator-fixed";
64		regulator-name = "cp1-usb3h0-vbus";
65		regulator-min-microvolt = <5000000>;
66		regulator-max-microvolt = <5000000>;
67		enable-active-high;
68		gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
69	};
70
71	cp1_usb3_0_phy: cp1-usb3-0-phy {
72		compatible = "usb-nop-xceiv";
73		vcc-supply = <&cp1_reg_usb3_0_vbus>;
74	};
75};
76
77&spi0 {
78	status = "okay";
79
80	spi-flash@0 {
81		compatible = "jedec,spi-nor";
82		reg = <0>;
83		spi-max-frequency = <10000000>;
84
85		partitions {
86			compatible = "fixed-partitions";
87			#address-cells = <1>;
88			#size-cells = <1>;
89
90			partition@0 {
91				label = "U-Boot";
92				reg = <0 0x200000>;
93			};
94			partition@400000 {
95				label = "Filesystem";
96				reg = <0x200000 0xce0000>;
97			};
98		};
99	};
100};
101
102/* Accessible over the mini-USB CON9 connector on the main board */
103&uart0 {
104	status = "okay";
105	pinctrl-0 = <&uart0_pins>;
106	pinctrl-names = "default";
107};
108
109/* CON6 on CP0 expansion */
110&cp0_pcie0 {
111	status = "okay";
112};
113
114/* CON5 on CP0 expansion */
115&cp0_pcie2 {
116	status = "okay";
117};
118
119&cp0_i2c0 {
120	status = "okay";
121	clock-frequency = <100000>;
122
123	/* U31 */
124	expander0: pca9555@21 {
125		compatible = "nxp,pca9555";
126		pinctrl-names = "default";
127		gpio-controller;
128		#gpio-cells = <2>;
129		reg = <0x21>;
130	};
131
132	/* U25 */
133	expander1: pca9555@25 {
134		compatible = "nxp,pca9555";
135		pinctrl-names = "default";
136		gpio-controller;
137		#gpio-cells = <2>;
138		reg = <0x25>;
139	};
140
141};
142
143/* CON4 on CP0 expansion */
144&cp0_sata0 {
145	status = "okay";
146};
147
148/* CON9 on CP0 expansion */
149&cp0_usb3_0 {
150	usb-phy = <&cp0_usb3_0_phy>;
151	status = "okay";
152};
153
154/* CON10 on CP0 expansion */
155&cp0_usb3_1 {
156	usb-phy = <&cp0_usb3_1_phy>;
157	status = "okay";
158};
159
160&cp0_mdio {
161	status = "okay";
162
163	phy1: ethernet-phy@1 {
164		reg = <1>;
165	};
166};
167
168&cp0_ethernet {
169	status = "okay";
170};
171
172&cp0_eth0 {
173	status = "okay";
174	phy-mode = "10gbase-kr";
175
176	fixed-link {
177		speed = <10000>;
178		full-duplex;
179	};
180};
181
182&cp0_eth2 {
183	status = "okay";
184	phy = <&phy1>;
185	phy-mode = "rgmii-id";
186};
187
188/* CON6 on CP1 expansion */
189&cp1_pcie0 {
190	status = "okay";
191};
192
193/* CON7 on CP1 expansion */
194&cp1_pcie1 {
195	status = "okay";
196};
197
198/* CON5 on CP1 expansion */
199&cp1_pcie2 {
200	status = "okay";
201};
202
203&cp1_i2c0 {
204	status = "okay";
205	clock-frequency = <100000>;
206};
207
208&cp1_spi1 {
209	status = "okay";
210
211	spi-flash@0 {
212		compatible = "jedec,spi-nor";
213		reg = <0x0>;
214		spi-max-frequency = <20000000>;
215
216		partitions {
217			compatible = "fixed-partitions";
218			#address-cells = <1>;
219			#size-cells = <1>;
220
221			partition@0 {
222				label = "Boot";
223				reg = <0x0 0x200000>;
224			};
225			partition@200000 {
226				label = "Filesystem";
227				reg = <0x200000 0xd00000>;
228			};
229			partition@f00000 {
230				label = "Boot_2nd";
231				reg = <0xf00000 0x100000>;
232			};
233		};
234	};
235};
236
237/*
238 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
239 * MDIO signal of CP1.
240 */
241&cp1_nand_controller {
242	pinctrl-0 = <&nand_pins>, <&nand_rb>;
243	pinctrl-names = "default";
244
245	nand@0 {
246		reg = <0>;
247		nand-rb = <0>;
248		nand-on-flash-bbt;
249		nand-ecc-strength = <4>;
250		nand-ecc-step-size = <512>;
251
252		partitions {
253			compatible = "fixed-partitions";
254			#address-cells = <1>;
255			#size-cells = <1>;
256
257			partition@0 {
258				label = "U-Boot";
259				reg = <0 0x200000>;
260			};
261			partition@200000 {
262				label = "Linux";
263				reg = <0x200000 0xe00000>;
264			};
265			partition@1000000 {
266				label = "Filesystem";
267				reg = <0x1000000 0x3f000000>;
268			};
269		};
270	};
271};
272
273/* CON4 on CP1 expansion */
274&cp1_sata0 {
275	status = "okay";
276};
277
278/* CON9 on CP1 expansion */
279&cp1_usb3_0 {
280	usb-phy = <&cp1_usb3_0_phy>;
281	status = "okay";
282};
283
284/* CON10 on CP1 expansion */
285&cp1_usb3_1 {
286	status = "okay";
287};
288
289&cp1_mdio {
290	status = "okay";
291
292	phy0: ethernet-phy@0 {
293		reg = <0>;
294	};
295};
296
297&cp1_ethernet {
298	status = "okay";
299};
300
301&cp1_eth0 {
302	status = "okay";
303	phy-mode = "10gbase-kr";
304
305	fixed-link {
306		speed = <10000>;
307		full-duplex;
308	};
309};
310
311&cp1_eth1 {
312	status = "okay";
313	phy = <&phy0>;
314	phy-mode = "rgmii-id";
315};
316
317&ap_sdhci0 {
318	status = "okay";
319	bus-width = <4>;
320	non-removable;
321};
322
323&cp0_sdhci0 {
324	status = "okay";
325	bus-width = <8>;
326	non-removable;
327};
328