1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada 8040 Development board platform
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include "armada-8040.dtsi"
10
11/ {
12	model = "Marvell Armada 8040 DB board";
13	compatible = "marvell,armada8040-db", "marvell,armada8040",
14		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	memory@0 {
21		device_type = "memory";
22		reg = <0x0 0x0 0x0 0x80000000>;
23	};
24
25	aliases {
26		ethernet0 = &cp0_eth0;
27		ethernet1 = &cp0_eth2;
28		ethernet2 = &cp1_eth0;
29		ethernet3 = &cp1_eth1;
30	};
31
32	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
33		compatible = "regulator-fixed";
34		regulator-name = "cp0-usb3h0-vbus";
35		regulator-min-microvolt = <5000000>;
36		regulator-max-microvolt = <5000000>;
37		enable-active-high;
38		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
39	};
40
41	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
42		compatible = "regulator-fixed";
43		regulator-name = "cp0-usb3h1-vbus";
44		regulator-min-microvolt = <5000000>;
45		regulator-max-microvolt = <5000000>;
46		enable-active-high;
47		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
48	};
49
50	cp0_usb3_0_phy: cp0-usb3-0-phy {
51		compatible = "usb-nop-xceiv";
52		vcc-supply = <&cp0_reg_usb3_0_vbus>;
53	};
54
55	cp0_usb3_1_phy: cp0-usb3-1-phy {
56		compatible = "usb-nop-xceiv";
57		vcc-supply = <&cp0_reg_usb3_1_vbus>;
58	};
59
60	cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
61		compatible = "regulator-fixed";
62		regulator-name = "cp1-usb3h0-vbus";
63		regulator-min-microvolt = <5000000>;
64		regulator-max-microvolt = <5000000>;
65		enable-active-high;
66		gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
67	};
68
69	cp1_usb3_0_phy: cp1-usb3-0-phy {
70		compatible = "usb-nop-xceiv";
71		vcc-supply = <&cp1_reg_usb3_0_vbus>;
72	};
73};
74
75&i2c0 {
76	status = "okay";
77	clock-frequency = <100000>;
78};
79
80&spi0 {
81	status = "okay";
82
83	spi-flash@0 {
84		compatible = "jedec,spi-nor";
85		reg = <0>;
86		spi-max-frequency = <10000000>;
87
88		partitions {
89			compatible = "fixed-partitions";
90			#address-cells = <1>;
91			#size-cells = <1>;
92
93			partition@0 {
94				label = "U-Boot";
95				reg = <0 0x200000>;
96			};
97			partition@400000 {
98				label = "Filesystem";
99				reg = <0x200000 0xce0000>;
100			};
101		};
102	};
103};
104
105/* Accessible over the mini-USB CON9 connector on the main board */
106&uart0 {
107	status = "okay";
108	pinctrl-0 = <&uart0_pins>;
109	pinctrl-names = "default";
110};
111
112/* CON6 on CP0 expansion */
113&cp0_pcie0 {
114	status = "okay";
115};
116
117/* CON5 on CP0 expansion */
118&cp0_pcie2 {
119	status = "okay";
120};
121
122&cp0_i2c0 {
123	status = "okay";
124	clock-frequency = <100000>;
125
126	/* U31 */
127	expander0: pca9555@21 {
128		compatible = "nxp,pca9555";
129		pinctrl-names = "default";
130		gpio-controller;
131		#gpio-cells = <2>;
132		reg = <0x21>;
133	};
134
135	/* U25 */
136	expander1: pca9555@25 {
137		compatible = "nxp,pca9555";
138		pinctrl-names = "default";
139		gpio-controller;
140		#gpio-cells = <2>;
141		reg = <0x25>;
142	};
143
144};
145
146/* CON4 on CP0 expansion */
147&cp0_sata0 {
148	status = "okay";
149};
150
151/* CON9 on CP0 expansion */
152&cp0_usb3_0 {
153	usb-phy = <&cp0_usb3_0_phy>;
154	status = "okay";
155};
156
157/* CON10 on CP0 expansion */
158&cp0_usb3_1 {
159	usb-phy = <&cp0_usb3_1_phy>;
160	status = "okay";
161};
162
163&cp0_mdio {
164	status = "okay";
165
166	phy1: ethernet-phy@1 {
167		reg = <1>;
168	};
169};
170
171&cp0_ethernet {
172	status = "okay";
173};
174
175&cp0_eth0 {
176	status = "okay";
177	phy-mode = "10gbase-kr";
178
179	fixed-link {
180		speed = <10000>;
181		full-duplex;
182	};
183};
184
185&cp0_eth2 {
186	status = "okay";
187	phy = <&phy1>;
188	phy-mode = "rgmii-id";
189};
190
191/* CON6 on CP1 expansion */
192&cp1_pcie0 {
193	status = "okay";
194};
195
196/* CON7 on CP1 expansion */
197&cp1_pcie1 {
198	status = "okay";
199};
200
201/* CON5 on CP1 expansion */
202&cp1_pcie2 {
203	status = "okay";
204};
205
206&cp1_i2c0 {
207	status = "okay";
208	clock-frequency = <100000>;
209};
210
211&cp1_spi1 {
212	status = "okay";
213
214	spi-flash@0 {
215		compatible = "jedec,spi-nor";
216		reg = <0x0>;
217		spi-max-frequency = <20000000>;
218
219		partitions {
220			compatible = "fixed-partitions";
221			#address-cells = <1>;
222			#size-cells = <1>;
223
224			partition@0 {
225				label = "Boot";
226				reg = <0x0 0x200000>;
227			};
228			partition@200000 {
229				label = "Filesystem";
230				reg = <0x200000 0xd00000>;
231			};
232			partition@f00000 {
233				label = "Boot_2nd";
234				reg = <0xf00000 0x100000>;
235			};
236		};
237	};
238};
239
240/*
241 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
242 * MDIO signal of CP1.
243 */
244&cp1_nand_controller {
245	pinctrl-0 = <&nand_pins>, <&nand_rb>;
246	pinctrl-names = "default";
247
248	nand@0 {
249		reg = <0>;
250		nand-rb = <0>;
251		nand-on-flash-bbt;
252		nand-ecc-strength = <4>;
253		nand-ecc-step-size = <512>;
254
255		partitions {
256			compatible = "fixed-partitions";
257			#address-cells = <1>;
258			#size-cells = <1>;
259
260			partition@0 {
261				label = "U-Boot";
262				reg = <0 0x200000>;
263			};
264			partition@200000 {
265				label = "Linux";
266				reg = <0x200000 0xe00000>;
267			};
268			partition@1000000 {
269				label = "Filesystem";
270				reg = <0x1000000 0x3f000000>;
271			};
272		};
273	};
274};
275
276/* CON4 on CP1 expansion */
277&cp1_sata0 {
278	status = "okay";
279};
280
281/* CON9 on CP1 expansion */
282&cp1_usb3_0 {
283	usb-phy = <&cp1_usb3_0_phy>;
284	status = "okay";
285};
286
287/* CON10 on CP1 expansion */
288&cp1_usb3_1 {
289	status = "okay";
290};
291
292&cp1_mdio {
293	status = "okay";
294
295	phy0: ethernet-phy@0 {
296		reg = <0>;
297	};
298};
299
300&cp1_ethernet {
301	status = "okay";
302};
303
304&cp1_eth0 {
305	status = "okay";
306	phy-mode = "10gbase-kr";
307
308	fixed-link {
309		speed = <10000>;
310		full-duplex;
311	};
312};
313
314&cp1_eth1 {
315	status = "okay";
316	phy = <&phy0>;
317	phy-mode = "rgmii-id";
318};
319
320&ap_sdhci0 {
321	status = "okay";
322	bus-width = <4>;
323	non-removable;
324};
325
326&cp0_sdhci0 {
327	status = "okay";
328	bus-width = <8>;
329	non-removable;
330};
331