1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada 7040 Development board platform
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include "armada-7040.dtsi"
10
11/ {
12	model = "Marvell Armada 7040 DB board";
13	compatible = "marvell,armada7040-db", "marvell,armada7040",
14		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	memory@0 {
21		device_type = "memory";
22		reg = <0x0 0x0 0x0 0x80000000>;
23	};
24
25	aliases {
26		ethernet0 = &cp0_eth0;
27		ethernet1 = &cp0_eth1;
28		ethernet2 = &cp0_eth2;
29	};
30
31	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
32		compatible = "regulator-fixed";
33		regulator-name = "usb3h0-vbus";
34		regulator-min-microvolt = <5000000>;
35		regulator-max-microvolt = <5000000>;
36		enable-active-high;
37		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
38	};
39
40	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
41		compatible = "regulator-fixed";
42		regulator-name = "usb3h1-vbus";
43		regulator-min-microvolt = <5000000>;
44		regulator-max-microvolt = <5000000>;
45		enable-active-high;
46		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
47	};
48
49	cp0_usb3_0_phy: cp0-usb3-0-phy {
50		compatible = "usb-nop-xceiv";
51		vcc-supply = <&cp0_reg_usb3_0_vbus>;
52	};
53
54	cp0_usb3_1_phy: cp0-usb3-1-phy {
55		compatible = "usb-nop-xceiv";
56		vcc-supply = <&cp0_reg_usb3_1_vbus>;
57	};
58};
59
60&i2c0 {
61	status = "okay";
62	clock-frequency = <100000>;
63};
64
65&spi0 {
66	status = "okay";
67
68	spi-flash@0 {
69		compatible = "jedec,spi-nor";
70		reg = <0>;
71		spi-max-frequency = <10000000>;
72
73		partitions {
74			compatible = "fixed-partitions";
75			#address-cells = <1>;
76			#size-cells = <1>;
77
78			partition@0 {
79				label = "U-Boot";
80				reg = <0 0x200000>;
81			};
82			partition@400000 {
83				label = "Filesystem";
84				reg = <0x200000 0xce0000>;
85			};
86		};
87	};
88};
89
90&uart0 {
91	status = "okay";
92	pinctrl-0 = <&uart0_pins>;
93	pinctrl-names = "default";
94};
95
96
97&cp0_pcie2 {
98	status = "okay";
99};
100
101&cp0_i2c0 {
102	status = "okay";
103	clock-frequency = <100000>;
104
105	expander0: pca9555@21 {
106		compatible = "nxp,pca9555";
107		pinctrl-names = "default";
108		gpio-controller;
109		#gpio-cells = <2>;
110		reg = <0x21>;
111		/*
112		 * IO0_0: USB3_PWR_EN0	IO1_0: USB_3_1_Dev_Detect
113		 * IO0_1: USB3_PWR_EN1	IO1_1: USB2_1_current_limit
114		 * IO0_2: DDR3_4_Detect	IO1_2: Hcon_IO_RstN
115		 * IO0_3: USB2_DEVICE_DETECT
116		 * IO0_4: GPIO_0	IO1_4: SD_Status
117		 * IO0_5: GPIO_1	IO1_5: LDO_5V_Enable
118		 * IO0_6: IHB_5V_Enable	IO1_6: PWR_EN_eMMC
119		 * IO0_7:		IO1_7: SDIO_Vcntrl
120		 */
121	};
122};
123
124&cp0_nand_controller {
125	/*
126	 * SPI on CPM and NAND have common pins on this board. We can
127	 * use only one at a time. To enable the NAND (which will
128	 * disable the SPI), the "status = "okay";" line have to be
129	 * added here.
130	 */
131	pinctrl-0 = <&nand_pins>, <&nand_rb>;
132	pinctrl-names = "default";
133
134	nand@0 {
135		reg = <0>;
136		label = "pxa3xx_nand-0";
137		nand-rb = <0>;
138		nand-on-flash-bbt;
139		nand-ecc-strength = <4>;
140		nand-ecc-step-size = <512>;
141
142		partitions {
143			compatible = "fixed-partitions";
144			#address-cells = <1>;
145			#size-cells = <1>;
146
147			partition@0 {
148				label = "U-Boot";
149				reg = <0 0x200000>;
150			};
151
152			partition@200000 {
153				label = "Linux";
154				reg = <0x200000 0xe00000>;
155			};
156
157			partition@1000000 {
158				label = "Filesystem";
159				reg = <0x1000000 0x3f000000>;
160			};
161
162		};
163	};
164};
165
166&cp0_spi1 {
167	status = "okay";
168
169	spi-flash@0 {
170		compatible = "jedec,spi-nor";
171		reg = <0x0>;
172		spi-max-frequency = <20000000>;
173
174		partitions {
175			compatible = "fixed-partitions";
176			#address-cells = <1>;
177			#size-cells = <1>;
178
179			partition@0 {
180				label = "U-Boot";
181				reg = <0x0 0x200000>;
182			};
183
184			partition@400000 {
185				label = "Filesystem";
186				reg = <0x200000 0xe00000>;
187			};
188		};
189	};
190};
191
192&cp0_sata0 {
193	status = "okay";
194};
195
196&cp0_usb3_0 {
197	usb-phy = <&cp0_usb3_0_phy>;
198	status = "okay";
199};
200
201&cp0_usb3_1 {
202	usb-phy = <&cp0_usb3_1_phy>;
203	status = "okay";
204};
205
206&ap_sdhci0 {
207	status = "okay";
208	bus-width = <4>;
209	no-1-8-v;
210	non-removable;
211};
212
213&cp0_sdhci0 {
214	status = "okay";
215	bus-width = <4>;
216	no-1-8-v;
217	cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
218};
219
220&cp0_mdio {
221	status = "okay";
222
223	phy0: ethernet-phy@0 {
224		reg = <0>;
225	};
226	phy1: ethernet-phy@1 {
227		reg = <1>;
228	};
229};
230
231&cp0_ethernet {
232	status = "okay";
233};
234
235&cp0_eth0 {
236	status = "okay";
237	/* Network PHY */
238	phy-mode = "10gbase-kr";
239	/* Generic PHY, providing serdes lanes */
240	phys = <&cp0_comphy2 0>;
241
242	fixed-link {
243		speed = <10000>;
244		full-duplex;
245	};
246};
247
248&cp0_eth1 {
249	status = "okay";
250	/* Network PHY */
251	phy = <&phy0>;
252	phy-mode = "sgmii";
253	/* Generic PHY, providing serdes lanes */
254	phys = <&cp0_comphy0 1>;
255};
256
257&cp0_eth2 {
258	status = "okay";
259	phy = <&phy1>;
260	phy-mode = "rgmii-id";
261};
262