1/*
2 * Copyright (C) 2016 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This library is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This library is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/*
44 * Device Tree file for Marvell Armada 7040 Development board platform
45 */
46
47#include <dt-bindings/gpio/gpio.h>
48#include "armada-7040.dtsi"
49
50/ {
51	model = "Marvell Armada 7040 DB board";
52	compatible = "marvell,armada7040-db", "marvell,armada7040",
53		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
54
55	chosen {
56		stdout-path = "serial0:115200n8";
57	};
58
59	memory@0 {
60		device_type = "memory";
61		reg = <0x0 0x0 0x0 0x80000000>;
62	};
63
64	aliases {
65		ethernet0 = &cp0_eth0;
66		ethernet1 = &cp0_eth1;
67		ethernet2 = &cp0_eth2;
68	};
69
70	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
71		compatible = "regulator-fixed";
72		regulator-name = "usb3h0-vbus";
73		regulator-min-microvolt = <5000000>;
74		regulator-max-microvolt = <5000000>;
75		enable-active-high;
76		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
77	};
78
79	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
80		compatible = "regulator-fixed";
81		regulator-name = "usb3h1-vbus";
82		regulator-min-microvolt = <5000000>;
83		regulator-max-microvolt = <5000000>;
84		enable-active-high;
85		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
86	};
87
88	cp0_usb3_0_phy: cp0-usb3-0-phy {
89		compatible = "usb-nop-xceiv";
90		vcc-supply = <&cp0_reg_usb3_0_vbus>;
91	};
92
93	cp0_usb3_1_phy: cp0-usb3-1-phy {
94		compatible = "usb-nop-xceiv";
95		vcc-supply = <&cp0_reg_usb3_1_vbus>;
96	};
97};
98
99&i2c0 {
100	status = "okay";
101	clock-frequency = <100000>;
102};
103
104&spi0 {
105	status = "okay";
106
107	spi-flash@0 {
108		#address-cells = <1>;
109		#size-cells = <1>;
110		compatible = "jedec,spi-nor";
111		reg = <0>;
112		spi-max-frequency = <10000000>;
113
114		partitions {
115			compatible = "fixed-partitions";
116			#address-cells = <1>;
117			#size-cells = <1>;
118
119			partition@0 {
120				label = "U-Boot";
121				reg = <0 0x200000>;
122			};
123			partition@400000 {
124				label = "Filesystem";
125				reg = <0x200000 0xce0000>;
126			};
127		};
128	};
129};
130
131&uart0 {
132	status = "okay";
133	pinctrl-0 = <&uart0_pins>;
134	pinctrl-names = "default";
135};
136
137
138&cp0_pcie2 {
139	status = "okay";
140};
141
142&cp0_i2c0 {
143	status = "okay";
144	clock-frequency = <100000>;
145
146	expander0: pca9555@21 {
147		compatible = "nxp,pca9555";
148		pinctrl-names = "default";
149		gpio-controller;
150		#gpio-cells = <2>;
151		reg = <0x21>;
152		/*
153		 * IO0_0: USB3_PWR_EN0	IO1_0: USB_3_1_Dev_Detect
154		 * IO0_1: USB3_PWR_EN1	IO1_1: USB2_1_current_limit
155		 * IO0_2: DDR3_4_Detect	IO1_2: Hcon_IO_RstN
156		 * IO0_3: USB2_DEVICE_DETECT
157		 * IO0_4: GPIO_0	IO1_4: SD_Status
158		 * IO0_5: GPIO_1	IO1_5: LDO_5V_Enable
159		 * IO0_6: IHB_5V_Enable	IO1_6: PWR_EN_eMMC
160		 * IO0_7:		IO1_7: SDIO_Vcntrl
161		 */
162	};
163};
164
165&cp0_nand {
166	/*
167	 * SPI on CPM and NAND have common pins on this board. We can
168	 * use only one at a time. To enable the NAND (whihch will
169	 * disable the SPI), the "status = "okay";" line have to be
170	 * added here.
171	 */
172	num-cs = <1>;
173	pinctrl-0 = <&nand_pins>, <&nand_rb>;
174	pinctrl-names = "default";
175	nand-ecc-strength = <4>;
176	nand-ecc-step-size = <512>;
177	marvell,nand-enable-arbiter;
178	nand-on-flash-bbt;
179
180	partition@0 {
181		label = "U-Boot";
182		reg = <0 0x200000>;
183	};
184	partition@200000 {
185		label = "Linux";
186		reg = <0x200000 0xe00000>;
187	};
188	partition@1000000 {
189		label = "Filesystem";
190		reg = <0x1000000 0x3f000000>;
191	};
192};
193
194
195&cp0_spi1 {
196	status = "okay";
197
198	spi-flash@0 {
199		#address-cells = <0x1>;
200		#size-cells = <0x1>;
201		compatible = "jedec,spi-nor";
202		reg = <0x0>;
203		spi-max-frequency = <20000000>;
204
205		partitions {
206			compatible = "fixed-partitions";
207			#address-cells = <1>;
208			#size-cells = <1>;
209
210			partition@0 {
211				label = "U-Boot";
212				reg = <0x0 0x200000>;
213			};
214
215			partition@400000 {
216				label = "Filesystem";
217				reg = <0x200000 0xe00000>;
218			};
219		};
220	};
221};
222
223&cp0_sata0 {
224	status = "okay";
225};
226
227&cp0_usb3_0 {
228	usb-phy = <&cp0_usb3_0_phy>;
229	status = "okay";
230};
231
232&cp0_usb3_1 {
233	usb-phy = <&cp0_usb3_1_phy>;
234	status = "okay";
235};
236
237&ap_sdhci0 {
238	status = "okay";
239	bus-width = <4>;
240	no-1-8-v;
241	non-removable;
242};
243
244&cp0_sdhci0 {
245	status = "okay";
246	bus-width = <4>;
247	no-1-8-v;
248	cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
249};
250
251&cp0_mdio {
252	status = "okay";
253
254	phy0: ethernet-phy@0 {
255		reg = <0>;
256	};
257	phy1: ethernet-phy@1 {
258		reg = <1>;
259	};
260};
261
262&cp0_ethernet {
263	status = "okay";
264};
265
266&cp0_eth0 {
267	status = "okay";
268	/* Network PHY */
269	phy-mode = "10gbase-kr";
270	/* Generic PHY, providing serdes lanes */
271	phys = <&cp0_comphy2 0>;
272};
273
274&cp0_eth1 {
275	status = "okay";
276	/* Network PHY */
277	phy = <&phy0>;
278	phy-mode = "sgmii";
279	/* Generic PHY, providing serdes lanes */
280	phys = <&cp0_comphy0 1>;
281};
282
283&cp0_eth2 {
284	status = "okay";
285	phy = <&phy1>;
286	phy-mode = "rgmii-id";
287};
288