1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 4 * 5 * Copyright (C) 2016 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/ { 14 model = "Marvell Armada 37xx SoC"; 15 compatible = "marvell,armada3700"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a53", "arm,armv8"; 31 reg = <0>; 32 clocks = <&nb_periph_clk 16>; 33 enable-method = "psci"; 34 }; 35 }; 36 37 psci { 38 compatible = "arm,psci-0.2"; 39 method = "smc"; 40 }; 41 42 timer { 43 compatible = "arm,armv8-timer"; 44 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 48 }; 49 50 pmu { 51 compatible = "arm,armv8-pmuv3"; 52 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 53 }; 54 55 soc { 56 compatible = "simple-bus"; 57 #address-cells = <2>; 58 #size-cells = <2>; 59 ranges; 60 61 internal-regs@d0000000 { 62 #address-cells = <1>; 63 #size-cells = <1>; 64 compatible = "simple-bus"; 65 /* 32M internal register @ 0xd000_0000 */ 66 ranges = <0x0 0x0 0xd0000000 0x2000000>; 67 68 spi0: spi@10600 { 69 compatible = "marvell,armada-3700-spi"; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 reg = <0x10600 0xA00>; 73 clocks = <&nb_periph_clk 7>; 74 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 75 num-cs = <4>; 76 status = "disabled"; 77 }; 78 79 i2c0: i2c@11000 { 80 compatible = "marvell,armada-3700-i2c"; 81 reg = <0x11000 0x24>; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 clocks = <&nb_periph_clk 10>; 85 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 86 mrvl,i2c-fast-mode; 87 status = "disabled"; 88 }; 89 90 i2c1: i2c@11080 { 91 compatible = "marvell,armada-3700-i2c"; 92 reg = <0x11080 0x24>; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 clocks = <&nb_periph_clk 9>; 96 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 97 mrvl,i2c-fast-mode; 98 status = "disabled"; 99 }; 100 101 uart0: serial@12000 { 102 compatible = "marvell,armada-3700-uart"; 103 reg = <0x12000 0x200>; 104 clocks = <&xtalclk>; 105 interrupts = 106 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 109 interrupt-names = "uart-sum", "uart-tx", "uart-rx"; 110 status = "disabled"; 111 }; 112 113 uart1: serial@12200 { 114 compatible = "marvell,armada-3700-uart-ext"; 115 reg = <0x12200 0x30>; 116 clocks = <&xtalclk>; 117 interrupts = 118 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 119 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 120 interrupt-names = "uart-tx", "uart-rx"; 121 status = "disabled"; 122 }; 123 124 nb_periph_clk: nb-periph-clk@13000 { 125 compatible = "marvell,armada-3700-periph-clock-nb"; 126 reg = <0x13000 0x100>; 127 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 128 <&tbg 3>, <&xtalclk>; 129 #clock-cells = <1>; 130 }; 131 132 sb_periph_clk: sb-periph-clk@18000 { 133 compatible = "marvell,armada-3700-periph-clock-sb"; 134 reg = <0x18000 0x100>; 135 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 136 <&tbg 3>, <&xtalclk>; 137 #clock-cells = <1>; 138 }; 139 140 tbg: tbg@13200 { 141 compatible = "marvell,armada-3700-tbg-clock"; 142 reg = <0x13200 0x100>; 143 clocks = <&xtalclk>; 144 #clock-cells = <1>; 145 }; 146 147 pinctrl_nb: pinctrl@13800 { 148 compatible = "marvell,armada3710-nb-pinctrl", 149 "syscon", "simple-mfd"; 150 reg = <0x13800 0x100>, <0x13C00 0x20>; 151 /* MPP1[19:0] */ 152 gpionb: gpio { 153 #gpio-cells = <2>; 154 gpio-ranges = <&pinctrl_nb 0 0 36>; 155 gpio-controller; 156 interrupt-controller; 157 #interrupt-cells = <2>; 158 interrupts = 159 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 171 }; 172 173 xtalclk: xtal-clk { 174 compatible = "marvell,armada-3700-xtal-clock"; 175 clock-output-names = "xtal"; 176 #clock-cells = <0>; 177 }; 178 179 spi_quad_pins: spi-quad-pins { 180 groups = "spi_quad"; 181 function = "spi"; 182 }; 183 184 i2c1_pins: i2c1-pins { 185 groups = "i2c1"; 186 function = "i2c"; 187 }; 188 189 i2c2_pins: i2c2-pins { 190 groups = "i2c2"; 191 function = "i2c"; 192 }; 193 194 uart1_pins: uart1-pins { 195 groups = "uart1"; 196 function = "uart"; 197 }; 198 199 uart2_pins: uart2-pins { 200 groups = "uart2"; 201 function = "uart"; 202 }; 203 }; 204 205 nb_pm: syscon@14000 { 206 compatible = "marvell,armada-3700-nb-pm", 207 "syscon"; 208 reg = <0x14000 0x60>; 209 }; 210 211 pinctrl_sb: pinctrl@18800 { 212 compatible = "marvell,armada3710-sb-pinctrl", 213 "syscon", "simple-mfd"; 214 reg = <0x18800 0x100>, <0x18C00 0x20>; 215 /* MPP2[23:0] */ 216 gpiosb: gpio { 217 #gpio-cells = <2>; 218 gpio-ranges = <&pinctrl_sb 0 0 30>; 219 gpio-controller; 220 interrupt-controller; 221 #interrupt-cells = <2>; 222 interrupts = 223 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 228 }; 229 230 rgmii_pins: mii-pins { 231 groups = "rgmii"; 232 function = "mii"; 233 }; 234 235 }; 236 237 eth0: ethernet@30000 { 238 compatible = "marvell,armada-3700-neta"; 239 reg = <0x30000 0x4000>; 240 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&sb_periph_clk 8>; 242 status = "disabled"; 243 }; 244 245 mdio: mdio@32004 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 compatible = "marvell,orion-mdio"; 249 reg = <0x32004 0x4>; 250 }; 251 252 eth1: ethernet@40000 { 253 compatible = "marvell,armada-3700-neta"; 254 reg = <0x40000 0x4000>; 255 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&sb_periph_clk 7>; 257 status = "disabled"; 258 }; 259 260 usb3: usb@58000 { 261 compatible = "marvell,armada3700-xhci", 262 "generic-xhci"; 263 reg = <0x58000 0x4000>; 264 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&sb_periph_clk 12>; 266 status = "disabled"; 267 }; 268 269 usb2: usb@5e000 { 270 compatible = "marvell,armada-3700-ehci"; 271 reg = <0x5e000 0x2000>; 272 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 273 status = "disabled"; 274 }; 275 276 xor@60900 { 277 compatible = "marvell,armada-3700-xor"; 278 reg = <0x60900 0x100>, 279 <0x60b00 0x100>; 280 281 xor10 { 282 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 283 }; 284 xor11 { 285 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 286 }; 287 }; 288 289 crypto: crypto@90000 { 290 compatible = "inside-secure,safexcel-eip97"; 291 reg = <0x90000 0x20000>; 292 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 298 interrupt-names = "mem", "ring0", "ring1", 299 "ring2", "ring3", "eip"; 300 clocks = <&nb_periph_clk 15>; 301 }; 302 303 sdhci1: sdhci@d0000 { 304 compatible = "marvell,armada-3700-sdhci", 305 "marvell,sdhci-xenon"; 306 reg = <0xd0000 0x300>, 307 <0x1e808 0x4>; 308 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&nb_periph_clk 0>; 310 clock-names = "core"; 311 status = "disabled"; 312 }; 313 314 sdhci0: sdhci@d8000 { 315 compatible = "marvell,armada-3700-sdhci", 316 "marvell,sdhci-xenon"; 317 reg = <0xd8000 0x300>, 318 <0x17808 0x4>; 319 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&nb_periph_clk 0>; 321 clock-names = "core"; 322 status = "disabled"; 323 }; 324 325 sata: sata@e0000 { 326 compatible = "marvell,armada-3700-ahci"; 327 reg = <0xe0000 0x2000>; 328 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 329 status = "disabled"; 330 }; 331 332 gic: interrupt-controller@1d00000 { 333 compatible = "arm,gic-v3"; 334 #interrupt-cells = <3>; 335 interrupt-controller; 336 reg = <0x1d00000 0x10000>, /* GICD */ 337 <0x1d40000 0x40000>, /* GICR */ 338 <0x1d80000 0x2000>, /* GICC */ 339 <0x1d90000 0x2000>, /* GICH */ 340 <0x1da0000 0x20000>; /* GICV */ 341 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 342 }; 343 }; 344 345 pcie0: pcie@d0070000 { 346 compatible = "marvell,armada-3700-pcie"; 347 device_type = "pci"; 348 status = "disabled"; 349 reg = <0 0xd0070000 0 0x20000>; 350 #address-cells = <3>; 351 #size-cells = <2>; 352 bus-range = <0x00 0xff>; 353 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 354 #interrupt-cells = <1>; 355 msi-parent = <&pcie0>; 356 msi-controller; 357 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 358 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 359 interrupt-map-mask = <0 0 0 7>; 360 interrupt-map = <0 0 0 1 &pcie_intc 0>, 361 <0 0 0 2 &pcie_intc 1>, 362 <0 0 0 3 &pcie_intc 2>, 363 <0 0 0 4 &pcie_intc 3>; 364 pcie_intc: interrupt-controller { 365 interrupt-controller; 366 #interrupt-cells = <1>; 367 }; 368 }; 369 }; 370}; 371