1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 *
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14	model = "Marvell Armada 37xx SoC";
15	compatible = "marvell,armada3700";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		serial0 = &uart0;
22		serial1 = &uart1;
23	};
24
25	reserved-memory {
26		#address-cells = <2>;
27		#size-cells = <2>;
28		ranges;
29
30		/*
31		 * The PSCI firmware region depicted below is the default one
32		 * and should be updated by the bootloader.
33		 */
34		psci-area@4000000 {
35			reg = <0 0x4000000 0 0x200000>;
36			no-map;
37		};
38	};
39
40	cpus {
41		#address-cells = <1>;
42		#size-cells = <0>;
43		cpu@0 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53", "arm,armv8";
46			reg = <0>;
47			clocks = <&nb_periph_clk 16>;
48			enable-method = "psci";
49		};
50	};
51
52	psci {
53		compatible = "arm,psci-0.2";
54		method = "smc";
55	};
56
57	timer {
58		compatible = "arm,armv8-timer";
59		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
60			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
61			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
62			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
63	};
64
65	pmu {
66		compatible = "arm,armv8-pmuv3";
67		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
68	};
69
70	soc {
71		compatible = "simple-bus";
72		#address-cells = <2>;
73		#size-cells = <2>;
74		ranges;
75
76		internal-regs@d0000000 {
77			#address-cells = <1>;
78			#size-cells = <1>;
79			compatible = "simple-bus";
80			/* 32M internal register @ 0xd000_0000 */
81			ranges = <0x0 0x0 0xd0000000 0x2000000>;
82
83			spi0: spi@10600 {
84				compatible = "marvell,armada-3700-spi";
85				#address-cells = <1>;
86				#size-cells = <0>;
87				reg = <0x10600 0xA00>;
88				clocks = <&nb_periph_clk 7>;
89				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
90				num-cs = <4>;
91				status = "disabled";
92			};
93
94			i2c0: i2c@11000 {
95				compatible = "marvell,armada-3700-i2c";
96				reg = <0x11000 0x24>;
97				#address-cells = <1>;
98				#size-cells = <0>;
99				clocks = <&nb_periph_clk 10>;
100				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
101				mrvl,i2c-fast-mode;
102				status = "disabled";
103			};
104
105			i2c1: i2c@11080 {
106				compatible = "marvell,armada-3700-i2c";
107				reg = <0x11080 0x24>;
108				#address-cells = <1>;
109				#size-cells = <0>;
110				clocks = <&nb_periph_clk 9>;
111				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
112				mrvl,i2c-fast-mode;
113				status = "disabled";
114			};
115
116			avs: avs@11500 {
117				compatible = "marvell,armada-3700-avs",
118					     "syscon";
119				reg = <0x11500 0x40>;
120			};
121
122			uart0: serial@12000 {
123				compatible = "marvell,armada-3700-uart";
124				reg = <0x12000 0x200>;
125				clocks = <&xtalclk>;
126				interrupts =
127				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
128				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
129				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
130				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
131				status = "disabled";
132			};
133
134			uart1: serial@12200 {
135				compatible = "marvell,armada-3700-uart-ext";
136				reg = <0x12200 0x30>;
137				clocks = <&xtalclk>;
138				interrupts =
139				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
140				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
141				interrupt-names = "uart-tx", "uart-rx";
142				status = "disabled";
143			};
144
145			nb_periph_clk: nb-periph-clk@13000 {
146				compatible = "marvell,armada-3700-periph-clock-nb";
147				reg = <0x13000 0x100>;
148				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
149				<&tbg 3>, <&xtalclk>;
150				#clock-cells = <1>;
151			};
152
153			sb_periph_clk: sb-periph-clk@18000 {
154				compatible = "marvell,armada-3700-periph-clock-sb";
155				reg = <0x18000 0x100>;
156				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
157				<&tbg 3>, <&xtalclk>;
158				#clock-cells = <1>;
159			};
160
161			tbg: tbg@13200 {
162				compatible = "marvell,armada-3700-tbg-clock";
163				reg = <0x13200 0x100>;
164				clocks = <&xtalclk>;
165				#clock-cells = <1>;
166			};
167
168			pinctrl_nb: pinctrl@13800 {
169				compatible = "marvell,armada3710-nb-pinctrl",
170					     "syscon", "simple-mfd";
171				reg = <0x13800 0x100>, <0x13C00 0x20>;
172				/* MPP1[19:0] */
173				gpionb: gpio {
174					#gpio-cells = <2>;
175					gpio-ranges = <&pinctrl_nb 0 0 36>;
176					gpio-controller;
177					interrupt-controller;
178					#interrupt-cells = <2>;
179					interrupts =
180					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
181					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
182					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
183					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
184					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
185					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
186					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
187					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
188					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
189					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
190					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
191					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
192				};
193
194				xtalclk: xtal-clk {
195					compatible = "marvell,armada-3700-xtal-clock";
196					clock-output-names = "xtal";
197					#clock-cells = <0>;
198				};
199
200				spi_quad_pins: spi-quad-pins {
201					groups = "spi_quad";
202					function = "spi";
203				};
204
205				i2c1_pins: i2c1-pins {
206					groups = "i2c1";
207					function = "i2c";
208				};
209
210				i2c2_pins: i2c2-pins {
211					groups = "i2c2";
212					function = "i2c";
213				};
214
215				uart1_pins: uart1-pins {
216					groups = "uart1";
217					function = "uart";
218				};
219
220				uart2_pins: uart2-pins {
221					groups = "uart2";
222					function = "uart";
223				};
224			};
225
226			nb_pm: syscon@14000 {
227				compatible = "marvell,armada-3700-nb-pm",
228					     "syscon";
229				reg = <0x14000 0x60>;
230			};
231
232			pinctrl_sb: pinctrl@18800 {
233				compatible = "marvell,armada3710-sb-pinctrl",
234					     "syscon", "simple-mfd";
235				reg = <0x18800 0x100>, <0x18C00 0x20>;
236				/* MPP2[23:0] */
237				gpiosb: gpio {
238					#gpio-cells = <2>;
239					gpio-ranges = <&pinctrl_sb 0 0 30>;
240					gpio-controller;
241					interrupt-controller;
242					#interrupt-cells = <2>;
243					interrupts =
244					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
245					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
246					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
247					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
248					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
249				};
250
251				rgmii_pins: mii-pins {
252					groups = "rgmii";
253					function = "mii";
254				};
255
256			};
257
258			eth0: ethernet@30000 {
259				   compatible = "marvell,armada-3700-neta";
260				   reg = <0x30000 0x4000>;
261				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
262				   clocks = <&sb_periph_clk 8>;
263				   status = "disabled";
264			};
265
266			mdio: mdio@32004 {
267				#address-cells = <1>;
268				#size-cells = <0>;
269				compatible = "marvell,orion-mdio";
270				reg = <0x32004 0x4>;
271			};
272
273			eth1: ethernet@40000 {
274				compatible = "marvell,armada-3700-neta";
275				reg = <0x40000 0x4000>;
276				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
277				clocks = <&sb_periph_clk 7>;
278				status = "disabled";
279			};
280
281			usb3: usb@58000 {
282				compatible = "marvell,armada3700-xhci",
283				"generic-xhci";
284				reg = <0x58000 0x4000>;
285				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
286				clocks = <&sb_periph_clk 12>;
287				status = "disabled";
288			};
289
290			usb2: usb@5e000 {
291				compatible = "marvell,armada-3700-ehci";
292				reg = <0x5e000 0x2000>;
293				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
294				status = "disabled";
295			};
296
297			xor@60900 {
298				compatible = "marvell,armada-3700-xor";
299				reg = <0x60900 0x100>,
300				      <0x60b00 0x100>;
301
302				xor10 {
303					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
304				};
305				xor11 {
306					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
307				};
308			};
309
310			crypto: crypto@90000 {
311				compatible = "inside-secure,safexcel-eip97ies";
312				reg = <0x90000 0x20000>;
313				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
314					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
315					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
316					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
317					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
318					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
319				interrupt-names = "mem", "ring0", "ring1",
320						  "ring2", "ring3", "eip";
321				clocks = <&nb_periph_clk 15>;
322			};
323
324			sdhci1: sdhci@d0000 {
325				compatible = "marvell,armada-3700-sdhci",
326					     "marvell,sdhci-xenon";
327				reg = <0xd0000 0x300>,
328				      <0x1e808 0x4>;
329				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
330				clocks = <&nb_periph_clk 0>;
331				clock-names = "core";
332				status = "disabled";
333			};
334
335			sdhci0: sdhci@d8000 {
336				compatible = "marvell,armada-3700-sdhci",
337					     "marvell,sdhci-xenon";
338				reg = <0xd8000 0x300>,
339				      <0x17808 0x4>;
340				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
341				clocks = <&nb_periph_clk 0>;
342				clock-names = "core";
343				status = "disabled";
344			};
345
346			sata: sata@e0000 {
347				compatible = "marvell,armada-3700-ahci";
348				reg = <0xe0000 0x2000>;
349				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
350				status = "disabled";
351			};
352
353			gic: interrupt-controller@1d00000 {
354				compatible = "arm,gic-v3";
355				#interrupt-cells = <3>;
356				interrupt-controller;
357				reg = <0x1d00000 0x10000>, /* GICD */
358				      <0x1d40000 0x40000>, /* GICR */
359				      <0x1d80000 0x2000>,  /* GICC */
360				      <0x1d90000 0x2000>,  /* GICH */
361				      <0x1da0000 0x20000>; /* GICV */
362				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
363			};
364		};
365
366		pcie0: pcie@d0070000 {
367			compatible = "marvell,armada-3700-pcie";
368			device_type = "pci";
369			status = "disabled";
370			reg = <0 0xd0070000 0 0x20000>;
371			#address-cells = <3>;
372			#size-cells = <2>;
373			bus-range = <0x00 0xff>;
374			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
375			#interrupt-cells = <1>;
376			msi-parent = <&pcie0>;
377			msi-controller;
378			ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
379				  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
380			interrupt-map-mask = <0 0 0 7>;
381			interrupt-map = <0 0 0 1 &pcie_intc 0>,
382					<0 0 0 2 &pcie_intc 1>,
383					<0 0 0 3 &pcie_intc 2>,
384					<0 0 0 4 &pcie_intc 3>;
385			pcie_intc: interrupt-controller {
386				interrupt-controller;
387				#interrupt-cells = <1>;
388			};
389		};
390	};
391};
392