1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 *
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14	model = "Marvell Armada 37xx SoC";
15	compatible = "marvell,armada3700";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		serial0 = &uart0;
22		serial1 = &uart1;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28		cpu@0 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a53", "arm,armv8";
31			reg = <0>;
32			clocks = <&nb_periph_clk 16>;
33			enable-method = "psci";
34		};
35	};
36
37	psci {
38		compatible = "arm,psci-0.2";
39		method = "smc";
40	};
41
42	timer {
43		compatible = "arm,armv8-timer";
44		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
45			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
46			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
47			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
48	};
49
50	pmu {
51		compatible = "arm,armv8-pmuv3";
52		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
53	};
54
55	soc {
56		compatible = "simple-bus";
57		#address-cells = <2>;
58		#size-cells = <2>;
59		ranges;
60
61		internal-regs@d0000000 {
62			#address-cells = <1>;
63			#size-cells = <1>;
64			compatible = "simple-bus";
65			/* 32M internal register @ 0xd000_0000 */
66			ranges = <0x0 0x0 0xd0000000 0x2000000>;
67
68			spi0: spi@10600 {
69				compatible = "marvell,armada-3700-spi";
70				#address-cells = <1>;
71				#size-cells = <0>;
72				reg = <0x10600 0xA00>;
73				clocks = <&nb_periph_clk 7>;
74				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
75				num-cs = <4>;
76				status = "disabled";
77			};
78
79			i2c0: i2c@11000 {
80				compatible = "marvell,armada-3700-i2c";
81				reg = <0x11000 0x24>;
82				#address-cells = <1>;
83				#size-cells = <0>;
84				clocks = <&nb_periph_clk 10>;
85				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
86				mrvl,i2c-fast-mode;
87				status = "disabled";
88			};
89
90			i2c1: i2c@11080 {
91				compatible = "marvell,armada-3700-i2c";
92				reg = <0x11080 0x24>;
93				#address-cells = <1>;
94				#size-cells = <0>;
95				clocks = <&nb_periph_clk 9>;
96				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
97				mrvl,i2c-fast-mode;
98				status = "disabled";
99			};
100
101			uart0: serial@12000 {
102				compatible = "marvell,armada-3700-uart";
103				reg = <0x12000 0x200>;
104				clocks = <&xtalclk>;
105				interrupts =
106				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
107				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
108				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
109				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
110				status = "disabled";
111			};
112
113			uart1: serial@12200 {
114				compatible = "marvell,armada-3700-uart-ext";
115				reg = <0x12200 0x30>;
116				clocks = <&xtalclk>;
117				interrupts =
118				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
119				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
120				interrupt-names = "uart-tx", "uart-rx";
121				status = "disabled";
122			};
123
124			nb_periph_clk: nb-periph-clk@13000 {
125				compatible = "marvell,armada-3700-periph-clock-nb";
126				reg = <0x13000 0x100>;
127				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
128				<&tbg 3>, <&xtalclk>;
129				#clock-cells = <1>;
130			};
131
132			sb_periph_clk: sb-periph-clk@18000 {
133				compatible = "marvell,armada-3700-periph-clock-sb";
134				reg = <0x18000 0x100>;
135				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
136				<&tbg 3>, <&xtalclk>;
137				#clock-cells = <1>;
138			};
139
140			tbg: tbg@13200 {
141				compatible = "marvell,armada-3700-tbg-clock";
142				reg = <0x13200 0x100>;
143				clocks = <&xtalclk>;
144				#clock-cells = <1>;
145			};
146
147			pinctrl_nb: pinctrl@13800 {
148				compatible = "marvell,armada3710-nb-pinctrl",
149					     "syscon", "simple-mfd";
150				reg = <0x13800 0x100>, <0x13C00 0x20>;
151				gpionb: gpio {
152					#gpio-cells = <2>;
153					gpio-ranges = <&pinctrl_nb 0 0 36>;
154					gpio-controller;
155					interrupts =
156					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
157					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
158					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
159					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
160					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
161					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
162					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
163					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
164					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
165					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
166					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
167					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
168				};
169
170				xtalclk: xtal-clk {
171					compatible = "marvell,armada-3700-xtal-clock";
172					clock-output-names = "xtal";
173					#clock-cells = <0>;
174				};
175
176				spi_quad_pins: spi-quad-pins {
177					groups = "spi_quad";
178					function = "spi";
179				};
180
181				i2c1_pins: i2c1-pins {
182					groups = "i2c1";
183					function = "i2c";
184				};
185
186				i2c2_pins: i2c2-pins {
187					groups = "i2c2";
188					function = "i2c";
189				};
190
191				uart1_pins: uart1-pins {
192					groups = "uart1";
193					function = "uart";
194				};
195
196				uart2_pins: uart2-pins {
197					groups = "uart2";
198					function = "uart";
199				};
200			};
201
202			nb_pm: syscon@14000 {
203				compatible = "marvell,armada-3700-nb-pm",
204					     "syscon";
205				reg = <0x14000 0x60>;
206			};
207
208			pinctrl_sb: pinctrl@18800 {
209				compatible = "marvell,armada3710-sb-pinctrl",
210					     "syscon", "simple-mfd";
211				reg = <0x18800 0x100>, <0x18C00 0x20>;
212				gpiosb: gpio {
213					#gpio-cells = <2>;
214					gpio-ranges = <&pinctrl_sb 0 0 30>;
215					gpio-controller;
216					interrupts =
217					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
218					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
219					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
220					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
221					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
222				};
223
224				rgmii_pins: mii-pins {
225					groups = "rgmii";
226					function = "mii";
227				};
228
229			};
230
231			eth0: ethernet@30000 {
232				   compatible = "marvell,armada-3700-neta";
233				   reg = <0x30000 0x4000>;
234				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
235				   clocks = <&sb_periph_clk 8>;
236				   status = "disabled";
237			};
238
239			mdio: mdio@32004 {
240				#address-cells = <1>;
241				#size-cells = <0>;
242				compatible = "marvell,orion-mdio";
243				reg = <0x32004 0x4>;
244			};
245
246			eth1: ethernet@40000 {
247				compatible = "marvell,armada-3700-neta";
248				reg = <0x40000 0x4000>;
249				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
250				clocks = <&sb_periph_clk 7>;
251				status = "disabled";
252			};
253
254			usb3: usb@58000 {
255				compatible = "marvell,armada3700-xhci",
256				"generic-xhci";
257				reg = <0x58000 0x4000>;
258				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
259				clocks = <&sb_periph_clk 12>;
260				status = "disabled";
261			};
262
263			usb2: usb@5e000 {
264				compatible = "marvell,armada-3700-ehci";
265				reg = <0x5e000 0x2000>;
266				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
267				status = "disabled";
268			};
269
270			xor@60900 {
271				compatible = "marvell,armada-3700-xor";
272				reg = <0x60900 0x100>,
273				      <0x60b00 0x100>;
274
275				xor10 {
276					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
277				};
278				xor11 {
279					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
280				};
281			};
282
283			crypto: crypto@90000 {
284				compatible = "inside-secure,safexcel-eip97";
285				reg = <0x90000 0x20000>;
286				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
287					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
288					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
289					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
290					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
291					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
292				interrupt-names = "mem", "ring0", "ring1",
293						  "ring2", "ring3", "eip";
294				clocks = <&nb_periph_clk 15>;
295			};
296
297			sdhci1: sdhci@d0000 {
298				compatible = "marvell,armada-3700-sdhci",
299					     "marvell,sdhci-xenon";
300				reg = <0xd0000 0x300>,
301				      <0x1e808 0x4>;
302				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
303				clocks = <&nb_periph_clk 0>;
304				clock-names = "core";
305				status = "disabled";
306			};
307
308			sdhci0: sdhci@d8000 {
309				compatible = "marvell,armada-3700-sdhci",
310					     "marvell,sdhci-xenon";
311				reg = <0xd8000 0x300>,
312				      <0x17808 0x4>;
313				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
314				clocks = <&nb_periph_clk 0>;
315				clock-names = "core";
316				status = "disabled";
317			};
318
319			sata: sata@e0000 {
320				compatible = "marvell,armada-3700-ahci";
321				reg = <0xe0000 0x2000>;
322				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
323				status = "disabled";
324			};
325
326			gic: interrupt-controller@1d00000 {
327				compatible = "arm,gic-v3";
328				#interrupt-cells = <3>;
329				interrupt-controller;
330				reg = <0x1d00000 0x10000>, /* GICD */
331				      <0x1d40000 0x40000>, /* GICR */
332				      <0x1d80000 0x2000>,  /* GICC */
333				      <0x1d90000 0x2000>,  /* GICH */
334				      <0x1da0000 0x20000>; /* GICV */
335				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
336			};
337		};
338
339		pcie0: pcie@d0070000 {
340			compatible = "marvell,armada-3700-pcie";
341			device_type = "pci";
342			status = "disabled";
343			reg = <0 0xd0070000 0 0x20000>;
344			#address-cells = <3>;
345			#size-cells = <2>;
346			bus-range = <0x00 0xff>;
347			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
348			#interrupt-cells = <1>;
349			msi-parent = <&pcie0>;
350			msi-controller;
351			ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
352				  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
353			interrupt-map-mask = <0 0 0 7>;
354			interrupt-map = <0 0 0 1 &pcie_intc 0>,
355					<0 0 0 2 &pcie_intc 1>,
356					<0 0 0 3 &pcie_intc 2>,
357					<0 0 0 4 &pcie_intc 3>;
358			pcie_intc: interrupt-controller {
359				interrupt-controller;
360				#interrupt-cells = <1>;
361			};
362		};
363	};
364};
365