1/* 2 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3 * 4 * Copyright (C) 2016 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49/ { 50 model = "Marvell Armada 37xx SoC"; 51 compatible = "marvell,armada3700"; 52 interrupt-parent = <&gic>; 53 #address-cells = <2>; 54 #size-cells = <2>; 55 56 aliases { 57 serial0 = &uart0; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53", "arm,armv8"; 66 reg = <0>; 67 enable-method = "psci"; 68 }; 69 }; 70 71 psci { 72 compatible = "arm,psci-0.2"; 73 method = "smc"; 74 }; 75 76 timer { 77 compatible = "arm,armv8-timer"; 78 interrupts = <GIC_PPI 13 79 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 80 <GIC_PPI 14 81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 11 83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84 <GIC_PPI 10 85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 86 }; 87 88 soc { 89 compatible = "simple-bus"; 90 #address-cells = <2>; 91 #size-cells = <2>; 92 ranges; 93 94 internal-regs@d0000000 { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 compatible = "simple-bus"; 98 /* 32M internal register @ 0xd000_0000 */ 99 ranges = <0x0 0x0 0xd0000000 0x2000000>; 100 101 spi0: spi@10600 { 102 compatible = "marvell,armada-3700-spi"; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 reg = <0x10600 0xA00>; 106 clocks = <&nb_periph_clk 7>; 107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 108 num-cs = <4>; 109 status = "disabled"; 110 }; 111 112 i2c0: i2c@11000 { 113 compatible = "marvell,armada-3700-i2c"; 114 reg = <0x11000 0x24>; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 clocks = <&nb_periph_clk 10>; 118 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 119 mrvl,i2c-fast-mode; 120 status = "disabled"; 121 }; 122 123 i2c1: i2c@11080 { 124 compatible = "marvell,armada-3700-i2c"; 125 reg = <0x11080 0x24>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&nb_periph_clk 9>; 129 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 130 mrvl,i2c-fast-mode; 131 status = "disabled"; 132 }; 133 134 uart0: serial@12000 { 135 compatible = "marvell,armada-3700-uart"; 136 reg = <0x12000 0x400>; 137 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 138 status = "disabled"; 139 }; 140 141 nb_periph_clk: nb-periph-clk@13000 { 142 compatible = "marvell,armada-3700-periph-clock-nb"; 143 reg = <0x13000 0x100>; 144 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 145 <&tbg 3>, <&xtalclk>; 146 #clock-cells = <1>; 147 }; 148 149 sb_periph_clk: sb-periph-clk@18000 { 150 compatible = "marvell,armada-3700-periph-clock-sb"; 151 reg = <0x18000 0x100>; 152 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 153 <&tbg 3>, <&xtalclk>; 154 #clock-cells = <1>; 155 }; 156 157 tbg: tbg@13200 { 158 compatible = "marvell,armada-3700-tbg-clock"; 159 reg = <0x13200 0x100>; 160 clocks = <&xtalclk>; 161 #clock-cells = <1>; 162 }; 163 164 pinctrl_nb: pinctrl@13800 { 165 compatible = "marvell,armada3710-nb-pinctrl", 166 "syscon", "simple-mfd"; 167 reg = <0x13800 0x100>, <0x13C00 0x20>; 168 gpionb: gpio { 169 #gpio-cells = <2>; 170 gpio-ranges = <&pinctrl_nb 0 0 36>; 171 gpio-controller; 172 interrupts = 173 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 185 186 }; 187 188 xtalclk: xtal-clk { 189 compatible = "marvell,armada-3700-xtal-clock"; 190 clock-output-names = "xtal"; 191 #clock-cells = <0>; 192 }; 193 194 spi_quad_pins: spi-quad-pins { 195 groups = "spi_quad"; 196 function = "spi"; 197 }; 198 199 i2c1_pins: i2c1-pins { 200 groups = "i2c1"; 201 function = "i2c"; 202 }; 203 204 i2c2_pins: i2c2-pins { 205 groups = "i2c2"; 206 function = "i2c"; 207 }; 208 209 uart1_pins: uart1-pins { 210 groups = "uart1"; 211 function = "uart"; 212 }; 213 214 uart2_pins: uart2-pins { 215 groups = "uart2"; 216 function = "uart"; 217 }; 218 }; 219 220 pinctrl_sb: pinctrl@18800 { 221 compatible = "marvell,armada3710-sb-pinctrl", 222 "syscon", "simple-mfd"; 223 reg = <0x18800 0x100>, <0x18C00 0x20>; 224 gpiosb: gpio { 225 #gpio-cells = <2>; 226 gpio-ranges = <&pinctrl_sb 0 0 29>; 227 gpio-controller; 228 interrupts = 229 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 234 }; 235 236 rgmii_pins: mii-pins { 237 groups = "rgmii"; 238 function = "mii"; 239 }; 240 241 }; 242 243 eth0: ethernet@30000 { 244 compatible = "marvell,armada-3700-neta"; 245 reg = <0x30000 0x4000>; 246 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&sb_periph_clk 8>; 248 status = "disabled"; 249 }; 250 251 mdio: mdio@32004 { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 compatible = "marvell,orion-mdio"; 255 reg = <0x32004 0x4>; 256 }; 257 258 eth1: ethernet@40000 { 259 compatible = "marvell,armada-3700-neta"; 260 reg = <0x40000 0x4000>; 261 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&sb_periph_clk 7>; 263 status = "disabled"; 264 }; 265 266 usb3: usb@58000 { 267 compatible = "marvell,armada3700-xhci", 268 "generic-xhci"; 269 reg = <0x58000 0x4000>; 270 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&sb_periph_clk 12>; 272 status = "disabled"; 273 }; 274 275 usb2: usb@5e000 { 276 compatible = "marvell,armada-3700-ehci"; 277 reg = <0x5e000 0x2000>; 278 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 279 status = "disabled"; 280 }; 281 282 xor@60900 { 283 compatible = "marvell,armada-3700-xor"; 284 reg = <0x60900 0x100 285 0x60b00 0x100>; 286 287 xor10 { 288 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 289 }; 290 xor11 { 291 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 292 }; 293 }; 294 295 sdhci0: sdhci@d8000 { 296 compatible = "marvell,armada-3700-sdhci", 297 "marvell,sdhci-xenon"; 298 reg = <0xd8000 0x300 299 0x17808 0x4>; 300 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&nb_periph_clk 0>; 302 clock-names = "core"; 303 status = "disabled"; 304 }; 305 306 sata: sata@e0000 { 307 compatible = "marvell,armada-3700-ahci"; 308 reg = <0xe0000 0x2000>; 309 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 310 status = "disabled"; 311 }; 312 313 gic: interrupt-controller@1d00000 { 314 compatible = "arm,gic-v3"; 315 #interrupt-cells = <3>; 316 interrupt-controller; 317 reg = <0x1d00000 0x10000>, /* GICD */ 318 <0x1d40000 0x40000>; /* GICR */ 319 }; 320 }; 321 322 pcie0: pcie@d0070000 { 323 compatible = "marvell,armada-3700-pcie"; 324 device_type = "pci"; 325 status = "disabled"; 326 reg = <0 0xd0070000 0 0x20000>; 327 #address-cells = <3>; 328 #size-cells = <2>; 329 bus-range = <0x00 0xff>; 330 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 331 #interrupt-cells = <1>; 332 msi-parent = <&pcie0>; 333 msi-controller; 334 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 335 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 336 interrupt-map-mask = <0 0 0 7>; 337 interrupt-map = <0 0 0 1 &pcie_intc 0>, 338 <0 0 0 2 &pcie_intc 1>, 339 <0 0 0 3 &pcie_intc 2>, 340 <0 0 0 4 &pcie_intc 3>; 341 pcie_intc: interrupt-controller { 342 interrupt-controller; 343 #interrupt-cells = <1>; 344 }; 345 }; 346 }; 347}; 348