1/* 2 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3 * 4 * Copyright (C) 2016 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49/ { 50 model = "Marvell Armada 37xx SoC"; 51 compatible = "marvell,armada3700"; 52 interrupt-parent = <&gic>; 53 #address-cells = <2>; 54 #size-cells = <2>; 55 56 aliases { 57 serial0 = &uart0; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53", "arm,armv8"; 66 reg = <0>; 67 enable-method = "psci"; 68 }; 69 }; 70 71 psci { 72 compatible = "arm,psci-0.2"; 73 method = "smc"; 74 }; 75 76 timer { 77 compatible = "arm,armv8-timer"; 78 interrupts = <GIC_PPI 13 79 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 80 <GIC_PPI 14 81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 11 83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84 <GIC_PPI 10 85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 86 }; 87 88 soc { 89 compatible = "simple-bus"; 90 #address-cells = <2>; 91 #size-cells = <2>; 92 ranges; 93 94 internal-regs@d0000000 { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 compatible = "simple-bus"; 98 /* 32M internal register @ 0xd000_0000 */ 99 ranges = <0x0 0x0 0xd0000000 0x2000000>; 100 101 uart0: serial@12000 { 102 compatible = "marvell,armada-3700-uart"; 103 reg = <0x12000 0x400>; 104 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 105 status = "disabled"; 106 }; 107 108 nb_periph_clk: nb-periph-clk@13000 { 109 compatible = "marvell,armada-3700-periph-clock-nb"; 110 reg = <0x13000 0x100>; 111 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 112 <&tbg 3>, <&xtalclk>; 113 #clock-cells = <1>; 114 }; 115 116 sb_periph_clk: sb-periph-clk@18000 { 117 compatible = "marvell,armada-3700-periph-clock-sb"; 118 reg = <0x18000 0x100>; 119 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 120 <&tbg 3>, <&xtalclk>; 121 #clock-cells = <1>; 122 }; 123 124 tbg: tbg@13200 { 125 compatible = "marvell,armada-3700-tbg-clock"; 126 reg = <0x13200 0x100>; 127 clocks = <&xtalclk>; 128 #clock-cells = <1>; 129 }; 130 131 gpio1: gpio@13800 { 132 compatible = "marvell,mvebu-gpio-3700", 133 "syscon", "simple-mfd"; 134 reg = <0x13800 0x500>; 135 136 xtalclk: xtal-clk { 137 compatible = "marvell,armada-3700-xtal-clock"; 138 clock-output-names = "xtal"; 139 #clock-cells = <0>; 140 }; 141 }; 142 143 eth0: ethernet@30000 { 144 compatible = "marvell,armada-3700-neta"; 145 reg = <0x30000 0x4000>; 146 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&sb_periph_clk 8>; 148 status = "disabled"; 149 }; 150 151 mdio: mdio@32004 { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 compatible = "marvell,orion-mdio"; 155 reg = <0x32004 0x4>; 156 }; 157 158 eth1: ethernet@40000 { 159 compatible = "marvell,armada-3700-neta"; 160 reg = <0x40000 0x4000>; 161 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&sb_periph_clk 7>; 163 status = "disabled"; 164 }; 165 166 usb3: usb@58000 { 167 compatible = "marvell,armada3700-xhci", 168 "generic-xhci"; 169 reg = <0x58000 0x4000>; 170 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 171 status = "disabled"; 172 }; 173 174 xor@60900 { 175 compatible = "marvell,armada-3700-xor"; 176 reg = <0x60900 0x100 177 0x60b00 0x100>; 178 179 xor10 { 180 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 181 }; 182 xor11 { 183 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 184 }; 185 }; 186 187 sata: sata@e0000 { 188 compatible = "marvell,armada-3700-ahci"; 189 reg = <0xe0000 0x2000>; 190 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 191 status = "disabled"; 192 }; 193 194 gic: interrupt-controller@1d00000 { 195 compatible = "arm,gic-v3"; 196 #interrupt-cells = <3>; 197 interrupt-controller; 198 reg = <0x1d00000 0x10000>, /* GICD */ 199 <0x1d40000 0x40000>; /* GICR */ 200 }; 201 }; 202 203 pcie0: pcie@d0070000 { 204 compatible = "marvell,armada-3700-pcie"; 205 device_type = "pci"; 206 status = "disabled"; 207 reg = <0 0xd0070000 0 0x20000>; 208 #address-cells = <3>; 209 #size-cells = <2>; 210 bus-range = <0x00 0xff>; 211 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 212 #interrupt-cells = <1>; 213 msi-parent = <&pcie0>; 214 msi-controller; 215 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 216 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 217 interrupt-map-mask = <0 0 0 7>; 218 interrupt-map = <0 0 0 1 &pcie_intc 0>, 219 <0 0 0 2 &pcie_intc 1>, 220 <0 0 0 3 &pcie_intc 2>, 221 <0 0 0 4 &pcie_intc 3>; 222 pcie_intc: interrupt-controller { 223 interrupt-controller; 224 #interrupt-cells = <1>; 225 }; 226 }; 227 }; 228}; 229