1/* 2 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3 * 4 * Copyright (C) 2016 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49/ { 50 model = "Marvell Armada 37xx SoC"; 51 compatible = "marvell,armada3700"; 52 interrupt-parent = <&gic>; 53 #address-cells = <2>; 54 #size-cells = <2>; 55 56 aliases { 57 serial0 = &uart0; 58 serial1 = &uart1; 59 }; 60 61 cpus { 62 #address-cells = <1>; 63 #size-cells = <0>; 64 cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 reg = <0>; 68 enable-method = "psci"; 69 }; 70 }; 71 72 psci { 73 compatible = "arm,psci-0.2"; 74 method = "smc"; 75 }; 76 77 timer { 78 compatible = "arm,armv8-timer"; 79 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 83 }; 84 85 pmu { 86 compatible = "arm,armv8-pmuv3"; 87 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 88 }; 89 90 soc { 91 compatible = "simple-bus"; 92 #address-cells = <2>; 93 #size-cells = <2>; 94 ranges; 95 96 internal-regs@d0000000 { 97 #address-cells = <1>; 98 #size-cells = <1>; 99 compatible = "simple-bus"; 100 /* 32M internal register @ 0xd000_0000 */ 101 ranges = <0x0 0x0 0xd0000000 0x2000000>; 102 103 spi0: spi@10600 { 104 compatible = "marvell,armada-3700-spi"; 105 #address-cells = <1>; 106 #size-cells = <0>; 107 reg = <0x10600 0xA00>; 108 clocks = <&nb_periph_clk 7>; 109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 110 num-cs = <4>; 111 status = "disabled"; 112 }; 113 114 i2c0: i2c@11000 { 115 compatible = "marvell,armada-3700-i2c"; 116 reg = <0x11000 0x24>; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 clocks = <&nb_periph_clk 10>; 120 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 121 mrvl,i2c-fast-mode; 122 status = "disabled"; 123 }; 124 125 i2c1: i2c@11080 { 126 compatible = "marvell,armada-3700-i2c"; 127 reg = <0x11080 0x24>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 clocks = <&nb_periph_clk 9>; 131 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 132 mrvl,i2c-fast-mode; 133 status = "disabled"; 134 }; 135 136 uart0: serial@12000 { 137 compatible = "marvell,armada-3700-uart"; 138 reg = <0x12000 0x200>; 139 clocks = <&xtalclk>; 140 interrupts = 141 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 144 interrupt-names = "uart-sum", "uart-tx", "uart-rx"; 145 status = "disabled"; 146 }; 147 148 uart1: serial@12200 { 149 compatible = "marvell,armada-3700-uart-ext"; 150 reg = <0x12200 0x30>; 151 clocks = <&xtalclk>; 152 interrupts = 153 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 154 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 155 interrupt-names = "uart-tx", "uart-rx"; 156 status = "disabled"; 157 }; 158 159 nb_periph_clk: nb-periph-clk@13000 { 160 compatible = "marvell,armada-3700-periph-clock-nb"; 161 reg = <0x13000 0x100>; 162 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 163 <&tbg 3>, <&xtalclk>; 164 #clock-cells = <1>; 165 }; 166 167 sb_periph_clk: sb-periph-clk@18000 { 168 compatible = "marvell,armada-3700-periph-clock-sb"; 169 reg = <0x18000 0x100>; 170 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 171 <&tbg 3>, <&xtalclk>; 172 #clock-cells = <1>; 173 }; 174 175 tbg: tbg@13200 { 176 compatible = "marvell,armada-3700-tbg-clock"; 177 reg = <0x13200 0x100>; 178 clocks = <&xtalclk>; 179 #clock-cells = <1>; 180 }; 181 182 pinctrl_nb: pinctrl@13800 { 183 compatible = "marvell,armada3710-nb-pinctrl", 184 "syscon", "simple-mfd"; 185 reg = <0x13800 0x100>, <0x13C00 0x20>; 186 gpionb: gpio { 187 #gpio-cells = <2>; 188 gpio-ranges = <&pinctrl_nb 0 0 36>; 189 gpio-controller; 190 interrupts = 191 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 203 }; 204 205 xtalclk: xtal-clk { 206 compatible = "marvell,armada-3700-xtal-clock"; 207 clock-output-names = "xtal"; 208 #clock-cells = <0>; 209 }; 210 211 spi_quad_pins: spi-quad-pins { 212 groups = "spi_quad"; 213 function = "spi"; 214 }; 215 216 i2c1_pins: i2c1-pins { 217 groups = "i2c1"; 218 function = "i2c"; 219 }; 220 221 i2c2_pins: i2c2-pins { 222 groups = "i2c2"; 223 function = "i2c"; 224 }; 225 226 uart1_pins: uart1-pins { 227 groups = "uart1"; 228 function = "uart"; 229 }; 230 231 uart2_pins: uart2-pins { 232 groups = "uart2"; 233 function = "uart"; 234 }; 235 }; 236 237 pinctrl_sb: pinctrl@18800 { 238 compatible = "marvell,armada3710-sb-pinctrl", 239 "syscon", "simple-mfd"; 240 reg = <0x18800 0x100>, <0x18C00 0x20>; 241 gpiosb: gpio { 242 #gpio-cells = <2>; 243 gpio-ranges = <&pinctrl_sb 0 0 30>; 244 gpio-controller; 245 interrupts = 246 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 251 }; 252 253 rgmii_pins: mii-pins { 254 groups = "rgmii"; 255 function = "mii"; 256 }; 257 258 }; 259 260 eth0: ethernet@30000 { 261 compatible = "marvell,armada-3700-neta"; 262 reg = <0x30000 0x4000>; 263 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&sb_periph_clk 8>; 265 status = "disabled"; 266 }; 267 268 mdio: mdio@32004 { 269 #address-cells = <1>; 270 #size-cells = <0>; 271 compatible = "marvell,orion-mdio"; 272 reg = <0x32004 0x4>; 273 }; 274 275 eth1: ethernet@40000 { 276 compatible = "marvell,armada-3700-neta"; 277 reg = <0x40000 0x4000>; 278 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&sb_periph_clk 7>; 280 status = "disabled"; 281 }; 282 283 usb3: usb@58000 { 284 compatible = "marvell,armada3700-xhci", 285 "generic-xhci"; 286 reg = <0x58000 0x4000>; 287 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&sb_periph_clk 12>; 289 status = "disabled"; 290 }; 291 292 usb2: usb@5e000 { 293 compatible = "marvell,armada-3700-ehci"; 294 reg = <0x5e000 0x2000>; 295 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 296 status = "disabled"; 297 }; 298 299 xor@60900 { 300 compatible = "marvell,armada-3700-xor"; 301 reg = <0x60900 0x100>, 302 <0x60b00 0x100>; 303 304 xor10 { 305 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 306 }; 307 xor11 { 308 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 309 }; 310 }; 311 312 sdhci1: sdhci@d0000 { 313 compatible = "marvell,armada-3700-sdhci", 314 "marvell,sdhci-xenon"; 315 reg = <0xd0000 0x300>, 316 <0x1e808 0x4>; 317 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&nb_periph_clk 0>; 319 clock-names = "core"; 320 status = "disabled"; 321 }; 322 323 sdhci0: sdhci@d8000 { 324 compatible = "marvell,armada-3700-sdhci", 325 "marvell,sdhci-xenon"; 326 reg = <0xd8000 0x300>, 327 <0x17808 0x4>; 328 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&nb_periph_clk 0>; 330 clock-names = "core"; 331 status = "disabled"; 332 }; 333 334 sata: sata@e0000 { 335 compatible = "marvell,armada-3700-ahci"; 336 reg = <0xe0000 0x2000>; 337 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 338 status = "disabled"; 339 }; 340 341 gic: interrupt-controller@1d00000 { 342 compatible = "arm,gic-v3"; 343 #interrupt-cells = <3>; 344 interrupt-controller; 345 reg = <0x1d00000 0x10000>, /* GICD */ 346 <0x1d40000 0x40000>, /* GICR */ 347 <0x1d80000 0x2000>, /* GICC */ 348 <0x1d90000 0x2000>, /* GICH */ 349 <0x1da0000 0x20000>; /* GICV */ 350 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 351 }; 352 }; 353 354 pcie0: pcie@d0070000 { 355 compatible = "marvell,armada-3700-pcie"; 356 device_type = "pci"; 357 status = "disabled"; 358 reg = <0 0xd0070000 0 0x20000>; 359 #address-cells = <3>; 360 #size-cells = <2>; 361 bus-range = <0x00 0xff>; 362 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 363 #interrupt-cells = <1>; 364 msi-parent = <&pcie0>; 365 msi-controller; 366 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 367 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 368 interrupt-map-mask = <0 0 0 7>; 369 interrupt-map = <0 0 0 1 &pcie_intc 0>, 370 <0 0 0 2 &pcie_intc 1>, 371 <0 0 0 3 &pcie_intc 2>, 372 <0 0 0 4 &pcie_intc 3>; 373 pcie_intc: interrupt-controller { 374 interrupt-controller; 375 #interrupt-cells = <1>; 376 }; 377 }; 378 }; 379}; 380