1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 *
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14	model = "Marvell Armada 37xx SoC";
15	compatible = "marvell,armada3700";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		serial0 = &uart0;
22		serial1 = &uart1;
23	};
24
25	reserved-memory {
26		#address-cells = <2>;
27		#size-cells = <2>;
28		ranges;
29
30		/*
31		 * The PSCI firmware region depicted below is the default one
32		 * and should be updated by the bootloader.
33		 */
34		psci-area@4000000 {
35			reg = <0 0x4000000 0 0x200000>;
36			no-map;
37		};
38	};
39
40	cpus {
41		#address-cells = <1>;
42		#size-cells = <0>;
43		cpu0: cpu@0 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53";
46			reg = <0>;
47			clocks = <&nb_periph_clk 16>;
48			enable-method = "psci";
49		};
50	};
51
52	psci {
53		compatible = "arm,psci-0.2";
54		method = "smc";
55	};
56
57	timer {
58		compatible = "arm,armv8-timer";
59		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
60			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
61			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
62			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
63	};
64
65	pmu {
66		compatible = "arm,armv8-pmuv3";
67		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
68	};
69
70	soc {
71		compatible = "simple-bus";
72		#address-cells = <2>;
73		#size-cells = <2>;
74		ranges;
75
76		internal-regs@d0000000 {
77			#address-cells = <1>;
78			#size-cells = <1>;
79			compatible = "simple-bus";
80			/* 32M internal register @ 0xd000_0000 */
81			ranges = <0x0 0x0 0xd0000000 0x2000000>;
82
83			wdt: watchdog@8300 {
84				compatible = "marvell,armada-3700-wdt";
85				reg = <0x8300 0x40>;
86				marvell,system-controller = <&cpu_misc>;
87				clocks = <&xtalclk>;
88			};
89
90			cpu_misc: system-controller@d000 {
91				compatible = "marvell,armada-3700-cpu-misc",
92					     "syscon";
93				reg = <0xd000 0x1000>;
94			};
95
96			spi0: spi@10600 {
97				compatible = "marvell,armada-3700-spi";
98				#address-cells = <1>;
99				#size-cells = <0>;
100				reg = <0x10600 0xA00>;
101				clocks = <&nb_periph_clk 7>;
102				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
103				num-cs = <4>;
104				status = "disabled";
105			};
106
107			i2c0: i2c@11000 {
108				compatible = "marvell,armada-3700-i2c";
109				reg = <0x11000 0x24>;
110				#address-cells = <1>;
111				#size-cells = <0>;
112				clocks = <&nb_periph_clk 10>;
113				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
114				mrvl,i2c-fast-mode;
115				status = "disabled";
116			};
117
118			i2c1: i2c@11080 {
119				compatible = "marvell,armada-3700-i2c";
120				reg = <0x11080 0x24>;
121				#address-cells = <1>;
122				#size-cells = <0>;
123				clocks = <&nb_periph_clk 9>;
124				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
125				mrvl,i2c-fast-mode;
126				status = "disabled";
127			};
128
129			avs: avs@11500 {
130				compatible = "marvell,armada-3700-avs",
131					     "syscon";
132				reg = <0x11500 0x40>;
133			};
134
135			uart0: serial@12000 {
136				compatible = "marvell,armada-3700-uart";
137				reg = <0x12000 0x18>;
138				clocks = <&xtalclk>;
139				interrupts =
140				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
141				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
142				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
143				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
144				status = "disabled";
145			};
146
147			uart1: serial@12200 {
148				compatible = "marvell,armada-3700-uart-ext";
149				reg = <0x12200 0x30>;
150				clocks = <&xtalclk>;
151				interrupts =
152				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
153				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
154				interrupt-names = "uart-tx", "uart-rx";
155				status = "disabled";
156			};
157
158			nb_periph_clk: nb-periph-clk@13000 {
159				compatible = "marvell,armada-3700-periph-clock-nb",
160					     "syscon";
161				reg = <0x13000 0x100>;
162				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
163				<&tbg 3>, <&xtalclk>;
164				#clock-cells = <1>;
165			};
166
167			sb_periph_clk: sb-periph-clk@18000 {
168				compatible = "marvell,armada-3700-periph-clock-sb";
169				reg = <0x18000 0x100>;
170				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
171				<&tbg 3>, <&xtalclk>;
172				#clock-cells = <1>;
173			};
174
175			tbg: tbg@13200 {
176				compatible = "marvell,armada-3700-tbg-clock";
177				reg = <0x13200 0x100>;
178				clocks = <&xtalclk>;
179				#clock-cells = <1>;
180			};
181
182			pinctrl_nb: pinctrl@13800 {
183				compatible = "marvell,armada3710-nb-pinctrl",
184					     "syscon", "simple-mfd";
185				reg = <0x13800 0x100>, <0x13C00 0x20>;
186				/* MPP1[19:0] */
187				gpionb: gpio {
188					#gpio-cells = <2>;
189					gpio-ranges = <&pinctrl_nb 0 0 36>;
190					gpio-controller;
191					interrupt-controller;
192					#interrupt-cells = <2>;
193					interrupts =
194					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
195					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
196					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
197					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
198					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
199					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
200					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
201					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
202					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
203					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
204					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
205					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
206				};
207
208				xtalclk: xtal-clk {
209					compatible = "marvell,armada-3700-xtal-clock";
210					clock-output-names = "xtal";
211					#clock-cells = <0>;
212				};
213
214				spi_quad_pins: spi-quad-pins {
215					groups = "spi_quad";
216					function = "spi";
217				};
218
219				spi_cs1_pins: spi-cs1-pins {
220					groups = "spi_cs1";
221					function = "spi";
222				};
223
224				i2c1_pins: i2c1-pins {
225					groups = "i2c1";
226					function = "i2c";
227				};
228
229				i2c2_pins: i2c2-pins {
230					groups = "i2c2";
231					function = "i2c";
232				};
233
234				uart1_pins: uart1-pins {
235					groups = "uart1";
236					function = "uart";
237				};
238
239				uart2_pins: uart2-pins {
240					groups = "uart2";
241					function = "uart";
242				};
243
244				mmc_pins: mmc-pins {
245					groups = "emmc_nb";
246					function = "emmc";
247				};
248			};
249
250			nb_pm: syscon@14000 {
251				compatible = "marvell,armada-3700-nb-pm",
252					     "syscon";
253				reg = <0x14000 0x60>;
254			};
255
256			comphy: phy@18300 {
257				compatible = "marvell,comphy-a3700";
258				reg = <0x18300 0x300>,
259				      <0x1F000 0x400>,
260				      <0x5C000 0x400>,
261				      <0xe0178 0x8>;
262				reg-names = "comphy",
263					    "lane1_pcie_gbe",
264					    "lane0_usb3_gbe",
265					    "lane2_sata_usb3";
266				#address-cells = <1>;
267				#size-cells = <0>;
268
269				comphy0: phy@0 {
270					reg = <0>;
271					#phy-cells = <1>;
272				};
273
274				comphy1: phy@1 {
275					reg = <1>;
276					#phy-cells = <1>;
277				};
278
279				comphy2: phy@2 {
280					reg = <2>;
281					#phy-cells = <1>;
282				};
283			};
284
285			pinctrl_sb: pinctrl@18800 {
286				compatible = "marvell,armada3710-sb-pinctrl",
287					     "syscon", "simple-mfd";
288				reg = <0x18800 0x100>, <0x18C00 0x20>;
289				/* MPP2[23:0] */
290				gpiosb: gpio {
291					#gpio-cells = <2>;
292					gpio-ranges = <&pinctrl_sb 0 0 30>;
293					gpio-controller;
294					interrupt-controller;
295					#interrupt-cells = <2>;
296					interrupts =
297					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
298					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
299					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
300					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
301					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
302				};
303
304				rgmii_pins: mii-pins {
305					groups = "rgmii";
306					function = "mii";
307				};
308
309				smi_pins: smi-pins {
310					groups = "smi";
311					function = "smi";
312				};
313
314				sdio_pins: sdio-pins {
315					groups = "sdio_sb";
316					function = "sdio";
317				};
318
319				pcie_reset_pins: pcie-reset-pins {
320					groups = "pcie1"; /* this actually controls "pcie1_reset" */
321					function = "gpio";
322				};
323
324				pcie_clkreq_pins: pcie-clkreq-pins {
325					groups = "pcie1_clkreq";
326					function = "pcie";
327				};
328			};
329
330			eth0: ethernet@30000 {
331				   compatible = "marvell,armada-3700-neta";
332				   reg = <0x30000 0x4000>;
333				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
334				   clocks = <&sb_periph_clk 8>;
335				   status = "disabled";
336			};
337
338			mdio: mdio@32004 {
339				#address-cells = <1>;
340				#size-cells = <0>;
341				compatible = "marvell,orion-mdio";
342				reg = <0x32004 0x4>;
343			};
344
345			eth1: ethernet@40000 {
346				compatible = "marvell,armada-3700-neta";
347				reg = <0x40000 0x4000>;
348				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
349				clocks = <&sb_periph_clk 7>;
350				status = "disabled";
351			};
352
353			usb3: usb@58000 {
354				compatible = "marvell,armada3700-xhci",
355				"generic-xhci";
356				reg = <0x58000 0x4000>;
357				marvell,usb-misc-reg = <&usb32_syscon>;
358				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
359				clocks = <&sb_periph_clk 12>;
360				phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
361				phy-names = "usb3-phy", "usb2-utmi-otg-phy";
362				status = "disabled";
363			};
364
365			usb2_utmi_otg_phy: phy@5d000 {
366				compatible = "marvell,a3700-utmi-otg-phy";
367				reg = <0x5d000 0x800>;
368				marvell,usb-misc-reg = <&usb32_syscon>;
369				#phy-cells = <0>;
370			};
371
372			usb32_syscon: system-controller@5d800 {
373				compatible = "marvell,armada-3700-usb2-host-device-misc",
374				"syscon";
375				reg = <0x5d800 0x800>;
376			};
377
378			usb2: usb@5e000 {
379				compatible = "marvell,armada-3700-ehci";
380				reg = <0x5e000 0x1000>;
381				marvell,usb-misc-reg = <&usb2_syscon>;
382				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
383				phys = <&usb2_utmi_host_phy>;
384				phy-names = "usb2-utmi-host-phy";
385				status = "disabled";
386			};
387
388			usb2_utmi_host_phy: phy@5f000 {
389				compatible = "marvell,a3700-utmi-host-phy";
390				reg = <0x5f000 0x800>;
391				marvell,usb-misc-reg = <&usb2_syscon>;
392				#phy-cells = <0>;
393			};
394
395			usb2_syscon: system-controller@5f800 {
396				compatible = "marvell,armada-3700-usb2-host-misc",
397				"syscon";
398				reg = <0x5f800 0x800>;
399			};
400
401			xor@60900 {
402				compatible = "marvell,armada-3700-xor";
403				reg = <0x60900 0x100>,
404				      <0x60b00 0x100>;
405
406				xor10 {
407					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
408				};
409				xor11 {
410					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
411				};
412			};
413
414			crypto: crypto@90000 {
415				compatible = "inside-secure,safexcel-eip97ies";
416				reg = <0x90000 0x20000>;
417				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
418					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
419					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
420					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
421					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
422					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
423				interrupt-names = "mem", "ring0", "ring1",
424						  "ring2", "ring3", "eip";
425				clocks = <&nb_periph_clk 15>;
426			};
427
428			rwtm: mailbox@b0000 {
429				compatible = "marvell,armada-3700-rwtm-mailbox";
430				reg = <0xb0000 0x100>;
431				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
432				#mbox-cells = <1>;
433			};
434
435			sdhci1: sdhci@d0000 {
436				compatible = "marvell,armada-3700-sdhci",
437					     "marvell,sdhci-xenon";
438				reg = <0xd0000 0x300>,
439				      <0x1e808 0x4>;
440				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
441				clocks = <&nb_periph_clk 0>;
442				clock-names = "core";
443				status = "disabled";
444			};
445
446			sdhci0: sdhci@d8000 {
447				compatible = "marvell,armada-3700-sdhci",
448					     "marvell,sdhci-xenon";
449				reg = <0xd8000 0x300>,
450				      <0x17808 0x4>;
451				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
452				clocks = <&nb_periph_clk 0>;
453				clock-names = "core";
454				status = "disabled";
455			};
456
457			sata: sata@e0000 {
458				compatible = "marvell,armada-3700-ahci";
459				reg = <0xe0000 0x178>;
460				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
461				clocks = <&nb_periph_clk 1>;
462				phys = <&comphy2 0>;
463				phy-names = "sata-phy";
464				status = "disabled";
465			};
466
467			gic: interrupt-controller@1d00000 {
468				compatible = "arm,gic-v3";
469				#interrupt-cells = <3>;
470				interrupt-controller;
471				reg = <0x1d00000 0x10000>, /* GICD */
472				      <0x1d40000 0x40000>, /* GICR */
473				      <0x1d80000 0x2000>,  /* GICC */
474				      <0x1d90000 0x2000>,  /* GICH */
475				      <0x1da0000 0x20000>; /* GICV */
476				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
477			};
478		};
479
480		pcie0: pcie@d0070000 {
481			compatible = "marvell,armada-3700-pcie";
482			device_type = "pci";
483			status = "disabled";
484			reg = <0 0xd0070000 0 0x20000>;
485			#address-cells = <3>;
486			#size-cells = <2>;
487			bus-range = <0x00 0xff>;
488			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
489			#interrupt-cells = <1>;
490			msi-parent = <&pcie0>;
491			msi-controller;
492			/*
493			 * The 128 MiB address range [0xe8000000-0xf0000000] is
494			 * dedicated for PCIe and can be assigned to 8 windows
495			 * with size a power of two. Use one 64 KiB window for
496			 * IO at the end and the remaining seven windows
497			 * (totaling 127 MiB) for MEM.
498			 */
499			ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */
500				  0x81000000 0 0xefff0000   0 0xefff0000   0 0x00010000>; /* Port 0 IO */
501			interrupt-map-mask = <0 0 0 7>;
502			interrupt-map = <0 0 0 1 &pcie_intc 0>,
503					<0 0 0 2 &pcie_intc 1>,
504					<0 0 0 3 &pcie_intc 2>,
505					<0 0 0 4 &pcie_intc 3>;
506			max-link-speed = <2>;
507			phys = <&comphy1 0>;
508			pcie_intc: interrupt-controller {
509				interrupt-controller;
510				#interrupt-cells = <1>;
511			};
512		};
513	};
514
515	firmware {
516		armada-3700-rwtm {
517			compatible = "marvell,armada-3700-rwtm-firmware";
518			mboxes = <&rwtm 0>;
519			status = "okay";
520		};
521	};
522};
523