1/* 2 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3 * 4 * Copyright (C) 2016 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49/ { 50 model = "Marvell Armada 37xx SoC"; 51 compatible = "marvell,armada3700"; 52 interrupt-parent = <&gic>; 53 #address-cells = <2>; 54 #size-cells = <2>; 55 56 aliases { 57 serial0 = &uart0; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53", "arm,armv8"; 66 reg = <0>; 67 enable-method = "psci"; 68 }; 69 }; 70 71 psci { 72 compatible = "arm,psci-0.2"; 73 method = "smc"; 74 }; 75 76 timer { 77 compatible = "arm,armv8-timer"; 78 interrupts = <GIC_PPI 13 79 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 80 <GIC_PPI 14 81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 11 83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84 <GIC_PPI 10 85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 86 }; 87 88 soc { 89 compatible = "simple-bus"; 90 #address-cells = <2>; 91 #size-cells = <2>; 92 ranges; 93 94 internal-regs@d0000000 { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 compatible = "simple-bus"; 98 /* 32M internal register @ 0xd000_0000 */ 99 ranges = <0x0 0x0 0xd0000000 0x2000000>; 100 101 spi0: spi@10600 { 102 compatible = "marvell,armada-3700-spi"; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 reg = <0x10600 0xA00>; 106 clocks = <&nb_periph_clk 7>; 107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 108 num-cs = <4>; 109 status = "disabled"; 110 }; 111 112 i2c0: i2c@11000 { 113 compatible = "marvell,armada-3700-i2c"; 114 reg = <0x11000 0x24>; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 clocks = <&nb_periph_clk 10>; 118 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 119 mrvl,i2c-fast-mode; 120 status = "disabled"; 121 }; 122 123 i2c1: i2c@11080 { 124 compatible = "marvell,armada-3700-i2c"; 125 reg = <0x11080 0x24>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&nb_periph_clk 9>; 129 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 130 mrvl,i2c-fast-mode; 131 status = "disabled"; 132 }; 133 134 uart0: serial@12000 { 135 compatible = "marvell,armada-3700-uart"; 136 reg = <0x12000 0x400>; 137 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 138 status = "disabled"; 139 }; 140 141 nb_periph_clk: nb-periph-clk@13000 { 142 compatible = "marvell,armada-3700-periph-clock-nb"; 143 reg = <0x13000 0x100>; 144 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 145 <&tbg 3>, <&xtalclk>; 146 #clock-cells = <1>; 147 }; 148 149 sb_periph_clk: sb-periph-clk@18000 { 150 compatible = "marvell,armada-3700-periph-clock-sb"; 151 reg = <0x18000 0x100>; 152 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 153 <&tbg 3>, <&xtalclk>; 154 #clock-cells = <1>; 155 }; 156 157 tbg: tbg@13200 { 158 compatible = "marvell,armada-3700-tbg-clock"; 159 reg = <0x13200 0x100>; 160 clocks = <&xtalclk>; 161 #clock-cells = <1>; 162 }; 163 164 gpio1: gpio@13800 { 165 compatible = "marvell,mvebu-gpio-3700", 166 "syscon", "simple-mfd"; 167 reg = <0x13800 0x500>; 168 169 xtalclk: xtal-clk { 170 compatible = "marvell,armada-3700-xtal-clock"; 171 clock-output-names = "xtal"; 172 #clock-cells = <0>; 173 }; 174 }; 175 176 eth0: ethernet@30000 { 177 compatible = "marvell,armada-3700-neta"; 178 reg = <0x30000 0x4000>; 179 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&sb_periph_clk 8>; 181 status = "disabled"; 182 }; 183 184 mdio: mdio@32004 { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 compatible = "marvell,orion-mdio"; 188 reg = <0x32004 0x4>; 189 }; 190 191 eth1: ethernet@40000 { 192 compatible = "marvell,armada-3700-neta"; 193 reg = <0x40000 0x4000>; 194 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&sb_periph_clk 7>; 196 status = "disabled"; 197 }; 198 199 usb3: usb@58000 { 200 compatible = "marvell,armada3700-xhci", 201 "generic-xhci"; 202 reg = <0x58000 0x4000>; 203 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&sb_periph_clk 12>; 205 status = "disabled"; 206 }; 207 208 usb2: usb@5e000 { 209 compatible = "marvell,armada-3700-ehci"; 210 reg = <0x5e000 0x2000>; 211 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 212 status = "disabled"; 213 }; 214 215 xor@60900 { 216 compatible = "marvell,armada-3700-xor"; 217 reg = <0x60900 0x100 218 0x60b00 0x100>; 219 220 xor10 { 221 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 222 }; 223 xor11 { 224 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 225 }; 226 }; 227 228 sdhci0: sdhci@d8000 { 229 compatible = "marvell,armada-3700-sdhci", 230 "marvell,sdhci-xenon"; 231 reg = <0xd8000 0x300 232 0x17808 0x4>; 233 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&nb_periph_clk 0>; 235 clock-names = "core"; 236 status = "disabled"; 237 }; 238 239 sata: sata@e0000 { 240 compatible = "marvell,armada-3700-ahci"; 241 reg = <0xe0000 0x2000>; 242 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 243 status = "disabled"; 244 }; 245 246 gic: interrupt-controller@1d00000 { 247 compatible = "arm,gic-v3"; 248 #interrupt-cells = <3>; 249 interrupt-controller; 250 reg = <0x1d00000 0x10000>, /* GICD */ 251 <0x1d40000 0x40000>; /* GICR */ 252 }; 253 }; 254 255 pcie0: pcie@d0070000 { 256 compatible = "marvell,armada-3700-pcie"; 257 device_type = "pci"; 258 status = "disabled"; 259 reg = <0 0xd0070000 0 0x20000>; 260 #address-cells = <3>; 261 #size-cells = <2>; 262 bus-range = <0x00 0xff>; 263 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 264 #interrupt-cells = <1>; 265 msi-parent = <&pcie0>; 266 msi-controller; 267 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 268 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 269 interrupt-map-mask = <0 0 0 7>; 270 interrupt-map = <0 0 0 1 &pcie_intc 0>, 271 <0 0 0 2 &pcie_intc 1>, 272 <0 0 0 3 &pcie_intc 2>, 273 <0 0 0 4 &pcie_intc 3>; 274 pcie_intc: interrupt-controller { 275 interrupt-controller; 276 #interrupt-cells = <1>; 277 }; 278 }; 279 }; 280}; 281