1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behún <kabel@kernel.org>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	memory@0 {
29		device_type = "memory";
30		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
31	};
32
33	leds {
34		compatible = "gpio-leds";
35		red {
36			label = "mox:red:activity";
37			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
38			linux,default-trigger = "default-on";
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		reset {
46			label = "reset";
47			linux,code = <KEY_RESTART>;
48			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
49			debounce-interval = <60>;
50		};
51	};
52
53	exp_usb3_vbus: usb3-vbus {
54		compatible = "regulator-fixed";
55		regulator-name = "usb3-vbus";
56		regulator-min-microvolt = <5000000>;
57		regulator-max-microvolt = <5000000>;
58		enable-active-high;
59		regulator-always-on;
60		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
61	};
62
63	vsdc_reg: vsdc-reg {
64		compatible = "regulator-gpio";
65		regulator-name = "vsdc";
66		regulator-min-microvolt = <1800000>;
67		regulator-max-microvolt = <3300000>;
68		regulator-boot-on;
69
70		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
71		gpios-states = <0>;
72		states = <1800000 0x1
73			  3300000 0x0>;
74		enable-active-high;
75	};
76
77	vsdio_reg: vsdio-reg {
78		compatible = "regulator-gpio";
79		regulator-name = "vsdio";
80		regulator-min-microvolt = <1800000>;
81		regulator-max-microvolt = <3300000>;
82		regulator-boot-on;
83
84		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
85		gpios-states = <0>;
86		states = <1800000 0x1
87			  3300000 0x0>;
88		enable-active-high;
89	};
90
91	sdhci1_pwrseq: sdhci1-pwrseq {
92		compatible = "mmc-pwrseq-simple";
93		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
94		status = "okay";
95	};
96
97	sfp: sfp {
98		compatible = "sff,sfp";
99		i2c-bus = <&i2c0>;
100		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
101		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
102		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
103		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
104		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
105		maximum-power-milliwatt = <3000>;
106
107		/* enabled by U-Boot if SFP module is present */
108		status = "disabled";
109	};
110
111	firmware {
112		armada-3700-rwtm {
113			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
114		};
115	};
116};
117
118&i2c0 {
119	pinctrl-names = "default";
120	pinctrl-0 = <&i2c1_pins>;
121	clock-frequency = <100000>;
122	status = "okay";
123
124	rtc@6f {
125		compatible = "microchip,mcp7940x";
126		reg = <0x6f>;
127	};
128};
129
130&pcie0 {
131	pinctrl-names = "default";
132	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
133	status = "okay";
134	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
135
136	/* enabled by U-Boot if PCIe module is present */
137	status = "disabled";
138};
139
140&uart0 {
141	status = "okay";
142};
143
144&eth0 {
145	pinctrl-names = "default";
146	pinctrl-0 = <&rgmii_pins>;
147	phy-mode = "rgmii-id";
148	phy-handle = <&phy1>;
149	status = "okay";
150};
151
152&eth1 {
153	phy-mode = "2500base-x";
154	managed = "in-band-status";
155	phys = <&comphy0 1>;
156};
157
158&sdhci0 {
159	wp-inverted;
160	bus-width = <4>;
161	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
162	vqmmc-supply = <&vsdc_reg>;
163	marvell,pad-type = "sd";
164	status = "okay";
165};
166
167&sdhci1 {
168	pinctrl-names = "default";
169	pinctrl-0 = <&sdio_pins>;
170	non-removable;
171	bus-width = <4>;
172	marvell,pad-type = "sd";
173	vqmmc-supply = <&vsdio_reg>;
174	mmc-pwrseq = <&sdhci1_pwrseq>;
175	/* forbid SDR104 for FCC purposes */
176	sdhci-caps-mask = <0x2 0x0>;
177	status = "okay";
178};
179
180&spi0 {
181	status = "okay";
182	pinctrl-names = "default";
183	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
184	assigned-clocks = <&nb_periph_clk 7>;
185	assigned-clock-parents = <&tbg 1>;
186	assigned-clock-rates = <20000000>;
187
188	spi-flash@0 {
189		#address-cells = <1>;
190		#size-cells = <1>;
191		compatible = "jedec,spi-nor";
192		reg = <0>;
193		spi-max-frequency = <20000000>;
194
195		partitions {
196			compatible = "fixed-partitions";
197			#address-cells = <1>;
198			#size-cells = <1>;
199
200			partition@0 {
201				label = "secure-firmware";
202				reg = <0x0 0x20000>;
203			};
204
205			partition@20000 {
206				label = "a53-firmware";
207				reg = <0x20000 0x160000>;
208			};
209
210			partition@180000 {
211				label = "u-boot-env";
212				reg = <0x180000 0x10000>;
213			};
214
215			partition@190000 {
216				label = "Rescue system";
217				reg = <0x190000 0x660000>;
218			};
219
220			partition@7f0000 {
221				label = "dtb";
222				reg = <0x7f0000 0x10000>;
223			};
224		};
225	};
226
227	moxtet: moxtet@1 {
228		#address-cells = <1>;
229		#size-cells = <0>;
230		compatible = "cznic,moxtet";
231		reg = <1>;
232		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
233		spi-max-frequency = <10000000>;
234		spi-cpol;
235		spi-cpha;
236		interrupt-controller;
237		#interrupt-cells = <1>;
238		interrupt-parent = <&gpiosb>;
239		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
240		status = "okay";
241
242		moxtet_sfp: gpio@0 {
243			compatible = "cznic,moxtet-gpio";
244			gpio-controller;
245			#gpio-cells = <2>;
246			reg = <0>;
247			status = "disabled";
248		};
249	};
250};
251
252&usb2 {
253	status = "okay";
254};
255
256&comphy2 {
257	connector {
258		compatible = "usb-a-connector";
259		phy-supply = <&exp_usb3_vbus>;
260	};
261};
262
263&usb3 {
264	status = "okay";
265	phys = <&comphy2 0>;
266};
267
268&mdio {
269	pinctrl-names = "default";
270	pinctrl-0 = <&smi_pins>;
271	status = "okay";
272
273	phy1: ethernet-phy@1 {
274		reg = <1>;
275	};
276
277	/* switch nodes are enabled by U-Boot if modules are present */
278	switch0@10 {
279		compatible = "marvell,mv88e6190";
280		reg = <0x10 0>;
281		dsa,member = <0 0>;
282		interrupt-parent = <&moxtet>;
283		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
284		status = "disabled";
285
286		mdio {
287			#address-cells = <1>;
288			#size-cells = <0>;
289
290			switch0phy1: switch0phy1@1 {
291				reg = <0x1>;
292			};
293
294			switch0phy2: switch0phy2@2 {
295				reg = <0x2>;
296			};
297
298			switch0phy3: switch0phy3@3 {
299				reg = <0x3>;
300			};
301
302			switch0phy4: switch0phy4@4 {
303				reg = <0x4>;
304			};
305
306			switch0phy5: switch0phy5@5 {
307				reg = <0x5>;
308			};
309
310			switch0phy6: switch0phy6@6 {
311				reg = <0x6>;
312			};
313
314			switch0phy7: switch0phy7@7 {
315				reg = <0x7>;
316			};
317
318			switch0phy8: switch0phy8@8 {
319				reg = <0x8>;
320			};
321		};
322
323		ports {
324			#address-cells = <1>;
325			#size-cells = <0>;
326
327			port@1 {
328				reg = <0x1>;
329				label = "lan1";
330				phy-handle = <&switch0phy1>;
331			};
332
333			port@2 {
334				reg = <0x2>;
335				label = "lan2";
336				phy-handle = <&switch0phy2>;
337			};
338
339			port@3 {
340				reg = <0x3>;
341				label = "lan3";
342				phy-handle = <&switch0phy3>;
343			};
344
345			port@4 {
346				reg = <0x4>;
347				label = "lan4";
348				phy-handle = <&switch0phy4>;
349			};
350
351			port@5 {
352				reg = <0x5>;
353				label = "lan5";
354				phy-handle = <&switch0phy5>;
355			};
356
357			port@6 {
358				reg = <0x6>;
359				label = "lan6";
360				phy-handle = <&switch0phy6>;
361			};
362
363			port@7 {
364				reg = <0x7>;
365				label = "lan7";
366				phy-handle = <&switch0phy7>;
367			};
368
369			port@8 {
370				reg = <0x8>;
371				label = "lan8";
372				phy-handle = <&switch0phy8>;
373			};
374
375			port@9 {
376				reg = <0x9>;
377				label = "cpu";
378				ethernet = <&eth1>;
379				phy-mode = "2500base-x";
380				managed = "in-band-status";
381			};
382
383			switch0port10: port@a {
384				reg = <0xa>;
385				label = "dsa";
386				phy-mode = "2500base-x";
387				managed = "in-band-status";
388				link = <&switch1port9 &switch2port9>;
389				status = "disabled";
390			};
391
392			port-sfp@a {
393				reg = <0xa>;
394				label = "sfp";
395				sfp = <&sfp>;
396				phy-mode = "sgmii";
397				managed = "in-band-status";
398				status = "disabled";
399			};
400		};
401	};
402
403	switch0@2 {
404		compatible = "marvell,mv88e6085";
405		reg = <0x2 0>;
406		dsa,member = <0 0>;
407		interrupt-parent = <&moxtet>;
408		interrupts = <MOXTET_IRQ_TOPAZ>;
409		status = "disabled";
410
411		mdio {
412			#address-cells = <1>;
413			#size-cells = <0>;
414
415			switch0phy1_topaz: switch0phy1@11 {
416				reg = <0x11>;
417			};
418
419			switch0phy2_topaz: switch0phy2@12 {
420				reg = <0x12>;
421			};
422
423			switch0phy3_topaz: switch0phy3@13 {
424				reg = <0x13>;
425			};
426
427			switch0phy4_topaz: switch0phy4@14 {
428				reg = <0x14>;
429			};
430		};
431
432		ports {
433			#address-cells = <1>;
434			#size-cells = <0>;
435
436			port@1 {
437				reg = <0x1>;
438				label = "lan1";
439				phy-handle = <&switch0phy1_topaz>;
440			};
441
442			port@2 {
443				reg = <0x2>;
444				label = "lan2";
445				phy-handle = <&switch0phy2_topaz>;
446			};
447
448			port@3 {
449				reg = <0x3>;
450				label = "lan3";
451				phy-handle = <&switch0phy3_topaz>;
452			};
453
454			port@4 {
455				reg = <0x4>;
456				label = "lan4";
457				phy-handle = <&switch0phy4_topaz>;
458			};
459
460			port@5 {
461				reg = <0x5>;
462				label = "cpu";
463				phy-mode = "2500base-x";
464				managed = "in-band-status";
465				ethernet = <&eth1>;
466			};
467		};
468	};
469
470	switch1@11 {
471		compatible = "marvell,mv88e6190";
472		reg = <0x11 0>;
473		dsa,member = <0 1>;
474		interrupt-parent = <&moxtet>;
475		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
476		status = "disabled";
477
478		mdio {
479			#address-cells = <1>;
480			#size-cells = <0>;
481
482			switch1phy1: switch1phy1@1 {
483				reg = <0x1>;
484			};
485
486			switch1phy2: switch1phy2@2 {
487				reg = <0x2>;
488			};
489
490			switch1phy3: switch1phy3@3 {
491				reg = <0x3>;
492			};
493
494			switch1phy4: switch1phy4@4 {
495				reg = <0x4>;
496			};
497
498			switch1phy5: switch1phy5@5 {
499				reg = <0x5>;
500			};
501
502			switch1phy6: switch1phy6@6 {
503				reg = <0x6>;
504			};
505
506			switch1phy7: switch1phy7@7 {
507				reg = <0x7>;
508			};
509
510			switch1phy8: switch1phy8@8 {
511				reg = <0x8>;
512			};
513		};
514
515		ports {
516			#address-cells = <1>;
517			#size-cells = <0>;
518
519			port@1 {
520				reg = <0x1>;
521				label = "lan9";
522				phy-handle = <&switch1phy1>;
523			};
524
525			port@2 {
526				reg = <0x2>;
527				label = "lan10";
528				phy-handle = <&switch1phy2>;
529			};
530
531			port@3 {
532				reg = <0x3>;
533				label = "lan11";
534				phy-handle = <&switch1phy3>;
535			};
536
537			port@4 {
538				reg = <0x4>;
539				label = "lan12";
540				phy-handle = <&switch1phy4>;
541			};
542
543			port@5 {
544				reg = <0x5>;
545				label = "lan13";
546				phy-handle = <&switch1phy5>;
547			};
548
549			port@6 {
550				reg = <0x6>;
551				label = "lan14";
552				phy-handle = <&switch1phy6>;
553			};
554
555			port@7 {
556				reg = <0x7>;
557				label = "lan15";
558				phy-handle = <&switch1phy7>;
559			};
560
561			port@8 {
562				reg = <0x8>;
563				label = "lan16";
564				phy-handle = <&switch1phy8>;
565			};
566
567			switch1port9: port@9 {
568				reg = <0x9>;
569				label = "dsa";
570				phy-mode = "2500base-x";
571				managed = "in-band-status";
572				link = <&switch0port10>;
573			};
574
575			switch1port10: port@a {
576				reg = <0xa>;
577				label = "dsa";
578				phy-mode = "2500base-x";
579				managed = "in-band-status";
580				link = <&switch2port9>;
581				status = "disabled";
582			};
583
584			port-sfp@a {
585				reg = <0xa>;
586				label = "sfp";
587				sfp = <&sfp>;
588				phy-mode = "sgmii";
589				managed = "in-band-status";
590				status = "disabled";
591			};
592		};
593	};
594
595	switch1@2 {
596		compatible = "marvell,mv88e6085";
597		reg = <0x2 0>;
598		dsa,member = <0 1>;
599		interrupt-parent = <&moxtet>;
600		interrupts = <MOXTET_IRQ_TOPAZ>;
601		status = "disabled";
602
603		mdio {
604			#address-cells = <1>;
605			#size-cells = <0>;
606
607			switch1phy1_topaz: switch1phy1@11 {
608				reg = <0x11>;
609			};
610
611			switch1phy2_topaz: switch1phy2@12 {
612				reg = <0x12>;
613			};
614
615			switch1phy3_topaz: switch1phy3@13 {
616				reg = <0x13>;
617			};
618
619			switch1phy4_topaz: switch1phy4@14 {
620				reg = <0x14>;
621			};
622		};
623
624		ports {
625			#address-cells = <1>;
626			#size-cells = <0>;
627
628			port@1 {
629				reg = <0x1>;
630				label = "lan9";
631				phy-handle = <&switch1phy1_topaz>;
632			};
633
634			port@2 {
635				reg = <0x2>;
636				label = "lan10";
637				phy-handle = <&switch1phy2_topaz>;
638			};
639
640			port@3 {
641				reg = <0x3>;
642				label = "lan11";
643				phy-handle = <&switch1phy3_topaz>;
644			};
645
646			port@4 {
647				reg = <0x4>;
648				label = "lan12";
649				phy-handle = <&switch1phy4_topaz>;
650			};
651
652			port@5 {
653				reg = <0x5>;
654				label = "dsa";
655				phy-mode = "2500base-x";
656				managed = "in-band-status";
657				link = <&switch0port10>;
658			};
659		};
660	};
661
662	switch2@12 {
663		compatible = "marvell,mv88e6190";
664		reg = <0x12 0>;
665		dsa,member = <0 2>;
666		interrupt-parent = <&moxtet>;
667		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
668		status = "disabled";
669
670		mdio {
671			#address-cells = <1>;
672			#size-cells = <0>;
673
674			switch2phy1: switch2phy1@1 {
675				reg = <0x1>;
676			};
677
678			switch2phy2: switch2phy2@2 {
679				reg = <0x2>;
680			};
681
682			switch2phy3: switch2phy3@3 {
683				reg = <0x3>;
684			};
685
686			switch2phy4: switch2phy4@4 {
687				reg = <0x4>;
688			};
689
690			switch2phy5: switch2phy5@5 {
691				reg = <0x5>;
692			};
693
694			switch2phy6: switch2phy6@6 {
695				reg = <0x6>;
696			};
697
698			switch2phy7: switch2phy7@7 {
699				reg = <0x7>;
700			};
701
702			switch2phy8: switch2phy8@8 {
703				reg = <0x8>;
704			};
705		};
706
707		ports {
708			#address-cells = <1>;
709			#size-cells = <0>;
710
711			port@1 {
712				reg = <0x1>;
713				label = "lan17";
714				phy-handle = <&switch2phy1>;
715			};
716
717			port@2 {
718				reg = <0x2>;
719				label = "lan18";
720				phy-handle = <&switch2phy2>;
721			};
722
723			port@3 {
724				reg = <0x3>;
725				label = "lan19";
726				phy-handle = <&switch2phy3>;
727			};
728
729			port@4 {
730				reg = <0x4>;
731				label = "lan20";
732				phy-handle = <&switch2phy4>;
733			};
734
735			port@5 {
736				reg = <0x5>;
737				label = "lan21";
738				phy-handle = <&switch2phy5>;
739			};
740
741			port@6 {
742				reg = <0x6>;
743				label = "lan22";
744				phy-handle = <&switch2phy6>;
745			};
746
747			port@7 {
748				reg = <0x7>;
749				label = "lan23";
750				phy-handle = <&switch2phy7>;
751			};
752
753			port@8 {
754				reg = <0x8>;
755				label = "lan24";
756				phy-handle = <&switch2phy8>;
757			};
758
759			switch2port9: port@9 {
760				reg = <0x9>;
761				label = "dsa";
762				phy-mode = "2500base-x";
763				managed = "in-band-status";
764				link = <&switch1port10 &switch0port10>;
765			};
766
767			port-sfp@a {
768				reg = <0xa>;
769				label = "sfp";
770				sfp = <&sfp>;
771				phy-mode = "sgmii";
772				managed = "in-band-status";
773				status = "disabled";
774			};
775		};
776	};
777
778	switch2@2 {
779		compatible = "marvell,mv88e6085";
780		reg = <0x2 0>;
781		dsa,member = <0 2>;
782		interrupt-parent = <&moxtet>;
783		interrupts = <MOXTET_IRQ_TOPAZ>;
784		status = "disabled";
785
786		mdio {
787			#address-cells = <1>;
788			#size-cells = <0>;
789
790			switch2phy1_topaz: switch2phy1@11 {
791				reg = <0x11>;
792			};
793
794			switch2phy2_topaz: switch2phy2@12 {
795				reg = <0x12>;
796			};
797
798			switch2phy3_topaz: switch2phy3@13 {
799				reg = <0x13>;
800			};
801
802			switch2phy4_topaz: switch2phy4@14 {
803				reg = <0x14>;
804			};
805		};
806
807		ports {
808			#address-cells = <1>;
809			#size-cells = <0>;
810
811			port@1 {
812				reg = <0x1>;
813				label = "lan17";
814				phy-handle = <&switch2phy1_topaz>;
815			};
816
817			port@2 {
818				reg = <0x2>;
819				label = "lan18";
820				phy-handle = <&switch2phy2_topaz>;
821			};
822
823			port@3 {
824				reg = <0x3>;
825				label = "lan19";
826				phy-handle = <&switch2phy3_topaz>;
827			};
828
829			port@4 {
830				reg = <0x4>;
831				label = "lan20";
832				phy-handle = <&switch2phy4_topaz>;
833			};
834
835			port@5 {
836				reg = <0x5>;
837				label = "dsa";
838				phy-mode = "2500base-x";
839				managed = "in-band-status";
840				link = <&switch1port10 &switch0port10>;
841			};
842		};
843	};
844};
845