1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behun <marek.behun@nic.cz>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	memory@0 {
29		device_type = "memory";
30		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
31	};
32
33	leds {
34		compatible = "gpio-leds";
35		red {
36			label = "mox:red:activity";
37			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
38			linux,default-trigger = "default-on";
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		reset {
46			label = "reset";
47			linux,code = <KEY_RESTART>;
48			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
49			debounce-interval = <60>;
50		};
51	};
52
53	exp_usb3_vbus: usb3-vbus {
54		compatible = "regulator-fixed";
55		regulator-name = "usb3-vbus";
56		regulator-min-microvolt = <5000000>;
57		regulator-max-microvolt = <5000000>;
58		enable-active-high;
59		regulator-always-on;
60		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
61	};
62
63	vsdc_reg: vsdc-reg {
64		compatible = "regulator-gpio";
65		regulator-name = "vsdc";
66		regulator-min-microvolt = <1800000>;
67		regulator-max-microvolt = <3300000>;
68		regulator-boot-on;
69
70		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
71		gpios-states = <0>;
72		states = <1800000 0x1
73			  3300000 0x0>;
74		enable-active-high;
75	};
76
77	vsdio_reg: vsdio-reg {
78		compatible = "regulator-gpio";
79		regulator-name = "vsdio";
80		regulator-min-microvolt = <1800000>;
81		regulator-max-microvolt = <3300000>;
82		regulator-boot-on;
83
84		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
85		gpios-states = <0>;
86		states = <1800000 0x1
87			  3300000 0x0>;
88		enable-active-high;
89	};
90
91	sdhci1_pwrseq: sdhci1-pwrseq {
92		compatible = "mmc-pwrseq-simple";
93		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
94		status = "okay";
95	};
96
97	sfp: sfp {
98		compatible = "sff,sfp+";
99		i2c-bus = <&i2c0>;
100		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
101		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
102		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
103		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
104		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
105
106		/* enabled by U-Boot if SFP module is present */
107		status = "disabled";
108	};
109
110	firmware {
111		turris-mox-rwtm {
112			compatible = "cznic,turris-mox-rwtm";
113			mboxes = <&rwtm 0>;
114			status = "okay";
115		};
116	};
117};
118
119&i2c0 {
120	pinctrl-names = "default";
121	pinctrl-0 = <&i2c1_pins>;
122	clock-frequency = <100000>;
123	status = "okay";
124
125	rtc@6f {
126		compatible = "microchip,mcp7940x";
127		reg = <0x6f>;
128	};
129};
130
131&pcie_reset_pins {
132	function = "gpio";
133};
134
135&pcie0 {
136	pinctrl-names = "default";
137	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
138	status = "okay";
139	max-link-speed = <2>;
140	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
141	phys = <&comphy1 0>;
142
143	/* enabled by U-Boot if PCIe module is present */
144	status = "disabled";
145};
146
147&uart0 {
148	status = "okay";
149};
150
151&eth0 {
152	pinctrl-names = "default";
153	pinctrl-0 = <&rgmii_pins>;
154	phy-mode = "rgmii-id";
155	phy = <&phy1>;
156	status = "okay";
157};
158
159&eth1 {
160	phy-mode = "2500base-x";
161	managed = "in-band-status";
162	phys = <&comphy0 1>;
163};
164
165&sdhci0 {
166	wp-inverted;
167	bus-width = <4>;
168	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
169	vqmmc-supply = <&vsdc_reg>;
170	marvell,pad-type = "sd";
171	status = "okay";
172};
173
174&sdhci1 {
175	pinctrl-names = "default";
176	pinctrl-0 = <&sdio_pins>;
177	non-removable;
178	bus-width = <4>;
179	marvell,pad-type = "sd";
180	vqmmc-supply = <&vsdio_reg>;
181	mmc-pwrseq = <&sdhci1_pwrseq>;
182	status = "okay";
183};
184
185&spi0 {
186	status = "okay";
187	pinctrl-names = "default";
188	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
189	assigned-clocks = <&nb_periph_clk 7>;
190	assigned-clock-parents = <&tbg 1>;
191	assigned-clock-rates = <20000000>;
192
193	spi-flash@0 {
194		#address-cells = <1>;
195		#size-cells = <1>;
196		compatible = "jedec,spi-nor";
197		reg = <0>;
198		spi-max-frequency = <20000000>;
199
200		partitions {
201			compatible = "fixed-partitions";
202			#address-cells = <1>;
203			#size-cells = <1>;
204
205			partition@0 {
206				label = "secure-firmware";
207				reg = <0x0 0x20000>;
208			};
209
210			partition@20000 {
211				label = "u-boot";
212				reg = <0x20000 0x160000>;
213			};
214
215			partition@180000 {
216				label = "u-boot-env";
217				reg = <0x180000 0x10000>;
218			};
219
220			partition@190000 {
221				label = "Rescue system";
222				reg = <0x190000 0x660000>;
223			};
224
225			partition@7f0000 {
226				label = "dtb";
227				reg = <0x7f0000 0x10000>;
228			};
229		};
230	};
231
232	moxtet: moxtet@1 {
233		#address-cells = <1>;
234		#size-cells = <0>;
235		compatible = "cznic,moxtet";
236		reg = <1>;
237		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
238		spi-max-frequency = <10000000>;
239		spi-cpol;
240		spi-cpha;
241		interrupt-controller;
242		#interrupt-cells = <1>;
243		interrupt-parent = <&gpiosb>;
244		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
245		status = "okay";
246
247		moxtet_sfp: gpio@0 {
248			compatible = "cznic,moxtet-gpio";
249			gpio-controller;
250			#gpio-cells = <2>;
251			reg = <0>;
252			status = "disabled";
253		};
254	};
255};
256
257&usb2 {
258	status = "okay";
259};
260
261&comphy2 {
262	connector {
263		compatible = "usb-a-connector";
264		phy-supply = <&exp_usb3_vbus>;
265	};
266};
267
268&usb3 {
269	status = "okay";
270	phys = <&comphy2 0>;
271};
272
273&mdio {
274	pinctrl-names = "default";
275	pinctrl-0 = <&smi_pins>;
276	status = "okay";
277
278	phy1: ethernet-phy@1 {
279		reg = <1>;
280	};
281
282	/* switch nodes are enabled by U-Boot if modules are present */
283	switch0@10 {
284		compatible = "marvell,mv88e6190";
285		reg = <0x10 0>;
286		dsa,member = <0 0>;
287		interrupt-parent = <&moxtet>;
288		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
289		status = "disabled";
290
291		mdio {
292			#address-cells = <1>;
293			#size-cells = <0>;
294
295			switch0phy1: switch0phy1@1 {
296				reg = <0x1>;
297			};
298
299			switch0phy2: switch0phy2@2 {
300				reg = <0x2>;
301			};
302
303			switch0phy3: switch0phy3@3 {
304				reg = <0x3>;
305			};
306
307			switch0phy4: switch0phy4@4 {
308				reg = <0x4>;
309			};
310
311			switch0phy5: switch0phy5@5 {
312				reg = <0x5>;
313			};
314
315			switch0phy6: switch0phy6@6 {
316				reg = <0x6>;
317			};
318
319			switch0phy7: switch0phy7@7 {
320				reg = <0x7>;
321			};
322
323			switch0phy8: switch0phy8@8 {
324				reg = <0x8>;
325			};
326		};
327
328		ports {
329			#address-cells = <1>;
330			#size-cells = <0>;
331
332			port@1 {
333				reg = <0x1>;
334				label = "lan1";
335				phy-handle = <&switch0phy1>;
336			};
337
338			port@2 {
339				reg = <0x2>;
340				label = "lan2";
341				phy-handle = <&switch0phy2>;
342			};
343
344			port@3 {
345				reg = <0x3>;
346				label = "lan3";
347				phy-handle = <&switch0phy3>;
348			};
349
350			port@4 {
351				reg = <0x4>;
352				label = "lan4";
353				phy-handle = <&switch0phy4>;
354			};
355
356			port@5 {
357				reg = <0x5>;
358				label = "lan5";
359				phy-handle = <&switch0phy5>;
360			};
361
362			port@6 {
363				reg = <0x6>;
364				label = "lan6";
365				phy-handle = <&switch0phy6>;
366			};
367
368			port@7 {
369				reg = <0x7>;
370				label = "lan7";
371				phy-handle = <&switch0phy7>;
372			};
373
374			port@8 {
375				reg = <0x8>;
376				label = "lan8";
377				phy-handle = <&switch0phy8>;
378			};
379
380			port@9 {
381				reg = <0x9>;
382				label = "cpu";
383				ethernet = <&eth1>;
384				phy-mode = "2500base-x";
385				managed = "in-band-status";
386			};
387
388			switch0port10: port@a {
389				reg = <0xa>;
390				label = "dsa";
391				phy-mode = "2500base-x";
392				managed = "in-band-status";
393				link = <&switch1port9 &switch2port9>;
394				status = "disabled";
395			};
396
397			port-sfp@a {
398				reg = <0xa>;
399				label = "sfp";
400				sfp = <&sfp>;
401				phy-mode = "sgmii";
402				managed = "in-band-status";
403				status = "disabled";
404			};
405		};
406	};
407
408	switch0@2 {
409		compatible = "marvell,mv88e6085";
410		reg = <0x2 0>;
411		dsa,member = <0 0>;
412		interrupt-parent = <&moxtet>;
413		interrupts = <MOXTET_IRQ_TOPAZ>;
414		status = "disabled";
415
416		mdio {
417			#address-cells = <1>;
418			#size-cells = <0>;
419
420			switch0phy1_topaz: switch0phy1@11 {
421				reg = <0x11>;
422			};
423
424			switch0phy2_topaz: switch0phy2@12 {
425				reg = <0x12>;
426			};
427
428			switch0phy3_topaz: switch0phy3@13 {
429				reg = <0x13>;
430			};
431
432			switch0phy4_topaz: switch0phy4@14 {
433				reg = <0x14>;
434			};
435		};
436
437		ports {
438			#address-cells = <1>;
439			#size-cells = <0>;
440
441			port@1 {
442				reg = <0x1>;
443				label = "lan1";
444				phy-handle = <&switch0phy1_topaz>;
445			};
446
447			port@2 {
448				reg = <0x2>;
449				label = "lan2";
450				phy-handle = <&switch0phy2_topaz>;
451			};
452
453			port@3 {
454				reg = <0x3>;
455				label = "lan3";
456				phy-handle = <&switch0phy3_topaz>;
457			};
458
459			port@4 {
460				reg = <0x4>;
461				label = "lan4";
462				phy-handle = <&switch0phy4_topaz>;
463			};
464
465			port@5 {
466				reg = <0x5>;
467				label = "cpu";
468				phy-mode = "2500base-x";
469				managed = "in-band-status";
470				ethernet = <&eth1>;
471			};
472		};
473	};
474
475	switch1@11 {
476		compatible = "marvell,mv88e6190";
477		reg = <0x11 0>;
478		dsa,member = <0 1>;
479		interrupt-parent = <&moxtet>;
480		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
481		status = "disabled";
482
483		mdio {
484			#address-cells = <1>;
485			#size-cells = <0>;
486
487			switch1phy1: switch1phy1@1 {
488				reg = <0x1>;
489			};
490
491			switch1phy2: switch1phy2@2 {
492				reg = <0x2>;
493			};
494
495			switch1phy3: switch1phy3@3 {
496				reg = <0x3>;
497			};
498
499			switch1phy4: switch1phy4@4 {
500				reg = <0x4>;
501			};
502
503			switch1phy5: switch1phy5@5 {
504				reg = <0x5>;
505			};
506
507			switch1phy6: switch1phy6@6 {
508				reg = <0x6>;
509			};
510
511			switch1phy7: switch1phy7@7 {
512				reg = <0x7>;
513			};
514
515			switch1phy8: switch1phy8@8 {
516				reg = <0x8>;
517			};
518		};
519
520		ports {
521			#address-cells = <1>;
522			#size-cells = <0>;
523
524			port@1 {
525				reg = <0x1>;
526				label = "lan9";
527				phy-handle = <&switch1phy1>;
528			};
529
530			port@2 {
531				reg = <0x2>;
532				label = "lan10";
533				phy-handle = <&switch1phy2>;
534			};
535
536			port@3 {
537				reg = <0x3>;
538				label = "lan11";
539				phy-handle = <&switch1phy3>;
540			};
541
542			port@4 {
543				reg = <0x4>;
544				label = "lan12";
545				phy-handle = <&switch1phy4>;
546			};
547
548			port@5 {
549				reg = <0x5>;
550				label = "lan13";
551				phy-handle = <&switch1phy5>;
552			};
553
554			port@6 {
555				reg = <0x6>;
556				label = "lan14";
557				phy-handle = <&switch1phy6>;
558			};
559
560			port@7 {
561				reg = <0x7>;
562				label = "lan15";
563				phy-handle = <&switch1phy7>;
564			};
565
566			port@8 {
567				reg = <0x8>;
568				label = "lan16";
569				phy-handle = <&switch1phy8>;
570			};
571
572			switch1port9: port@9 {
573				reg = <0x9>;
574				label = "dsa";
575				phy-mode = "2500base-x";
576				managed = "in-band-status";
577				link = <&switch0port10>;
578			};
579
580			switch1port10: port@a {
581				reg = <0xa>;
582				label = "dsa";
583				phy-mode = "2500base-x";
584				managed = "in-band-status";
585				link = <&switch2port9>;
586				status = "disabled";
587			};
588
589			port-sfp@a {
590				reg = <0xa>;
591				label = "sfp";
592				sfp = <&sfp>;
593				phy-mode = "sgmii";
594				managed = "in-band-status";
595				status = "disabled";
596			};
597		};
598	};
599
600	switch1@2 {
601		compatible = "marvell,mv88e6085";
602		reg = <0x2 0>;
603		dsa,member = <0 1>;
604		interrupt-parent = <&moxtet>;
605		interrupts = <MOXTET_IRQ_TOPAZ>;
606		status = "disabled";
607
608		mdio {
609			#address-cells = <1>;
610			#size-cells = <0>;
611
612			switch1phy1_topaz: switch1phy1@11 {
613				reg = <0x11>;
614			};
615
616			switch1phy2_topaz: switch1phy2@12 {
617				reg = <0x12>;
618			};
619
620			switch1phy3_topaz: switch1phy3@13 {
621				reg = <0x13>;
622			};
623
624			switch1phy4_topaz: switch1phy4@14 {
625				reg = <0x14>;
626			};
627		};
628
629		ports {
630			#address-cells = <1>;
631			#size-cells = <0>;
632
633			port@1 {
634				reg = <0x1>;
635				label = "lan9";
636				phy-handle = <&switch1phy1_topaz>;
637			};
638
639			port@2 {
640				reg = <0x2>;
641				label = "lan10";
642				phy-handle = <&switch1phy2_topaz>;
643			};
644
645			port@3 {
646				reg = <0x3>;
647				label = "lan11";
648				phy-handle = <&switch1phy3_topaz>;
649			};
650
651			port@4 {
652				reg = <0x4>;
653				label = "lan12";
654				phy-handle = <&switch1phy4_topaz>;
655			};
656
657			port@5 {
658				reg = <0x5>;
659				label = "dsa";
660				phy-mode = "2500base-x";
661				managed = "in-band-status";
662				link = <&switch0port10>;
663			};
664		};
665	};
666
667	switch2@12 {
668		compatible = "marvell,mv88e6190";
669		reg = <0x12 0>;
670		dsa,member = <0 2>;
671		interrupt-parent = <&moxtet>;
672		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
673		status = "disabled";
674
675		mdio {
676			#address-cells = <1>;
677			#size-cells = <0>;
678
679			switch2phy1: switch2phy1@1 {
680				reg = <0x1>;
681			};
682
683			switch2phy2: switch2phy2@2 {
684				reg = <0x2>;
685			};
686
687			switch2phy3: switch2phy3@3 {
688				reg = <0x3>;
689			};
690
691			switch2phy4: switch2phy4@4 {
692				reg = <0x4>;
693			};
694
695			switch2phy5: switch2phy5@5 {
696				reg = <0x5>;
697			};
698
699			switch2phy6: switch2phy6@6 {
700				reg = <0x6>;
701			};
702
703			switch2phy7: switch2phy7@7 {
704				reg = <0x7>;
705			};
706
707			switch2phy8: switch2phy8@8 {
708				reg = <0x8>;
709			};
710		};
711
712		ports {
713			#address-cells = <1>;
714			#size-cells = <0>;
715
716			port@1 {
717				reg = <0x1>;
718				label = "lan17";
719				phy-handle = <&switch2phy1>;
720			};
721
722			port@2 {
723				reg = <0x2>;
724				label = "lan18";
725				phy-handle = <&switch2phy2>;
726			};
727
728			port@3 {
729				reg = <0x3>;
730				label = "lan19";
731				phy-handle = <&switch2phy3>;
732			};
733
734			port@4 {
735				reg = <0x4>;
736				label = "lan20";
737				phy-handle = <&switch2phy4>;
738			};
739
740			port@5 {
741				reg = <0x5>;
742				label = "lan21";
743				phy-handle = <&switch2phy5>;
744			};
745
746			port@6 {
747				reg = <0x6>;
748				label = "lan22";
749				phy-handle = <&switch2phy6>;
750			};
751
752			port@7 {
753				reg = <0x7>;
754				label = "lan23";
755				phy-handle = <&switch2phy7>;
756			};
757
758			port@8 {
759				reg = <0x8>;
760				label = "lan24";
761				phy-handle = <&switch2phy8>;
762			};
763
764			switch2port9: port@9 {
765				reg = <0x9>;
766				label = "dsa";
767				phy-mode = "2500base-x";
768				managed = "in-band-status";
769				link = <&switch1port10 &switch0port10>;
770			};
771
772			port-sfp@a {
773				reg = <0xa>;
774				label = "sfp";
775				sfp = <&sfp>;
776				phy-mode = "sgmii";
777				managed = "in-band-status";
778				status = "disabled";
779			};
780		};
781	};
782
783	switch2@2 {
784		compatible = "marvell,mv88e6085";
785		reg = <0x2 0>;
786		dsa,member = <0 2>;
787		interrupt-parent = <&moxtet>;
788		interrupts = <MOXTET_IRQ_TOPAZ>;
789		status = "disabled";
790
791		mdio {
792			#address-cells = <1>;
793			#size-cells = <0>;
794
795			switch2phy1_topaz: switch2phy1@11 {
796				reg = <0x11>;
797			};
798
799			switch2phy2_topaz: switch2phy2@12 {
800				reg = <0x12>;
801			};
802
803			switch2phy3_topaz: switch2phy3@13 {
804				reg = <0x13>;
805			};
806
807			switch2phy4_topaz: switch2phy4@14 {
808				reg = <0x14>;
809			};
810		};
811
812		ports {
813			#address-cells = <1>;
814			#size-cells = <0>;
815
816			port@1 {
817				reg = <0x1>;
818				label = "lan17";
819				phy-handle = <&switch2phy1_topaz>;
820			};
821
822			port@2 {
823				reg = <0x2>;
824				label = "lan18";
825				phy-handle = <&switch2phy2_topaz>;
826			};
827
828			port@3 {
829				reg = <0x3>;
830				label = "lan19";
831				phy-handle = <&switch2phy3_topaz>;
832			};
833
834			port@4 {
835				reg = <0x4>;
836				label = "lan20";
837				phy-handle = <&switch2phy4_topaz>;
838			};
839
840			port@5 {
841				reg = <0x5>;
842				label = "dsa";
843				phy-mode = "2500base-x";
844				managed = "in-band-status";
845				link = <&switch1port10 &switch0port10>;
846			};
847		};
848	};
849};
850