1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behun <marek.behun@nic.cz>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	memory@0 {
29		device_type = "memory";
30		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
31	};
32
33	leds {
34		compatible = "gpio-leds";
35		red {
36			label = "mox:red:activity";
37			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
38			linux,default-trigger = "default-on";
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		reset {
46			label = "reset";
47			linux,code = <KEY_RESTART>;
48			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
49			debounce-interval = <60>;
50		};
51	};
52
53	exp_usb3_vbus: usb3-vbus {
54		compatible = "regulator-fixed";
55		regulator-name = "usb3-vbus";
56		regulator-min-microvolt = <5000000>;
57		regulator-max-microvolt = <5000000>;
58		enable-active-high;
59		regulator-always-on;
60		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
61	};
62
63	usb3_phy: usb3-phy {
64		compatible = "usb-nop-xceiv";
65		vcc-supply = <&exp_usb3_vbus>;
66	};
67
68	vsdc_reg: vsdc-reg {
69		compatible = "regulator-gpio";
70		regulator-name = "vsdc";
71		regulator-min-microvolt = <1800000>;
72		regulator-max-microvolt = <3300000>;
73		regulator-boot-on;
74
75		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
76		gpios-states = <0>;
77		states = <1800000 0x1
78			  3300000 0x0>;
79		enable-active-high;
80	};
81
82	vsdio_reg: vsdio-reg {
83		compatible = "regulator-gpio";
84		regulator-name = "vsdio";
85		regulator-min-microvolt = <1800000>;
86		regulator-max-microvolt = <3300000>;
87		regulator-boot-on;
88
89		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
90		gpios-states = <0>;
91		states = <1800000 0x1
92			  3300000 0x0>;
93		enable-active-high;
94	};
95
96	sdhci1_pwrseq: sdhci1-pwrseq {
97		compatible = "mmc-pwrseq-simple";
98		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
99		status = "okay";
100	};
101
102	sfp: sfp {
103		compatible = "sff,sfp+";
104		i2c-bus = <&i2c0>;
105		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
106		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
107		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
108		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
109		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
110
111		/* enabled by U-Boot if SFP module is present */
112		status = "disabled";
113	};
114};
115
116&i2c0 {
117	pinctrl-names = "default";
118	pinctrl-0 = <&i2c1_pins>;
119	clock-frequency = <100000>;
120	status = "okay";
121
122	rtc@6f {
123		compatible = "microchip,mcp7940x";
124		reg = <0x6f>;
125	};
126};
127
128&pcie_reset_pins {
129	function = "gpio";
130};
131
132&pcie0 {
133	pinctrl-names = "default";
134	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
135	status = "okay";
136	max-link-speed = <2>;
137	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
138	phys = <&comphy1 0>;
139
140	/* enabled by U-Boot if PCIe module is present */
141	status = "disabled";
142};
143
144&uart0 {
145	status = "okay";
146};
147
148&eth0 {
149	pinctrl-names = "default";
150	pinctrl-0 = <&rgmii_pins>;
151	phy-mode = "rgmii-id";
152	phy = <&phy1>;
153	status = "okay";
154};
155
156&eth1 {
157	phy-mode = "2500base-x";
158	managed = "in-band-status";
159	phys = <&comphy0 1>;
160};
161
162&sdhci0 {
163	wp-inverted;
164	bus-width = <4>;
165	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
166	vqmmc-supply = <&vsdc_reg>;
167	marvell,pad-type = "sd";
168	status = "okay";
169};
170
171&sdhci1 {
172	pinctrl-names = "default";
173	pinctrl-0 = <&sdio_pins>;
174	non-removable;
175	bus-width = <4>;
176	marvell,pad-type = "sd";
177	vqmmc-supply = <&vsdio_reg>;
178	mmc-pwrseq = <&sdhci1_pwrseq>;
179	status = "okay";
180};
181
182&spi0 {
183	status = "okay";
184	pinctrl-names = "default";
185	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
186	assigned-clocks = <&nb_periph_clk 7>;
187	assigned-clock-parents = <&tbg 1>;
188	assigned-clock-rates = <20000000>;
189
190	spi-flash@0 {
191		#address-cells = <1>;
192		#size-cells = <1>;
193		compatible = "jedec,spi-nor";
194		reg = <0>;
195		spi-max-frequency = <20000000>;
196
197		partitions {
198			compatible = "fixed-partitions";
199			#address-cells = <1>;
200			#size-cells = <1>;
201
202			partition@0 {
203				label = "secure-firmware";
204				reg = <0x0 0x20000>;
205			};
206
207			partition@20000 {
208				label = "u-boot";
209				reg = <0x20000 0x160000>;
210			};
211
212			partition@180000 {
213				label = "u-boot-env";
214				reg = <0x180000 0x10000>;
215			};
216
217			partition@190000 {
218				label = "Rescue system";
219				reg = <0x190000 0x660000>;
220			};
221
222			partition@7f0000 {
223				label = "dtb";
224				reg = <0x7f0000 0x10000>;
225			};
226		};
227	};
228
229	moxtet: moxtet@1 {
230		#address-cells = <1>;
231		#size-cells = <0>;
232		compatible = "cznic,moxtet";
233		reg = <1>;
234		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
235		spi-max-frequency = <10000000>;
236		spi-cpol;
237		spi-cpha;
238		interrupt-controller;
239		#interrupt-cells = <1>;
240		interrupt-parent = <&gpiosb>;
241		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
242		status = "okay";
243
244		moxtet_sfp: gpio@0 {
245			compatible = "cznic,moxtet-gpio";
246			gpio-controller;
247			#gpio-cells = <2>;
248			reg = <0>;
249			status = "disabled";
250		};
251	};
252};
253
254&usb2 {
255	status = "okay";
256};
257
258&usb3 {
259	status = "okay";
260	phys = <&comphy2 0>;
261	usb-phy = <&usb3_phy>;
262};
263
264&mdio {
265	pinctrl-names = "default";
266	pinctrl-0 = <&smi_pins>;
267	status = "okay";
268
269	phy1: ethernet-phy@1 {
270		reg = <1>;
271	};
272
273	/* switch nodes are enabled by U-Boot if modules are present */
274	switch0@10 {
275		compatible = "marvell,mv88e6190";
276		reg = <0x10 0>;
277		dsa,member = <0 0>;
278		interrupt-parent = <&moxtet>;
279		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
280		status = "disabled";
281
282		mdio {
283			#address-cells = <1>;
284			#size-cells = <0>;
285
286			switch0phy1: switch0phy1@1 {
287				reg = <0x1>;
288			};
289
290			switch0phy2: switch0phy2@2 {
291				reg = <0x2>;
292			};
293
294			switch0phy3: switch0phy3@3 {
295				reg = <0x3>;
296			};
297
298			switch0phy4: switch0phy4@4 {
299				reg = <0x4>;
300			};
301
302			switch0phy5: switch0phy5@5 {
303				reg = <0x5>;
304			};
305
306			switch0phy6: switch0phy6@6 {
307				reg = <0x6>;
308			};
309
310			switch0phy7: switch0phy7@7 {
311				reg = <0x7>;
312			};
313
314			switch0phy8: switch0phy8@8 {
315				reg = <0x8>;
316			};
317		};
318
319		ports {
320			#address-cells = <1>;
321			#size-cells = <0>;
322
323			port@1 {
324				reg = <0x1>;
325				label = "lan1";
326				phy-handle = <&switch0phy1>;
327			};
328
329			port@2 {
330				reg = <0x2>;
331				label = "lan2";
332				phy-handle = <&switch0phy2>;
333			};
334
335			port@3 {
336				reg = <0x3>;
337				label = "lan3";
338				phy-handle = <&switch0phy3>;
339			};
340
341			port@4 {
342				reg = <0x4>;
343				label = "lan4";
344				phy-handle = <&switch0phy4>;
345			};
346
347			port@5 {
348				reg = <0x5>;
349				label = "lan5";
350				phy-handle = <&switch0phy5>;
351			};
352
353			port@6 {
354				reg = <0x6>;
355				label = "lan6";
356				phy-handle = <&switch0phy6>;
357			};
358
359			port@7 {
360				reg = <0x7>;
361				label = "lan7";
362				phy-handle = <&switch0phy7>;
363			};
364
365			port@8 {
366				reg = <0x8>;
367				label = "lan8";
368				phy-handle = <&switch0phy8>;
369			};
370
371			port@9 {
372				reg = <0x9>;
373				label = "cpu";
374				ethernet = <&eth1>;
375				phy-mode = "2500base-x";
376				managed = "in-band-status";
377			};
378
379			switch0port10: port@a {
380				reg = <0xa>;
381				label = "dsa";
382				phy-mode = "2500base-x";
383				managed = "in-band-status";
384				link = <&switch1port9 &switch2port9>;
385				status = "disabled";
386			};
387
388			port-sfp@a {
389				reg = <0xa>;
390				label = "sfp";
391				sfp = <&sfp>;
392				phy-mode = "sgmii";
393				managed = "in-band-status";
394				status = "disabled";
395			};
396		};
397	};
398
399	switch0@2 {
400		compatible = "marvell,mv88e6085";
401		reg = <0x2 0>;
402		dsa,member = <0 0>;
403		interrupt-parent = <&moxtet>;
404		interrupts = <MOXTET_IRQ_TOPAZ>;
405		status = "disabled";
406
407		mdio {
408			#address-cells = <1>;
409			#size-cells = <0>;
410
411			switch0phy1_topaz: switch0phy1@11 {
412				reg = <0x11>;
413			};
414
415			switch0phy2_topaz: switch0phy2@12 {
416				reg = <0x12>;
417			};
418
419			switch0phy3_topaz: switch0phy3@13 {
420				reg = <0x13>;
421			};
422
423			switch0phy4_topaz: switch0phy4@14 {
424				reg = <0x14>;
425			};
426		};
427
428		ports {
429			#address-cells = <1>;
430			#size-cells = <0>;
431
432			port@1 {
433				reg = <0x1>;
434				label = "lan1";
435				phy-handle = <&switch0phy1_topaz>;
436			};
437
438			port@2 {
439				reg = <0x2>;
440				label = "lan2";
441				phy-handle = <&switch0phy2_topaz>;
442			};
443
444			port@3 {
445				reg = <0x3>;
446				label = "lan3";
447				phy-handle = <&switch0phy3_topaz>;
448			};
449
450			port@4 {
451				reg = <0x4>;
452				label = "lan4";
453				phy-handle = <&switch0phy4_topaz>;
454			};
455
456			port@5 {
457				reg = <0x5>;
458				label = "cpu";
459				phy-mode = "2500base-x";
460				managed = "in-band-status";
461				ethernet = <&eth1>;
462			};
463		};
464	};
465
466	switch1@11 {
467		compatible = "marvell,mv88e6190";
468		reg = <0x11 0>;
469		dsa,member = <0 1>;
470		interrupt-parent = <&moxtet>;
471		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
472		status = "disabled";
473
474		mdio {
475			#address-cells = <1>;
476			#size-cells = <0>;
477
478			switch1phy1: switch1phy1@1 {
479				reg = <0x1>;
480			};
481
482			switch1phy2: switch1phy2@2 {
483				reg = <0x2>;
484			};
485
486			switch1phy3: switch1phy3@3 {
487				reg = <0x3>;
488			};
489
490			switch1phy4: switch1phy4@4 {
491				reg = <0x4>;
492			};
493
494			switch1phy5: switch1phy5@5 {
495				reg = <0x5>;
496			};
497
498			switch1phy6: switch1phy6@6 {
499				reg = <0x6>;
500			};
501
502			switch1phy7: switch1phy7@7 {
503				reg = <0x7>;
504			};
505
506			switch1phy8: switch1phy8@8 {
507				reg = <0x8>;
508			};
509		};
510
511		ports {
512			#address-cells = <1>;
513			#size-cells = <0>;
514
515			port@1 {
516				reg = <0x1>;
517				label = "lan9";
518				phy-handle = <&switch1phy1>;
519			};
520
521			port@2 {
522				reg = <0x2>;
523				label = "lan10";
524				phy-handle = <&switch1phy2>;
525			};
526
527			port@3 {
528				reg = <0x3>;
529				label = "lan11";
530				phy-handle = <&switch1phy3>;
531			};
532
533			port@4 {
534				reg = <0x4>;
535				label = "lan12";
536				phy-handle = <&switch1phy4>;
537			};
538
539			port@5 {
540				reg = <0x5>;
541				label = "lan13";
542				phy-handle = <&switch1phy5>;
543			};
544
545			port@6 {
546				reg = <0x6>;
547				label = "lan14";
548				phy-handle = <&switch1phy6>;
549			};
550
551			port@7 {
552				reg = <0x7>;
553				label = "lan15";
554				phy-handle = <&switch1phy7>;
555			};
556
557			port@8 {
558				reg = <0x8>;
559				label = "lan16";
560				phy-handle = <&switch1phy8>;
561			};
562
563			switch1port9: port@9 {
564				reg = <0x9>;
565				label = "dsa";
566				phy-mode = "2500base-x";
567				managed = "in-band-status";
568				link = <&switch0port10>;
569			};
570
571			switch1port10: port@a {
572				reg = <0xa>;
573				label = "dsa";
574				phy-mode = "2500base-x";
575				managed = "in-band-status";
576				link = <&switch2port9>;
577				status = "disabled";
578			};
579
580			port-sfp@a {
581				reg = <0xa>;
582				label = "sfp";
583				sfp = <&sfp>;
584				phy-mode = "sgmii";
585				managed = "in-band-status";
586				status = "disabled";
587			};
588		};
589	};
590
591	switch1@2 {
592		compatible = "marvell,mv88e6085";
593		reg = <0x2 0>;
594		dsa,member = <0 1>;
595		interrupt-parent = <&moxtet>;
596		interrupts = <MOXTET_IRQ_TOPAZ>;
597		status = "disabled";
598
599		mdio {
600			#address-cells = <1>;
601			#size-cells = <0>;
602
603			switch1phy1_topaz: switch1phy1@11 {
604				reg = <0x11>;
605			};
606
607			switch1phy2_topaz: switch1phy2@12 {
608				reg = <0x12>;
609			};
610
611			switch1phy3_topaz: switch1phy3@13 {
612				reg = <0x13>;
613			};
614
615			switch1phy4_topaz: switch1phy4@14 {
616				reg = <0x14>;
617			};
618		};
619
620		ports {
621			#address-cells = <1>;
622			#size-cells = <0>;
623
624			port@1 {
625				reg = <0x1>;
626				label = "lan9";
627				phy-handle = <&switch1phy1_topaz>;
628			};
629
630			port@2 {
631				reg = <0x2>;
632				label = "lan10";
633				phy-handle = <&switch1phy2_topaz>;
634			};
635
636			port@3 {
637				reg = <0x3>;
638				label = "lan11";
639				phy-handle = <&switch1phy3_topaz>;
640			};
641
642			port@4 {
643				reg = <0x4>;
644				label = "lan12";
645				phy-handle = <&switch1phy4_topaz>;
646			};
647
648			port@5 {
649				reg = <0x5>;
650				label = "dsa";
651				phy-mode = "2500base-x";
652				managed = "in-band-status";
653				link = <&switch0port10>;
654			};
655		};
656	};
657
658	switch2@12 {
659		compatible = "marvell,mv88e6190";
660		reg = <0x12 0>;
661		dsa,member = <0 2>;
662		interrupt-parent = <&moxtet>;
663		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
664		status = "disabled";
665
666		mdio {
667			#address-cells = <1>;
668			#size-cells = <0>;
669
670			switch2phy1: switch2phy1@1 {
671				reg = <0x1>;
672			};
673
674			switch2phy2: switch2phy2@2 {
675				reg = <0x2>;
676			};
677
678			switch2phy3: switch2phy3@3 {
679				reg = <0x3>;
680			};
681
682			switch2phy4: switch2phy4@4 {
683				reg = <0x4>;
684			};
685
686			switch2phy5: switch2phy5@5 {
687				reg = <0x5>;
688			};
689
690			switch2phy6: switch2phy6@6 {
691				reg = <0x6>;
692			};
693
694			switch2phy7: switch2phy7@7 {
695				reg = <0x7>;
696			};
697
698			switch2phy8: switch2phy8@8 {
699				reg = <0x8>;
700			};
701		};
702
703		ports {
704			#address-cells = <1>;
705			#size-cells = <0>;
706
707			port@1 {
708				reg = <0x1>;
709				label = "lan17";
710				phy-handle = <&switch2phy1>;
711			};
712
713			port@2 {
714				reg = <0x2>;
715				label = "lan18";
716				phy-handle = <&switch2phy2>;
717			};
718
719			port@3 {
720				reg = <0x3>;
721				label = "lan19";
722				phy-handle = <&switch2phy3>;
723			};
724
725			port@4 {
726				reg = <0x4>;
727				label = "lan20";
728				phy-handle = <&switch2phy4>;
729			};
730
731			port@5 {
732				reg = <0x5>;
733				label = "lan21";
734				phy-handle = <&switch2phy5>;
735			};
736
737			port@6 {
738				reg = <0x6>;
739				label = "lan22";
740				phy-handle = <&switch2phy6>;
741			};
742
743			port@7 {
744				reg = <0x7>;
745				label = "lan23";
746				phy-handle = <&switch2phy7>;
747			};
748
749			port@8 {
750				reg = <0x8>;
751				label = "lan24";
752				phy-handle = <&switch2phy8>;
753			};
754
755			switch2port9: port@9 {
756				reg = <0x9>;
757				label = "dsa";
758				phy-mode = "2500base-x";
759				managed = "in-band-status";
760				link = <&switch1port10 &switch0port10>;
761			};
762
763			port-sfp@a {
764				reg = <0xa>;
765				label = "sfp";
766				sfp = <&sfp>;
767				phy-mode = "sgmii";
768				managed = "in-band-status";
769				status = "disabled";
770			};
771		};
772	};
773
774	switch2@2 {
775		compatible = "marvell,mv88e6085";
776		reg = <0x2 0>;
777		dsa,member = <0 2>;
778		interrupt-parent = <&moxtet>;
779		interrupts = <MOXTET_IRQ_TOPAZ>;
780		status = "disabled";
781
782		mdio {
783			#address-cells = <1>;
784			#size-cells = <0>;
785
786			switch2phy1_topaz: switch2phy1@11 {
787				reg = <0x11>;
788			};
789
790			switch2phy2_topaz: switch2phy2@12 {
791				reg = <0x12>;
792			};
793
794			switch2phy3_topaz: switch2phy3@13 {
795				reg = <0x13>;
796			};
797
798			switch2phy4_topaz: switch2phy4@14 {
799				reg = <0x14>;
800			};
801		};
802
803		ports {
804			#address-cells = <1>;
805			#size-cells = <0>;
806
807			port@1 {
808				reg = <0x1>;
809				label = "lan17";
810				phy-handle = <&switch2phy1_topaz>;
811			};
812
813			port@2 {
814				reg = <0x2>;
815				label = "lan18";
816				phy-handle = <&switch2phy2_topaz>;
817			};
818
819			port@3 {
820				reg = <0x3>;
821				label = "lan19";
822				phy-handle = <&switch2phy3_topaz>;
823			};
824
825			port@4 {
826				reg = <0x4>;
827				label = "lan20";
828				phy-handle = <&switch2phy4_topaz>;
829			};
830
831			port@5 {
832				reg = <0x5>;
833				label = "dsa";
834				phy-mode = "2500base-x";
835				managed = "in-band-status";
836				link = <&switch1port10 &switch0port10>;
837			};
838		};
839	};
840};
841