1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Globalscale Marvell ESPRESSOBin Board
4 * Copyright (C) 2016 Marvell
5 *
6 * Romain Perier <romain.perier@free-electrons.com>
7 *
8 */
9/*
10 * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
11 */
12
13/dts-v1/;
14
15#include <dt-bindings/gpio/gpio.h>
16#include "armada-372x.dtsi"
17
18/ {
19	model = "Globalscale Marvell ESPRESSOBin Board";
20	compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
21
22	chosen {
23		stdout-path = "serial0:115200n8";
24	};
25
26	memory@0 {
27		device_type = "memory";
28		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
29	};
30
31	vcc_sd_reg1: regulator {
32		compatible = "regulator-gpio";
33		regulator-name = "vcc_sd1";
34		regulator-min-microvolt = <1800000>;
35		regulator-max-microvolt = <3300000>;
36		regulator-boot-on;
37
38		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
39		gpios-states = <0>;
40		states = <1800000 0x1
41			  3300000 0x0>;
42		enable-active-high;
43	};
44};
45
46/* J9 */
47&pcie0 {
48	status = "okay";
49};
50
51/* J6 */
52&sata {
53	status = "okay";
54};
55
56/* J1 */
57&sdhci1 {
58	wp-inverted;
59	bus-width = <4>;
60	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
61	marvell,pad-type = "sd";
62	vqmmc-supply = <&vcc_sd_reg1>;
63	status = "okay";
64};
65
66/* Exported on the micro USB connector J5 through an FTDI */
67&uart0 {
68	pinctrl-names = "default";
69	pinctrl-0 = <&uart1_pins>;
70	status = "okay";
71};
72
73/*
74 * Connector J17 and J18 expose a number of different features. Some pins are
75 * multiplexed. This is the case for instance for the following features:
76 * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
77 *   how to enable it. Beware that the signals are 1.8V TTL.
78 * - I2C
79 * - SPI
80 * - MMC
81 */
82
83/* J7 */
84&usb3 {
85	status = "okay";
86};
87
88/* J8 */
89&usb2 {
90	status = "okay";
91};
92
93&mdio {
94	switch0: switch0@1 {
95		compatible = "marvell,mv88e6085";
96		#address-cells = <1>;
97		#size-cells = <0>;
98		reg = <1>;
99
100		dsa,member = <0 0>;
101
102		ports {
103			#address-cells = <1>;
104			#size-cells = <0>;
105
106			port@0 {
107				reg = <0>;
108				label = "cpu";
109				ethernet = <&eth0>;
110			};
111
112			port@1 {
113				reg = <1>;
114				label = "wan";
115				phy-handle = <&switch0phy0>;
116			};
117
118			port@2 {
119				reg = <2>;
120				label = "lan0";
121				phy-handle = <&switch0phy1>;
122			};
123
124			port@3 {
125				reg = <3>;
126				label = "lan1";
127				phy-handle = <&switch0phy2>;
128			};
129
130		};
131
132		mdio {
133			#address-cells = <1>;
134			#size-cells = <0>;
135
136			switch0phy0: switch0phy0@11 {
137				reg = <0x11>;
138			};
139			switch0phy1: switch0phy1@12 {
140				reg = <0x12>;
141			};
142			switch0phy2: switch0phy2@13 {
143				reg = <0x13>;
144			};
145		};
146	};
147};
148
149&eth0 {
150	phy-mode = "rgmii-id";
151	status = "okay";
152
153	fixed-link {
154		speed = <1000>;
155		full-duplex;
156	};
157};
158