1*b795fadfSChris Packham// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*b795fadfSChris Packham/* 3*b795fadfSChris Packham * Device Tree For AC5. 4*b795fadfSChris Packham * 5*b795fadfSChris Packham * Copyright (C) 2021 Marvell 6*b795fadfSChris Packham * Copyright (C) 2022 Allied Telesis Labs 7*b795fadfSChris Packham */ 8*b795fadfSChris Packham 9*b795fadfSChris Packham#include <dt-bindings/gpio/gpio.h> 10*b795fadfSChris Packham#include <dt-bindings/interrupt-controller/arm-gic.h> 11*b795fadfSChris Packham 12*b795fadfSChris Packham/ { 13*b795fadfSChris Packham model = "Marvell AC5 SoC"; 14*b795fadfSChris Packham compatible = "marvell,ac5"; 15*b795fadfSChris Packham interrupt-parent = <&gic>; 16*b795fadfSChris Packham #address-cells = <2>; 17*b795fadfSChris Packham #size-cells = <2>; 18*b795fadfSChris Packham 19*b795fadfSChris Packham cpus { 20*b795fadfSChris Packham #address-cells = <2>; 21*b795fadfSChris Packham #size-cells = <0>; 22*b795fadfSChris Packham 23*b795fadfSChris Packham cpu-map { 24*b795fadfSChris Packham cluster0 { 25*b795fadfSChris Packham core0 { 26*b795fadfSChris Packham cpu = <&cpu0>; 27*b795fadfSChris Packham }; 28*b795fadfSChris Packham core1 { 29*b795fadfSChris Packham cpu = <&cpu1>; 30*b795fadfSChris Packham }; 31*b795fadfSChris Packham }; 32*b795fadfSChris Packham }; 33*b795fadfSChris Packham 34*b795fadfSChris Packham cpu0: cpu@0 { 35*b795fadfSChris Packham device_type = "cpu"; 36*b795fadfSChris Packham compatible = "arm,cortex-a55"; 37*b795fadfSChris Packham reg = <0x0 0x0>; 38*b795fadfSChris Packham enable-method = "psci"; 39*b795fadfSChris Packham next-level-cache = <&l2>; 40*b795fadfSChris Packham }; 41*b795fadfSChris Packham 42*b795fadfSChris Packham cpu1: cpu@1 { 43*b795fadfSChris Packham device_type = "cpu"; 44*b795fadfSChris Packham compatible = "arm,cortex-a55"; 45*b795fadfSChris Packham reg = <0x0 0x100>; 46*b795fadfSChris Packham enable-method = "psci"; 47*b795fadfSChris Packham next-level-cache = <&l2>; 48*b795fadfSChris Packham }; 49*b795fadfSChris Packham 50*b795fadfSChris Packham l2: l2-cache { 51*b795fadfSChris Packham compatible = "cache"; 52*b795fadfSChris Packham }; 53*b795fadfSChris Packham }; 54*b795fadfSChris Packham 55*b795fadfSChris Packham psci { 56*b795fadfSChris Packham compatible = "arm,psci-0.2"; 57*b795fadfSChris Packham method = "smc"; 58*b795fadfSChris Packham }; 59*b795fadfSChris Packham 60*b795fadfSChris Packham timer { 61*b795fadfSChris Packham compatible = "arm,armv8-timer"; 62*b795fadfSChris Packham interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, 63*b795fadfSChris Packham <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, 64*b795fadfSChris Packham <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, 65*b795fadfSChris Packham <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 66*b795fadfSChris Packham }; 67*b795fadfSChris Packham 68*b795fadfSChris Packham pmu { 69*b795fadfSChris Packham compatible = "arm,armv8-pmuv3"; 70*b795fadfSChris Packham interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; 71*b795fadfSChris Packham }; 72*b795fadfSChris Packham 73*b795fadfSChris Packham soc { 74*b795fadfSChris Packham compatible = "simple-bus"; 75*b795fadfSChris Packham #address-cells = <2>; 76*b795fadfSChris Packham #size-cells = <2>; 77*b795fadfSChris Packham ranges; 78*b795fadfSChris Packham dma-ranges; 79*b795fadfSChris Packham 80*b795fadfSChris Packham internal-regs@7f000000 { 81*b795fadfSChris Packham #address-cells = <1>; 82*b795fadfSChris Packham #size-cells = <1>; 83*b795fadfSChris Packham compatible = "simple-bus"; 84*b795fadfSChris Packham /* 16M internal register @ 0x7f00_0000 */ 85*b795fadfSChris Packham ranges = <0x0 0x0 0x7f000000 0x1000000>; 86*b795fadfSChris Packham dma-coherent; 87*b795fadfSChris Packham 88*b795fadfSChris Packham uart0: serial@12000 { 89*b795fadfSChris Packham compatible = "snps,dw-apb-uart"; 90*b795fadfSChris Packham reg = <0x12000 0x100>; 91*b795fadfSChris Packham reg-shift = <2>; 92*b795fadfSChris Packham interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 93*b795fadfSChris Packham reg-io-width = <1>; 94*b795fadfSChris Packham clocks = <&cnm_clock>; 95*b795fadfSChris Packham status = "okay"; 96*b795fadfSChris Packham }; 97*b795fadfSChris Packham 98*b795fadfSChris Packham mdio: mdio@22004 { 99*b795fadfSChris Packham #address-cells = <1>; 100*b795fadfSChris Packham #size-cells = <0>; 101*b795fadfSChris Packham compatible = "marvell,orion-mdio"; 102*b795fadfSChris Packham reg = <0x22004 0x4>; 103*b795fadfSChris Packham clocks = <&cnm_clock>; 104*b795fadfSChris Packham }; 105*b795fadfSChris Packham 106*b795fadfSChris Packham i2c0: i2c@11000{ 107*b795fadfSChris Packham compatible = "marvell,mv78230-i2c"; 108*b795fadfSChris Packham reg = <0x11000 0x20>; 109*b795fadfSChris Packham #address-cells = <1>; 110*b795fadfSChris Packham #size-cells = <0>; 111*b795fadfSChris Packham 112*b795fadfSChris Packham clocks = <&cnm_clock>; 113*b795fadfSChris Packham clock-names = "core"; 114*b795fadfSChris Packham interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 115*b795fadfSChris Packham clock-frequency=<100000>; 116*b795fadfSChris Packham 117*b795fadfSChris Packham pinctrl-names = "default", "gpio"; 118*b795fadfSChris Packham pinctrl-0 = <&i2c0_pins>; 119*b795fadfSChris Packham pinctrl-1 = <&i2c0_gpio>; 120*b795fadfSChris Packham scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; 121*b795fadfSChris Packham sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; 122*b795fadfSChris Packham status = "disabled"; 123*b795fadfSChris Packham }; 124*b795fadfSChris Packham 125*b795fadfSChris Packham i2c1: i2c@11100{ 126*b795fadfSChris Packham compatible = "marvell,mv78230-i2c"; 127*b795fadfSChris Packham reg = <0x11100 0x20>; 128*b795fadfSChris Packham #address-cells = <1>; 129*b795fadfSChris Packham #size-cells = <0>; 130*b795fadfSChris Packham 131*b795fadfSChris Packham clocks = <&cnm_clock>; 132*b795fadfSChris Packham clock-names = "core"; 133*b795fadfSChris Packham interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 134*b795fadfSChris Packham clock-frequency=<100000>; 135*b795fadfSChris Packham 136*b795fadfSChris Packham pinctrl-names = "default", "gpio"; 137*b795fadfSChris Packham pinctrl-0 = <&i2c1_pins>; 138*b795fadfSChris Packham pinctrl-1 = <&i2c1_gpio>; 139*b795fadfSChris Packham scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; 140*b795fadfSChris Packham sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; 141*b795fadfSChris Packham status = "disabled"; 142*b795fadfSChris Packham }; 143*b795fadfSChris Packham 144*b795fadfSChris Packham gpio0: gpio@18100 { 145*b795fadfSChris Packham compatible = "marvell,orion-gpio"; 146*b795fadfSChris Packham reg = <0x18100 0x40>; 147*b795fadfSChris Packham ngpios = <32>; 148*b795fadfSChris Packham gpio-controller; 149*b795fadfSChris Packham #gpio-cells = <2>; 150*b795fadfSChris Packham gpio-ranges = <&pinctrl0 0 0 32>; 151*b795fadfSChris Packham marvell,pwm-offset = <0x1f0>; 152*b795fadfSChris Packham interrupt-controller; 153*b795fadfSChris Packham #interrupt-cells = <2>; 154*b795fadfSChris Packham interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 155*b795fadfSChris Packham <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 156*b795fadfSChris Packham <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 157*b795fadfSChris Packham <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 158*b795fadfSChris Packham }; 159*b795fadfSChris Packham 160*b795fadfSChris Packham gpio1: gpio@18140 { 161*b795fadfSChris Packham reg = <0x18140 0x40>; 162*b795fadfSChris Packham compatible = "marvell,orion-gpio"; 163*b795fadfSChris Packham ngpios = <14>; 164*b795fadfSChris Packham gpio-controller; 165*b795fadfSChris Packham #gpio-cells = <2>; 166*b795fadfSChris Packham gpio-ranges = <&pinctrl0 0 32 14>; 167*b795fadfSChris Packham marvell,pwm-offset = <0x1f0>; 168*b795fadfSChris Packham interrupt-controller; 169*b795fadfSChris Packham #interrupt-cells = <2>; 170*b795fadfSChris Packham interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 171*b795fadfSChris Packham <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 172*b795fadfSChris Packham }; 173*b795fadfSChris Packham }; 174*b795fadfSChris Packham 175*b795fadfSChris Packham /* 176*b795fadfSChris Packham * Dedicated section for devices behind 32bit controllers so we 177*b795fadfSChris Packham * can configure specific DMA mapping for them 178*b795fadfSChris Packham */ 179*b795fadfSChris Packham behind-32bit-controller@7f000000 { 180*b795fadfSChris Packham compatible = "simple-bus"; 181*b795fadfSChris Packham #address-cells = <0x2>; 182*b795fadfSChris Packham #size-cells = <0x2>; 183*b795fadfSChris Packham ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; 184*b795fadfSChris Packham /* Host phy ram starts at 0x200M */ 185*b795fadfSChris Packham dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; 186*b795fadfSChris Packham dma-coherent; 187*b795fadfSChris Packham 188*b795fadfSChris Packham eth0: ethernet@20000 { 189*b795fadfSChris Packham compatible = "marvell,armada-ac5-neta"; 190*b795fadfSChris Packham reg = <0x0 0x20000 0x0 0x4000>; 191*b795fadfSChris Packham interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 192*b795fadfSChris Packham clocks = <&cnm_clock>; 193*b795fadfSChris Packham phy-mode = "sgmii"; 194*b795fadfSChris Packham status = "disabled"; 195*b795fadfSChris Packham }; 196*b795fadfSChris Packham 197*b795fadfSChris Packham eth1: ethernet@24000 { 198*b795fadfSChris Packham compatible = "marvell,armada-ac5-neta"; 199*b795fadfSChris Packham reg = <0x0 0x24000 0x0 0x4000>; 200*b795fadfSChris Packham interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 201*b795fadfSChris Packham clocks = <&cnm_clock>; 202*b795fadfSChris Packham phy-mode = "sgmii"; 203*b795fadfSChris Packham status = "disabled"; 204*b795fadfSChris Packham }; 205*b795fadfSChris Packham 206*b795fadfSChris Packham usb0: usb@80000 { 207*b795fadfSChris Packham compatible = "marvell,orion-ehci"; 208*b795fadfSChris Packham reg = <0x0 0x80000 0x0 0x500>; 209*b795fadfSChris Packham interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 210*b795fadfSChris Packham status = "disabled"; 211*b795fadfSChris Packham }; 212*b795fadfSChris Packham 213*b795fadfSChris Packham usb1: usb@a0000 { 214*b795fadfSChris Packham compatible = "marvell,orion-ehci"; 215*b795fadfSChris Packham reg = <0x0 0xa0000 0x0 0x500>; 216*b795fadfSChris Packham interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 217*b795fadfSChris Packham status = "disabled"; 218*b795fadfSChris Packham }; 219*b795fadfSChris Packham }; 220*b795fadfSChris Packham 221*b795fadfSChris Packham pinctrl0: pinctrl@80020100 { 222*b795fadfSChris Packham compatible = "marvell,ac5-pinctrl"; 223*b795fadfSChris Packham reg = <0 0x80020100 0 0x20>; 224*b795fadfSChris Packham 225*b795fadfSChris Packham i2c0_pins: i2c0-pins { 226*b795fadfSChris Packham marvell,pins = "mpp26", "mpp27"; 227*b795fadfSChris Packham marvell,function = "i2c0"; 228*b795fadfSChris Packham }; 229*b795fadfSChris Packham 230*b795fadfSChris Packham i2c0_gpio: i2c0-gpio-pins { 231*b795fadfSChris Packham marvell,pins = "mpp26", "mpp27"; 232*b795fadfSChris Packham marvell,function = "gpio"; 233*b795fadfSChris Packham }; 234*b795fadfSChris Packham 235*b795fadfSChris Packham i2c1_pins: i2c1-pins { 236*b795fadfSChris Packham marvell,pins = "mpp20", "mpp21"; 237*b795fadfSChris Packham marvell,function = "i2c1"; 238*b795fadfSChris Packham }; 239*b795fadfSChris Packham 240*b795fadfSChris Packham i2c1_gpio: i2c1-gpio-pins { 241*b795fadfSChris Packham marvell,pins = "mpp20", "mpp21"; 242*b795fadfSChris Packham marvell,function = "i2c1"; 243*b795fadfSChris Packham }; 244*b795fadfSChris Packham }; 245*b795fadfSChris Packham 246*b795fadfSChris Packham spi0: spi@805a0000 { 247*b795fadfSChris Packham compatible = "marvell,armada-3700-spi"; 248*b795fadfSChris Packham reg = <0x0 0x805a0000 0x0 0x50>; 249*b795fadfSChris Packham #address-cells = <0x1>; 250*b795fadfSChris Packham #size-cells = <0x0>; 251*b795fadfSChris Packham clocks = <&spi_clock>; 252*b795fadfSChris Packham interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 253*b795fadfSChris Packham num-cs = <1>; 254*b795fadfSChris Packham status = "disabled"; 255*b795fadfSChris Packham }; 256*b795fadfSChris Packham 257*b795fadfSChris Packham spi1: spi@805a8000 { 258*b795fadfSChris Packham compatible = "marvell,armada-3700-spi"; 259*b795fadfSChris Packham reg = <0x0 0x805a8000 0x0 0x50>; 260*b795fadfSChris Packham #address-cells = <0x1>; 261*b795fadfSChris Packham #size-cells = <0x0>; 262*b795fadfSChris Packham clocks = <&spi_clock>; 263*b795fadfSChris Packham interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 264*b795fadfSChris Packham num-cs = <1>; 265*b795fadfSChris Packham status = "disabled"; 266*b795fadfSChris Packham }; 267*b795fadfSChris Packham 268*b795fadfSChris Packham gic: interrupt-controller@80600000 { 269*b795fadfSChris Packham compatible = "arm,gic-v3"; 270*b795fadfSChris Packham #interrupt-cells = <3>; 271*b795fadfSChris Packham interrupt-controller; 272*b795fadfSChris Packham reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ 273*b795fadfSChris Packham <0x0 0x80660000 0x0 0x40000>; /* GICR */ 274*b795fadfSChris Packham interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 275*b795fadfSChris Packham }; 276*b795fadfSChris Packham }; 277*b795fadfSChris Packham 278*b795fadfSChris Packham clocks { 279*b795fadfSChris Packham cnm_clock: cnm-clock { 280*b795fadfSChris Packham compatible = "fixed-clock"; 281*b795fadfSChris Packham #clock-cells = <0>; 282*b795fadfSChris Packham clock-frequency = <328000000>; 283*b795fadfSChris Packham }; 284*b795fadfSChris Packham 285*b795fadfSChris Packham spi_clock: spi-clock { 286*b795fadfSChris Packham compatible = "fixed-clock"; 287*b795fadfSChris Packham #clock-cells = <0>; 288*b795fadfSChris Packham clock-frequency = <200000000>; 289*b795fadfSChris Packham }; 290*b795fadfSChris Packham }; 291*b795fadfSChris Packham}; 292