1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for lg1313 SoC 4 * 5 * Copyright (C) 2016, LG Electronics 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 compatible = "lge,lg1313"; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a53"; 25 reg = <0x0 0x0>; 26 next-level-cache = <&L2_0>; 27 }; 28 cpu1: cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a53"; 31 reg = <0x0 0x1>; 32 enable-method = "psci"; 33 next-level-cache = <&L2_0>; 34 }; 35 cpu2: cpu@2 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0 0x2>; 39 enable-method = "psci"; 40 next-level-cache = <&L2_0>; 41 }; 42 cpu3: cpu@3 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53"; 45 reg = <0x0 0x3>; 46 enable-method = "psci"; 47 next-level-cache = <&L2_0>; 48 }; 49 L2_0: l2-cache0 { 50 compatible = "cache"; 51 cache-level = <2>; 52 cache-unified; 53 }; 54 }; 55 56 psci { 57 compatible = "arm,psci-0.2", "arm,psci"; 58 method = "smc"; 59 cpu_suspend = <0x84000001>; 60 cpu_off = <0x84000002>; 61 cpu_on = <0x84000003>; 62 }; 63 64 gic: interrupt-controller@c0001000 { 65 #interrupt-cells = <3>; 66 compatible = "arm,gic-400"; 67 interrupt-controller; 68 reg = <0x0 0xc0001000 0x1000>, 69 <0x0 0xc0002000 0x2000>, 70 <0x0 0xc0004000 0x2000>, 71 <0x0 0xc0006000 0x2000>; 72 }; 73 74 pmu { 75 compatible = "arm,cortex-a53-pmu"; 76 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 80 interrupt-affinity = <&cpu0>, 81 <&cpu1>, 82 <&cpu2>, 83 <&cpu3>; 84 }; 85 86 timer { 87 compatible = "arm,armv8-timer"; 88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) | 89 IRQ_TYPE_LEVEL_LOW)>, 90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) | 91 IRQ_TYPE_LEVEL_LOW)>, 92 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) | 93 IRQ_TYPE_LEVEL_LOW)>, 94 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) | 95 IRQ_TYPE_LEVEL_LOW)>; 96 }; 97 98 clk_bus: clk_bus { 99 #clock-cells = <0>; 100 101 compatible = "fixed-clock"; 102 clock-frequency = <198000000>; 103 clock-output-names = "BUSCLK"; 104 }; 105 106 soc { 107 #address-cells = <2>; 108 #size-cells = <1>; 109 110 compatible = "simple-bus"; 111 interrupt-parent = <&gic>; 112 ranges; 113 114 eth0: ethernet@c3700000 { 115 compatible = "cdns,gem"; 116 reg = <0x0 0xc3700000 0x1000>; 117 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&clk_bus>, <&clk_bus>; 119 clock-names = "hclk", "pclk"; 120 phy-mode = "rmii"; 121 /* Filled in by boot */ 122 mac-address = [ 00 00 00 00 00 00 ]; 123 }; 124 }; 125 126 amba { 127 #address-cells = <2>; 128 #size-cells = <1>; 129 130 compatible = "simple-bus"; 131 interrupt-parent = <&gic>; 132 ranges; 133 134 timers: timer@fd100000 { 135 compatible = "arm,sp804", "arm,primecell"; 136 reg = <0x0 0xfd100000 0x1000>; 137 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; 139 clock-names = "timer0clk", "timer1clk", "apb_pclk"; 140 }; 141 wdog: watchdog@fd200000 { 142 compatible = "arm,sp805", "arm,primecell"; 143 reg = <0x0 0xfd200000 0x1000>; 144 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&clk_bus>, <&clk_bus>; 146 clock-names = "wdog_clk", "apb_pclk"; 147 }; 148 uart0: serial@fe000000 { 149 compatible = "arm,pl011", "arm,primecell"; 150 reg = <0x0 0xfe000000 0x1000>; 151 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&clk_bus>; 153 clock-names = "apb_pclk"; 154 status = "disabled"; 155 }; 156 uart1: serial@fe100000 { 157 compatible = "arm,pl011", "arm,primecell"; 158 reg = <0x0 0xfe100000 0x1000>; 159 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&clk_bus>; 161 clock-names = "apb_pclk"; 162 status = "disabled"; 163 }; 164 uart2: serial@fe200000 { 165 compatible = "arm,pl011", "arm,primecell"; 166 reg = <0x0 0xfe200000 0x1000>; 167 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&clk_bus>; 169 clock-names = "apb_pclk"; 170 status = "disabled"; 171 }; 172 spi0: spi@fe800000 { 173 compatible = "arm,pl022", "arm,primecell"; 174 reg = <0x0 0xfe800000 0x1000>; 175 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&clk_bus>; 177 clock-names = "apb_pclk"; 178 }; 179 spi1: spi@fe900000 { 180 compatible = "arm,pl022", "arm,primecell"; 181 reg = <0x0 0xfe900000 0x1000>; 182 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&clk_bus>; 184 clock-names = "apb_pclk"; 185 }; 186 dmac0: dma-controller@c1128000 { 187 compatible = "arm,pl330", "arm,primecell"; 188 reg = <0x0 0xc1128000 0x1000>; 189 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&clk_bus>; 191 clock-names = "apb_pclk"; 192 #dma-cells = <1>; 193 }; 194 gpio0: gpio@fd400000 { 195 #gpio-cells = <2>; 196 compatible = "arm,pl061", "arm,primecell"; 197 gpio-controller; 198 reg = <0x0 0xfd400000 0x1000>; 199 clocks = <&clk_bus>; 200 clock-names = "apb_pclk"; 201 status = "disabled"; 202 }; 203 gpio1: gpio@fd410000 { 204 #gpio-cells = <2>; 205 compatible = "arm,pl061", "arm,primecell"; 206 gpio-controller; 207 reg = <0x0 0xfd410000 0x1000>; 208 clocks = <&clk_bus>; 209 clock-names = "apb_pclk"; 210 status = "disabled"; 211 }; 212 gpio2: gpio@fd420000 { 213 #gpio-cells = <2>; 214 compatible = "arm,pl061", "arm,primecell"; 215 gpio-controller; 216 reg = <0x0 0xfd420000 0x1000>; 217 clocks = <&clk_bus>; 218 clock-names = "apb_pclk"; 219 status = "disabled"; 220 }; 221 gpio3: gpio@fd430000 { 222 #gpio-cells = <2>; 223 compatible = "arm,pl061", "arm,primecell"; 224 gpio-controller; 225 reg = <0x0 0xfd430000 0x1000>; 226 clocks = <&clk_bus>; 227 clock-names = "apb_pclk"; 228 }; 229 gpio4: gpio@fd440000 { 230 #gpio-cells = <2>; 231 compatible = "arm,pl061", "arm,primecell"; 232 gpio-controller; 233 reg = <0x0 0xfd440000 0x1000>; 234 clocks = <&clk_bus>; 235 clock-names = "apb_pclk"; 236 status = "disabled"; 237 }; 238 gpio5: gpio@fd450000 { 239 #gpio-cells = <2>; 240 compatible = "arm,pl061", "arm,primecell"; 241 gpio-controller; 242 reg = <0x0 0xfd450000 0x1000>; 243 clocks = <&clk_bus>; 244 clock-names = "apb_pclk"; 245 status = "disabled"; 246 }; 247 gpio6: gpio@fd460000 { 248 #gpio-cells = <2>; 249 compatible = "arm,pl061", "arm,primecell"; 250 gpio-controller; 251 reg = <0x0 0xfd460000 0x1000>; 252 clocks = <&clk_bus>; 253 clock-names = "apb_pclk"; 254 status = "disabled"; 255 }; 256 gpio7: gpio@fd470000 { 257 #gpio-cells = <2>; 258 compatible = "arm,pl061", "arm,primecell"; 259 gpio-controller; 260 reg = <0x0 0xfd470000 0x1000>; 261 clocks = <&clk_bus>; 262 clock-names = "apb_pclk"; 263 status = "disabled"; 264 }; 265 gpio8: gpio@fd480000 { 266 #gpio-cells = <2>; 267 compatible = "arm,pl061", "arm,primecell"; 268 gpio-controller; 269 reg = <0x0 0xfd480000 0x1000>; 270 clocks = <&clk_bus>; 271 clock-names = "apb_pclk"; 272 status = "disabled"; 273 }; 274 gpio9: gpio@fd490000 { 275 #gpio-cells = <2>; 276 compatible = "arm,pl061", "arm,primecell"; 277 gpio-controller; 278 reg = <0x0 0xfd490000 0x1000>; 279 clocks = <&clk_bus>; 280 clock-names = "apb_pclk"; 281 status = "disabled"; 282 }; 283 gpio10: gpio@fd4a0000 { 284 #gpio-cells = <2>; 285 compatible = "arm,pl061", "arm,primecell"; 286 gpio-controller; 287 reg = <0x0 0xfd4a0000 0x1000>; 288 clocks = <&clk_bus>; 289 clock-names = "apb_pclk"; 290 status = "disabled"; 291 }; 292 gpio11: gpio@fd4b0000 { 293 #gpio-cells = <2>; 294 compatible = "arm,pl061", "arm,primecell"; 295 gpio-controller; 296 reg = <0x0 0xfd4b0000 0x1000>; 297 clocks = <&clk_bus>; 298 clock-names = "apb_pclk"; 299 }; 300 gpio12: gpio@fd4c0000 { 301 #gpio-cells = <2>; 302 compatible = "arm,pl061", "arm,primecell"; 303 gpio-controller; 304 reg = <0x0 0xfd4c0000 0x1000>; 305 clocks = <&clk_bus>; 306 clock-names = "apb_pclk"; 307 status = "disabled"; 308 }; 309 gpio13: gpio@fd4d0000 { 310 #gpio-cells = <2>; 311 compatible = "arm,pl061", "arm,primecell"; 312 gpio-controller; 313 reg = <0x0 0xfd4d0000 0x1000>; 314 clocks = <&clk_bus>; 315 clock-names = "apb_pclk"; 316 status = "disabled"; 317 }; 318 gpio14: gpio@fd4e0000 { 319 #gpio-cells = <2>; 320 compatible = "arm,pl061", "arm,primecell"; 321 gpio-controller; 322 reg = <0x0 0xfd4e0000 0x1000>; 323 clocks = <&clk_bus>; 324 clock-names = "apb_pclk"; 325 status = "disabled"; 326 }; 327 gpio15: gpio@fd4f0000 { 328 #gpio-cells = <2>; 329 compatible = "arm,pl061", "arm,primecell"; 330 gpio-controller; 331 reg = <0x0 0xfd4f0000 0x1000>; 332 clocks = <&clk_bus>; 333 clock-names = "apb_pclk"; 334 status = "disabled"; 335 }; 336 gpio16: gpio@fd500000 { 337 #gpio-cells = <2>; 338 compatible = "arm,pl061", "arm,primecell"; 339 gpio-controller; 340 reg = <0x0 0xfd500000 0x1000>; 341 clocks = <&clk_bus>; 342 clock-names = "apb_pclk"; 343 status = "disabled"; 344 }; 345 gpio17: gpio@fd510000 { 346 #gpio-cells = <2>; 347 compatible = "arm,pl061", "arm,primecell"; 348 gpio-controller; 349 reg = <0x0 0xfd510000 0x1000>; 350 clocks = <&clk_bus>; 351 clock-names = "apb_pclk"; 352 }; 353 }; 354}; 355