1*2d599bc4SNiravkumar L Rabara// SPDX-License-Identifier: GPL-2.0-only
2*2d599bc4SNiravkumar L Rabara/*
3*2d599bc4SNiravkumar L Rabara * Copyright (C) 2023, Intel Corporation
4*2d599bc4SNiravkumar L Rabara */
5*2d599bc4SNiravkumar L Rabara#include "socfpga_agilex5.dtsi"
6*2d599bc4SNiravkumar L Rabara
7*2d599bc4SNiravkumar L Rabara/ {
8*2d599bc4SNiravkumar L Rabara	model = "SoCFPGA Agilex5 SoCDK";
9*2d599bc4SNiravkumar L Rabara	compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
10*2d599bc4SNiravkumar L Rabara
11*2d599bc4SNiravkumar L Rabara	aliases {
12*2d599bc4SNiravkumar L Rabara		serial0 = &uart0;
13*2d599bc4SNiravkumar L Rabara	};
14*2d599bc4SNiravkumar L Rabara
15*2d599bc4SNiravkumar L Rabara	chosen {
16*2d599bc4SNiravkumar L Rabara		stdout-path = "serial0:115200n8";
17*2d599bc4SNiravkumar L Rabara	};
18*2d599bc4SNiravkumar L Rabara};
19*2d599bc4SNiravkumar L Rabara
20*2d599bc4SNiravkumar L Rabara&gpio1 {
21*2d599bc4SNiravkumar L Rabara	status = "okay";
22*2d599bc4SNiravkumar L Rabara};
23*2d599bc4SNiravkumar L Rabara
24*2d599bc4SNiravkumar L Rabara&osc1 {
25*2d599bc4SNiravkumar L Rabara	clock-frequency = <25000000>;
26*2d599bc4SNiravkumar L Rabara};
27*2d599bc4SNiravkumar L Rabara
28*2d599bc4SNiravkumar L Rabara&uart0 {
29*2d599bc4SNiravkumar L Rabara	status = "okay";
30*2d599bc4SNiravkumar L Rabara};
31*2d599bc4SNiravkumar L Rabara
32*2d599bc4SNiravkumar L Rabara&usb0 {
33*2d599bc4SNiravkumar L Rabara	status = "okay";
34*2d599bc4SNiravkumar L Rabara	disable-over-current;
35*2d599bc4SNiravkumar L Rabara};
36*2d599bc4SNiravkumar L Rabara
37*2d599bc4SNiravkumar L Rabara&watchdog0 {
38*2d599bc4SNiravkumar L Rabara	status = "okay";
39*2d599bc4SNiravkumar L Rabara};
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