1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/agilex-clock.h> 11 12/ { 13 compatible = "intel,socfpga-agilex"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 service_reserved: svcbuffer@0 { 23 compatible = "shared-dma-pool"; 24 reg = <0x0 0x0 0x0 0x2000000>; 25 alignment = <0x1000>; 26 no-map; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 compatible = "arm,cortex-a53"; 36 device_type = "cpu"; 37 enable-method = "psci"; 38 reg = <0x0>; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "arm,cortex-a53"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 reg = <0x1>; 46 }; 47 48 cpu2: cpu@2 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 enable-method = "psci"; 52 reg = <0x2>; 53 }; 54 55 cpu3: cpu@3 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 }; 61 }; 62 63 pmu { 64 compatible = "arm,armv8-pmuv3"; 65 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, 70 <&cpu1>, 71 <&cpu2>, 72 <&cpu3>; 73 interrupt-parent = <&intc>; 74 }; 75 76 psci { 77 compatible = "arm,psci-0.2"; 78 method = "smc"; 79 }; 80 81 intc: interrupt-controller@fffc1000 { 82 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 83 #interrupt-cells = <3>; 84 interrupt-controller; 85 reg = <0x0 0xfffc1000 0x0 0x1000>, 86 <0x0 0xfffc2000 0x0 0x2000>, 87 <0x0 0xfffc4000 0x0 0x2000>, 88 <0x0 0xfffc6000 0x0 0x2000>; 89 }; 90 91 clocks { 92 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 93 #clock-cells = <0>; 94 compatible = "fixed-clock"; 95 }; 96 97 cb_intosc_ls_clk: cb-intosc-ls-clk { 98 #clock-cells = <0>; 99 compatible = "fixed-clock"; 100 }; 101 102 f2s_free_clk: f2s-free-clk { 103 #clock-cells = <0>; 104 compatible = "fixed-clock"; 105 }; 106 107 osc1: osc1 { 108 #clock-cells = <0>; 109 compatible = "fixed-clock"; 110 }; 111 112 qspi_clk: qspi-clk { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 clock-frequency = <200000000>; 116 }; 117 }; 118 119 timer { 120 compatible = "arm,armv8-timer"; 121 interrupt-parent = <&intc>; 122 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 123 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 124 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 125 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 126 }; 127 128 usbphy0: usbphy { 129 #phy-cells = <0>; 130 compatible = "usb-nop-xceiv"; 131 }; 132 133 soc { 134 #address-cells = <1>; 135 #size-cells = <1>; 136 compatible = "simple-bus"; 137 device_type = "soc"; 138 interrupt-parent = <&intc>; 139 ranges = <0 0 0 0xffffffff>; 140 141 base_fpga_region { 142 #address-cells = <0x1>; 143 #size-cells = <0x1>; 144 compatible = "fpga-region"; 145 fpga-mgr = <&fpga_mgr>; 146 }; 147 148 clkmgr: clock-controller@ffd10000 { 149 compatible = "intel,agilex-clkmgr"; 150 reg = <0xffd10000 0x1000>; 151 #clock-cells = <1>; 152 }; 153 154 gmac0: ethernet@ff800000 { 155 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 156 reg = <0xff800000 0x2000>; 157 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "macirq"; 159 mac-address = [00 00 00 00 00 00]; 160 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 161 reset-names = "stmmaceth", "stmmaceth-ocp"; 162 tx-fifo-depth = <16384>; 163 rx-fifo-depth = <16384>; 164 snps,multicast-filter-bins = <256>; 165 iommus = <&smmu 1>; 166 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 167 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 168 clock-names = "stmmaceth", "ptp_ref"; 169 status = "disabled"; 170 }; 171 172 gmac1: ethernet@ff802000 { 173 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 174 reg = <0xff802000 0x2000>; 175 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "macirq"; 177 mac-address = [00 00 00 00 00 00]; 178 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 179 reset-names = "stmmaceth", "stmmaceth-ocp"; 180 tx-fifo-depth = <16384>; 181 rx-fifo-depth = <16384>; 182 snps,multicast-filter-bins = <256>; 183 iommus = <&smmu 2>; 184 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 185 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 186 clock-names = "stmmaceth", "ptp_ref"; 187 status = "disabled"; 188 }; 189 190 gmac2: ethernet@ff804000 { 191 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 192 reg = <0xff804000 0x2000>; 193 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "macirq"; 195 mac-address = [00 00 00 00 00 00]; 196 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 197 reset-names = "stmmaceth", "stmmaceth-ocp"; 198 tx-fifo-depth = <16384>; 199 rx-fifo-depth = <16384>; 200 snps,multicast-filter-bins = <256>; 201 iommus = <&smmu 3>; 202 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 203 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 204 clock-names = "stmmaceth", "ptp_ref"; 205 status = "disabled"; 206 }; 207 208 gpio0: gpio@ffc03200 { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 compatible = "snps,dw-apb-gpio"; 212 reg = <0xffc03200 0x100>; 213 resets = <&rst GPIO0_RESET>; 214 status = "disabled"; 215 216 porta: gpio-controller@0 { 217 compatible = "snps,dw-apb-gpio-port"; 218 gpio-controller; 219 #gpio-cells = <2>; 220 snps,nr-gpios = <24>; 221 reg = <0>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 225 }; 226 }; 227 228 gpio1: gpio@ffc03300 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 compatible = "snps,dw-apb-gpio"; 232 reg = <0xffc03300 0x100>; 233 resets = <&rst GPIO1_RESET>; 234 status = "disabled"; 235 236 portb: gpio-controller@0 { 237 compatible = "snps,dw-apb-gpio-port"; 238 gpio-controller; 239 #gpio-cells = <2>; 240 snps,nr-gpios = <24>; 241 reg = <0>; 242 interrupt-controller; 243 #interrupt-cells = <2>; 244 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 245 }; 246 }; 247 248 i2c0: i2c@ffc02800 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "snps,designware-i2c"; 252 reg = <0xffc02800 0x100>; 253 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 254 resets = <&rst I2C0_RESET>; 255 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 256 status = "disabled"; 257 }; 258 259 i2c1: i2c@ffc02900 { 260 #address-cells = <1>; 261 #size-cells = <0>; 262 compatible = "snps,designware-i2c"; 263 reg = <0xffc02900 0x100>; 264 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 265 resets = <&rst I2C1_RESET>; 266 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 267 status = "disabled"; 268 }; 269 270 i2c2: i2c@ffc02a00 { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 compatible = "snps,designware-i2c"; 274 reg = <0xffc02a00 0x100>; 275 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 276 resets = <&rst I2C2_RESET>; 277 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 278 status = "disabled"; 279 }; 280 281 i2c3: i2c@ffc02b00 { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 compatible = "snps,designware-i2c"; 285 reg = <0xffc02b00 0x100>; 286 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 287 resets = <&rst I2C3_RESET>; 288 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 289 status = "disabled"; 290 }; 291 292 i2c4: i2c@ffc02c00 { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 compatible = "snps,designware-i2c"; 296 reg = <0xffc02c00 0x100>; 297 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 298 resets = <&rst I2C4_RESET>; 299 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 300 status = "disabled"; 301 }; 302 303 mmc: mmc@ff808000 { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 compatible = "altr,socfpga-dw-mshc"; 307 reg = <0xff808000 0x1000>; 308 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 309 fifo-depth = <0x400>; 310 resets = <&rst SDMMC_RESET>; 311 reset-names = "reset"; 312 clocks = <&clkmgr AGILEX_L4_MP_CLK>, 313 <&clkmgr AGILEX_SDMMC_CLK>; 314 clock-names = "biu", "ciu"; 315 iommus = <&smmu 5>; 316 status = "disabled"; 317 }; 318 319 nand: nand-controller@ffb90000 { 320 #address-cells = <1>; 321 #size-cells = <0>; 322 compatible = "altr,socfpga-denali-nand"; 323 reg = <0xffb90000 0x10000>, 324 <0xffb80000 0x1000>; 325 reg-names = "nand_data", "denali_reg"; 326 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clkmgr AGILEX_NAND_CLK>, 328 <&clkmgr AGILEX_NAND_X_CLK>, 329 <&clkmgr AGILEX_NAND_ECC_CLK>; 330 clock-names = "nand", "nand_x", "ecc"; 331 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 332 status = "disabled"; 333 }; 334 335 ocram: sram@ffe00000 { 336 compatible = "mmio-sram"; 337 reg = <0xffe00000 0x40000>; 338 }; 339 340 pdma: dma-controller@ffda0000 { 341 compatible = "arm,pl330", "arm,primecell"; 342 reg = <0xffda0000 0x1000>; 343 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 352 #dma-cells = <1>; 353 #dma-channels = <8>; 354 #dma-requests = <32>; 355 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 356 reset-names = "dma", "dma-ocp"; 357 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 358 clock-names = "apb_pclk"; 359 }; 360 361 rst: rstmgr@ffd11000 { 362 #reset-cells = <1>; 363 compatible = "altr,stratix10-rst-mgr"; 364 reg = <0xffd11000 0x100>; 365 }; 366 367 smmu: iommu@fa000000 { 368 compatible = "arm,mmu-500", "arm,smmu-v2"; 369 reg = <0xfa000000 0x40000>; 370 #global-interrupts = <2>; 371 #iommu-cells = <1>; 372 interrupt-parent = <&intc>; 373 /* Global Secure Fault */ 374 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 375 /* Global Non-secure Fault */ 376 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 377 /* Non-secure Context Interrupts (32) */ 378 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 410 stream-match-mask = <0x7ff0>; 411 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, 412 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, 413 <&clkmgr AGILEX_L4_MAIN_CLK>; 414 status = "disabled"; 415 }; 416 417 spi0: spi@ffda4000 { 418 compatible = "snps,dw-apb-ssi"; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 reg = <0xffda4000 0x1000>; 422 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 423 resets = <&rst SPIM0_RESET>; 424 reset-names = "spi"; 425 reg-io-width = <4>; 426 num-cs = <4>; 427 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 428 status = "disabled"; 429 }; 430 431 spi1: spi@ffda5000 { 432 compatible = "snps,dw-apb-ssi"; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 reg = <0xffda5000 0x1000>; 436 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 437 resets = <&rst SPIM1_RESET>; 438 reset-names = "spi"; 439 reg-io-width = <4>; 440 num-cs = <4>; 441 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 442 status = "disabled"; 443 }; 444 445 sysmgr: sysmgr@ffd12000 { 446 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 447 reg = <0xffd12000 0x500>; 448 }; 449 450 timer0: timer0@ffc03000 { 451 compatible = "snps,dw-apb-timer"; 452 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 453 reg = <0xffc03000 0x100>; 454 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 455 clock-names = "timer"; 456 }; 457 458 timer1: timer1@ffc03100 { 459 compatible = "snps,dw-apb-timer"; 460 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 461 reg = <0xffc03100 0x100>; 462 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 463 clock-names = "timer"; 464 }; 465 466 timer2: timer2@ffd00000 { 467 compatible = "snps,dw-apb-timer"; 468 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 469 reg = <0xffd00000 0x100>; 470 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 471 clock-names = "timer"; 472 }; 473 474 timer3: timer3@ffd00100 { 475 compatible = "snps,dw-apb-timer"; 476 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 477 reg = <0xffd00100 0x100>; 478 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 479 clock-names = "timer"; 480 }; 481 482 uart0: serial@ffc02000 { 483 compatible = "snps,dw-apb-uart"; 484 reg = <0xffc02000 0x100>; 485 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 486 reg-shift = <2>; 487 reg-io-width = <4>; 488 resets = <&rst UART0_RESET>; 489 status = "disabled"; 490 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 491 }; 492 493 uart1: serial@ffc02100 { 494 compatible = "snps,dw-apb-uart"; 495 reg = <0xffc02100 0x100>; 496 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 497 reg-shift = <2>; 498 reg-io-width = <4>; 499 resets = <&rst UART1_RESET>; 500 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 501 status = "disabled"; 502 }; 503 504 usb0: usb@ffb00000 { 505 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 506 reg = <0xffb00000 0x40000>; 507 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 508 phys = <&usbphy0>; 509 phy-names = "usb2-phy"; 510 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 511 reset-names = "dwc2", "dwc2-ecc"; 512 clocks = <&clkmgr AGILEX_USB_CLK>; 513 clock-names = "otg"; 514 iommus = <&smmu 6>; 515 status = "disabled"; 516 }; 517 518 usb1: usb@ffb40000 { 519 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 520 reg = <0xffb40000 0x40000>; 521 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 522 phys = <&usbphy0>; 523 phy-names = "usb2-phy"; 524 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 525 reset-names = "dwc2", "dwc2-ecc"; 526 iommus = <&smmu 7>; 527 clocks = <&clkmgr AGILEX_USB_CLK>; 528 status = "disabled"; 529 }; 530 531 watchdog0: watchdog@ffd00200 { 532 compatible = "snps,dw-wdt"; 533 reg = <0xffd00200 0x100>; 534 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 535 resets = <&rst WATCHDOG0_RESET>; 536 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 537 status = "disabled"; 538 }; 539 540 watchdog1: watchdog@ffd00300 { 541 compatible = "snps,dw-wdt"; 542 reg = <0xffd00300 0x100>; 543 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 544 resets = <&rst WATCHDOG1_RESET>; 545 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 546 status = "disabled"; 547 }; 548 549 watchdog2: watchdog@ffd00400 { 550 compatible = "snps,dw-wdt"; 551 reg = <0xffd00400 0x100>; 552 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 553 resets = <&rst WATCHDOG2_RESET>; 554 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 555 status = "disabled"; 556 }; 557 558 watchdog3: watchdog@ffd00500 { 559 compatible = "snps,dw-wdt"; 560 reg = <0xffd00500 0x100>; 561 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 562 resets = <&rst WATCHDOG3_RESET>; 563 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 564 status = "disabled"; 565 }; 566 567 sdr: sdr@f8011100 { 568 compatible = "altr,sdr-ctl", "syscon"; 569 reg = <0xf8011100 0xc0>; 570 }; 571 572 eccmgr { 573 compatible = "altr,socfpga-s10-ecc-manager", 574 "altr,socfpga-a10-ecc-manager"; 575 altr,sysmgr-syscon = <&sysmgr>; 576 #address-cells = <1>; 577 #size-cells = <1>; 578 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 579 interrupt-controller; 580 #interrupt-cells = <2>; 581 ranges; 582 583 sdramedac { 584 compatible = "altr,sdram-edac-s10"; 585 altr,sdr-syscon = <&sdr>; 586 interrupts = <16 4>; 587 }; 588 589 ocram-ecc@ff8cc000 { 590 compatible = "altr,socfpga-s10-ocram-ecc", 591 "altr,socfpga-a10-ocram-ecc"; 592 reg = <0xff8cc000 0x100>; 593 altr,ecc-parent = <&ocram>; 594 interrupts = <1 4>; 595 }; 596 597 usb0-ecc@ff8c4000 { 598 compatible = "altr,socfpga-s10-usb-ecc", 599 "altr,socfpga-usb-ecc"; 600 reg = <0xff8c4000 0x100>; 601 altr,ecc-parent = <&usb0>; 602 interrupts = <2 4>; 603 }; 604 605 emac0-rx-ecc@ff8c0000 { 606 compatible = "altr,socfpga-s10-eth-mac-ecc", 607 "altr,socfpga-eth-mac-ecc"; 608 reg = <0xff8c0000 0x100>; 609 altr,ecc-parent = <&gmac0>; 610 interrupts = <4 4>; 611 }; 612 613 emac0-tx-ecc@ff8c0400 { 614 compatible = "altr,socfpga-s10-eth-mac-ecc", 615 "altr,socfpga-eth-mac-ecc"; 616 reg = <0xff8c0400 0x100>; 617 altr,ecc-parent = <&gmac0>; 618 interrupts = <5 4>; 619 }; 620 621 sdmmca-ecc@ff8c8c00 { 622 compatible = "altr,socfpga-s10-sdmmc-ecc", 623 "altr,socfpga-sdmmc-ecc"; 624 reg = <0xff8c8c00 0x100>; 625 altr,ecc-parent = <&mmc>; 626 interrupts = <14 4>, 627 <15 4>; 628 }; 629 }; 630 631 qspi: spi@ff8d2000 { 632 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 reg = <0xff8d2000 0x100>, 636 <0xff900000 0x100000>; 637 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 638 cdns,fifo-depth = <128>; 639 cdns,fifo-width = <4>; 640 cdns,trigger-address = <0x00000000>; 641 clocks = <&qspi_clk>; 642 643 status = "disabled"; 644 }; 645 646 firmware { 647 svc { 648 compatible = "intel,agilex-svc"; 649 method = "smc"; 650 memory-region = <&service_reserved>; 651 652 fpga_mgr: fpga-mgr { 653 compatible = "intel,agilex-soc-fpga-mgr"; 654 }; 655 }; 656 }; 657 }; 658}; 659