1// SPDX-License-Identifier:     GPL-2.0
2/*
3 * Copyright (C) 2019, Intel Corporation
4 */
5
6/dts-v1/;
7#include <dt-bindings/reset/altr,rst-mgr-s10.h>
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	compatible = "intel,socfpga-agilex";
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	reserved-memory {
16		#address-cells = <2>;
17		#size-cells = <2>;
18		ranges;
19
20		service_reserved: svcbuffer@0 {
21			compatible = "shared-dma-pool";
22			reg = <0x0 0x0 0x0 0x1000000>;
23			alignment = <0x1000>;
24			no-map;
25		};
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			compatible = "arm,cortex-a53";
34			device_type = "cpu";
35			enable-method = "psci";
36			reg = <0x0>;
37		};
38
39		cpu1: cpu@1 {
40			compatible = "arm,cortex-a53";
41			device_type = "cpu";
42			enable-method = "psci";
43			reg = <0x1>;
44		};
45
46		cpu2: cpu@2 {
47			compatible = "arm,cortex-a53";
48			device_type = "cpu";
49			enable-method = "psci";
50			reg = <0x2>;
51		};
52
53		cpu3: cpu@3 {
54			compatible = "arm,cortex-a53";
55			device_type = "cpu";
56			enable-method = "psci";
57			reg = <0x3>;
58		};
59	};
60
61	pmu {
62		compatible = "arm,armv8-pmuv3";
63		interrupts = <0 120 8>,
64			     <0 121 8>,
65			     <0 122 8>,
66			     <0 123 8>;
67		interrupt-affinity = <&cpu0>,
68				     <&cpu1>,
69				     <&cpu2>,
70				     <&cpu3>;
71		interrupt-parent = <&intc>;
72	};
73
74	psci {
75		compatible = "arm,psci-0.2";
76		method = "smc";
77	};
78
79	intc: intc@fffc1000 {
80		compatible = "arm,gic-400", "arm,cortex-a15-gic";
81		#interrupt-cells = <3>;
82		interrupt-controller;
83		reg = <0x0 0xfffc1000 0x0 0x1000>,
84		      <0x0 0xfffc2000 0x0 0x2000>,
85		      <0x0 0xfffc4000 0x0 0x2000>,
86		      <0x0 0xfffc6000 0x0 0x2000>;
87	};
88
89	soc {
90		#address-cells = <1>;
91		#size-cells = <1>;
92		compatible = "simple-bus";
93		device_type = "soc";
94		interrupt-parent = <&intc>;
95		ranges = <0 0 0 0xffffffff>;
96
97		base_fpga_region {
98			#address-cells = <0x1>;
99			#size-cells = <0x1>;
100			compatible = "fpga-region";
101			fpga-mgr = <&fpga_mgr>;
102		};
103
104		gmac0: ethernet@ff800000 {
105			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
106			reg = <0xff800000 0x2000>;
107			interrupts = <0 90 4>;
108			interrupt-names = "macirq";
109			mac-address = [00 00 00 00 00 00];
110			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
111			reset-names = "stmmaceth", "stmmaceth-ocp";
112			tx-fifo-depth = <16384>;
113			rx-fifo-depth = <16384>;
114			snps,multicast-filter-bins = <256>;
115			iommus = <&smmu 1>;
116			status = "disabled";
117		};
118
119		gmac1: ethernet@ff802000 {
120			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
121			reg = <0xff802000 0x2000>;
122			interrupts = <0 91 4>;
123			interrupt-names = "macirq";
124			mac-address = [00 00 00 00 00 00];
125			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
126			reset-names = "stmmaceth", "stmmaceth-ocp";
127			tx-fifo-depth = <16384>;
128			rx-fifo-depth = <16384>;
129			snps,multicast-filter-bins = <256>;
130			iommus = <&smmu 2>;
131			status = "disabled";
132		};
133
134		gmac2: ethernet@ff804000 {
135			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
136			reg = <0xff804000 0x2000>;
137			interrupts = <0 92 4>;
138			interrupt-names = "macirq";
139			mac-address = [00 00 00 00 00 00];
140			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
141			reset-names = "stmmaceth", "stmmaceth-ocp";
142			tx-fifo-depth = <16384>;
143			rx-fifo-depth = <16384>;
144			snps,multicast-filter-bins = <256>;
145			iommus = <&smmu 3>;
146			status = "disabled";
147		};
148
149		gpio0: gpio@ffc03200 {
150			#address-cells = <1>;
151			#size-cells = <0>;
152			compatible = "snps,dw-apb-gpio";
153			reg = <0xffc03200 0x100>;
154			resets = <&rst GPIO0_RESET>;
155			status = "disabled";
156
157			porta: gpio-controller@0 {
158				compatible = "snps,dw-apb-gpio-port";
159				gpio-controller;
160				#gpio-cells = <2>;
161				snps,nr-gpios = <24>;
162				reg = <0>;
163				interrupt-controller;
164				#interrupt-cells = <2>;
165				interrupts = <0 110 4>;
166			};
167		};
168
169		gpio1: gpio@ffc03300 {
170			#address-cells = <1>;
171			#size-cells = <0>;
172			compatible = "snps,dw-apb-gpio";
173			reg = <0xffc03300 0x100>;
174			resets = <&rst GPIO1_RESET>;
175			status = "disabled";
176
177			portb: gpio-controller@0 {
178				compatible = "snps,dw-apb-gpio-port";
179				gpio-controller;
180				#gpio-cells = <2>;
181				snps,nr-gpios = <24>;
182				reg = <0>;
183				interrupt-controller;
184				#interrupt-cells = <2>;
185				interrupts = <0 111 4>;
186			};
187		};
188
189		i2c0: i2c@ffc02800 {
190			#address-cells = <1>;
191			#size-cells = <0>;
192			compatible = "snps,designware-i2c";
193			reg = <0xffc02800 0x100>;
194			interrupts = <0 103 4>;
195			resets = <&rst I2C0_RESET>;
196			status = "disabled";
197		};
198
199		i2c1: i2c@ffc02900 {
200			#address-cells = <1>;
201			#size-cells = <0>;
202			compatible = "snps,designware-i2c";
203			reg = <0xffc02900 0x100>;
204			interrupts = <0 104 4>;
205			resets = <&rst I2C1_RESET>;
206			status = "disabled";
207		};
208
209		i2c2: i2c@ffc02a00 {
210			#address-cells = <1>;
211			#size-cells = <0>;
212			compatible = "snps,designware-i2c";
213			reg = <0xffc02a00 0x100>;
214			interrupts = <0 105 4>;
215			resets = <&rst I2C2_RESET>;
216			status = "disabled";
217		};
218
219		i2c3: i2c@ffc02b00 {
220			#address-cells = <1>;
221			#size-cells = <0>;
222			compatible = "snps,designware-i2c";
223			reg = <0xffc02b00 0x100>;
224			interrupts = <0 106 4>;
225			resets = <&rst I2C3_RESET>;
226			status = "disabled";
227		};
228
229		i2c4: i2c@ffc02c00 {
230			#address-cells = <1>;
231			#size-cells = <0>;
232			compatible = "snps,designware-i2c";
233			reg = <0xffc02c00 0x100>;
234			interrupts = <0 107 4>;
235			resets = <&rst I2C4_RESET>;
236			status = "disabled";
237		};
238
239		mmc: dwmmc0@ff808000 {
240			#address-cells = <1>;
241			#size-cells = <0>;
242			compatible = "altr,socfpga-dw-mshc";
243			reg = <0xff808000 0x1000>;
244			interrupts = <0 96 4>;
245			fifo-depth = <0x400>;
246			resets = <&rst SDMMC_RESET>;
247			reset-names = "reset";
248			iommus = <&smmu 5>;
249			status = "disabled";
250		};
251
252		ocram: sram@ffe00000 {
253			compatible = "mmio-sram";
254			reg = <0xffe00000 0x40000>;
255		};
256
257		pdma: pdma@ffda0000 {
258			compatible = "arm,pl330", "arm,primecell";
259			reg = <0xffda0000 0x1000>;
260			interrupts = <0 81 4>,
261				     <0 82 4>,
262				     <0 83 4>,
263				     <0 84 4>,
264				     <0 85 4>,
265				     <0 86 4>,
266				     <0 87 4>,
267				     <0 88 4>,
268				     <0 89 4>;
269			#dma-cells = <1>;
270			#dma-channels = <8>;
271			#dma-requests = <32>;
272			resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
273			reset-names = "dma", "dma-ocp";
274		};
275
276		rst: rstmgr@ffd11000 {
277			#reset-cells = <1>;
278			compatible = "altr,stratix10-rst-mgr";
279			reg = <0xffd11000 0x100>;
280		};
281
282		smmu: iommu@fa000000 {
283			compatible = "arm,mmu-500", "arm,smmu-v2";
284			reg = <0xfa000000 0x40000>;
285			#global-interrupts = <2>;
286			#iommu-cells = <1>;
287			interrupt-parent = <&intc>;
288			interrupts = <0 128 4>,	/* Global Secure Fault */
289				<0 129 4>, /* Global Non-secure Fault */
290				/* Non-secure Context Interrupts (32) */
291				<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
292				<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
293				<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
294				<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
295				<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
296				<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
297				<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
298				<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
299			stream-match-mask = <0x7ff0>;
300			status = "disabled";
301		};
302
303		spi0: spi@ffda4000 {
304			compatible = "snps,dw-apb-ssi";
305			#address-cells = <1>;
306			#size-cells = <0>;
307			reg = <0xffda4000 0x1000>;
308			interrupts = <0 99 4>;
309			resets = <&rst SPIM0_RESET>;
310			reg-io-width = <4>;
311			num-cs = <4>;
312			status = "disabled";
313		};
314
315		spi1: spi@ffda5000 {
316			compatible = "snps,dw-apb-ssi";
317			#address-cells = <1>;
318			#size-cells = <0>;
319			reg = <0xffda5000 0x1000>;
320			interrupts = <0 100 4>;
321			resets = <&rst SPIM1_RESET>;
322			reg-io-width = <4>;
323			num-cs = <4>;
324			status = "disabled";
325		};
326
327		sysmgr: sysmgr@ffd12000 {
328			compatible = "altr,sys-mgr", "syscon";
329			reg = <0xffd12000 0x500>;
330		};
331
332		/* Local timer */
333		timer {
334			compatible = "arm,armv8-timer";
335			interrupts = <1 13 0xf08>,
336				     <1 14 0xf08>,
337				     <1 11 0xf08>,
338				     <1 10 0xf08>;
339		};
340
341		timer0: timer0@ffc03000 {
342			compatible = "snps,dw-apb-timer";
343			interrupts = <0 113 4>;
344			reg = <0xffc03000 0x100>;
345		};
346
347		timer1: timer1@ffc03100 {
348			compatible = "snps,dw-apb-timer";
349			interrupts = <0 114 4>;
350			reg = <0xffc03100 0x100>;
351		};
352
353		timer2: timer2@ffd00000 {
354			compatible = "snps,dw-apb-timer";
355			interrupts = <0 115 4>;
356			reg = <0xffd00000 0x100>;
357		};
358
359		timer3: timer3@ffd00100 {
360			compatible = "snps,dw-apb-timer";
361			interrupts = <0 116 4>;
362			reg = <0xffd00100 0x100>;
363		};
364
365		uart0: serial0@ffc02000 {
366			compatible = "snps,dw-apb-uart";
367			reg = <0xffc02000 0x100>;
368			interrupts = <0 108 4>;
369			reg-shift = <2>;
370			reg-io-width = <4>;
371			resets = <&rst UART0_RESET>;
372			status = "disabled";
373		};
374
375		uart1: serial1@ffc02100 {
376			compatible = "snps,dw-apb-uart";
377			reg = <0xffc02100 0x100>;
378			interrupts = <0 109 4>;
379			reg-shift = <2>;
380			reg-io-width = <4>;
381			resets = <&rst UART1_RESET>;
382			status = "disabled";
383		};
384
385		usbphy0: usbphy@0 {
386			#phy-cells = <0>;
387			compatible = "usb-nop-xceiv";
388			status = "okay";
389		};
390
391		usb0: usb@ffb00000 {
392			compatible = "snps,dwc2";
393			reg = <0xffb00000 0x40000>;
394			interrupts = <0 93 4>;
395			phys = <&usbphy0>;
396			phy-names = "usb2-phy";
397			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
398			reset-names = "dwc2", "dwc2-ecc";
399			iommus = <&smmu 6>;
400			status = "disabled";
401		};
402
403		usb1: usb@ffb40000 {
404			compatible = "snps,dwc2";
405			reg = <0xffb40000 0x40000>;
406			interrupts = <0 94 4>;
407			phys = <&usbphy0>;
408			phy-names = "usb2-phy";
409			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
410			reset-names = "dwc2", "dwc2-ecc";
411			iommus = <&smmu 7>;
412			status = "disabled";
413		};
414
415		watchdog0: watchdog@ffd00200 {
416			compatible = "snps,dw-wdt";
417			reg = <0xffd00200 0x100>;
418			interrupts = <0 117 4>;
419			resets = <&rst WATCHDOG0_RESET>;
420			status = "disabled";
421		};
422
423		watchdog1: watchdog@ffd00300 {
424			compatible = "snps,dw-wdt";
425			reg = <0xffd00300 0x100>;
426			interrupts = <0 118 4>;
427			resets = <&rst WATCHDOG1_RESET>;
428			status = "disabled";
429		};
430
431		watchdog2: watchdog@ffd00400 {
432			compatible = "snps,dw-wdt";
433			reg = <0xffd00400 0x100>;
434			interrupts = <0 125 4>;
435			resets = <&rst WATCHDOG2_RESET>;
436			status = "disabled";
437		};
438
439		watchdog3: watchdog@ffd00500 {
440			compatible = "snps,dw-wdt";
441			reg = <0xffd00500 0x100>;
442			interrupts = <0 126 4>;
443			resets = <&rst WATCHDOG3_RESET>;
444			status = "disabled";
445		};
446
447		sdr: sdr@f8011100 {
448			compatible = "altr,sdr-ctl", "syscon";
449			reg = <0xf8011100 0xc0>;
450		};
451
452		qspi: spi@ff8d2000 {
453			compatible = "cdns,qspi-nor";
454			#address-cells = <1>;
455			#size-cells = <0>;
456			reg = <0xff8d2000 0x100>,
457			      <0xff900000 0x100000>;
458			interrupts = <0 3 4>;
459			cdns,fifo-depth = <128>;
460			cdns,fifo-width = <4>;
461			cdns,trigger-address = <0x00000000>;
462
463			status = "disabled";
464		};
465
466		firmware {
467			svc {
468				compatible = "intel,stratix10-svc";
469				method = "smc";
470				memory-region = <&service_reserved>;
471
472				fpga_mgr: fpga-mgr {
473					compatible = "intel,stratix10-soc-fpga-mgr";
474				};
475			};
476		};
477	};
478};
479