1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/agilex-clock.h> 11 12/ { 13 compatible = "intel,socfpga-agilex"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 service_reserved: svcbuffer@0 { 23 compatible = "shared-dma-pool"; 24 reg = <0x0 0x0 0x0 0x2000000>; 25 alignment = <0x1000>; 26 no-map; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 compatible = "arm,cortex-a53"; 36 device_type = "cpu"; 37 enable-method = "psci"; 38 reg = <0x0>; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "arm,cortex-a53"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 reg = <0x1>; 46 }; 47 48 cpu2: cpu@2 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 enable-method = "psci"; 52 reg = <0x2>; 53 }; 54 55 cpu3: cpu@3 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 }; 61 }; 62 63 pmu { 64 compatible = "arm,armv8-pmuv3"; 65 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, 70 <&cpu1>, 71 <&cpu2>, 72 <&cpu3>; 73 interrupt-parent = <&intc>; 74 }; 75 76 psci { 77 compatible = "arm,psci-0.2"; 78 method = "smc"; 79 }; 80 81 intc: interrupt-controller@fffc1000 { 82 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 83 #interrupt-cells = <3>; 84 interrupt-controller; 85 reg = <0x0 0xfffc1000 0x0 0x1000>, 86 <0x0 0xfffc2000 0x0 0x2000>, 87 <0x0 0xfffc4000 0x0 0x2000>, 88 <0x0 0xfffc6000 0x0 0x2000>; 89 }; 90 91 clocks { 92 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 93 #clock-cells = <0>; 94 compatible = "fixed-clock"; 95 }; 96 97 cb_intosc_ls_clk: cb-intosc-ls-clk { 98 #clock-cells = <0>; 99 compatible = "fixed-clock"; 100 }; 101 102 f2s_free_clk: f2s-free-clk { 103 #clock-cells = <0>; 104 compatible = "fixed-clock"; 105 }; 106 107 osc1: osc1 { 108 #clock-cells = <0>; 109 compatible = "fixed-clock"; 110 }; 111 112 qspi_clk: qspi-clk { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 clock-frequency = <200000000>; 116 }; 117 }; 118 119 timer { 120 compatible = "arm,armv8-timer"; 121 interrupt-parent = <&intc>; 122 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 123 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 124 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 125 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 126 }; 127 128 usbphy0: usbphy { 129 #phy-cells = <0>; 130 compatible = "usb-nop-xceiv"; 131 }; 132 133 soc { 134 #address-cells = <1>; 135 #size-cells = <1>; 136 compatible = "simple-bus"; 137 device_type = "soc"; 138 interrupt-parent = <&intc>; 139 ranges = <0 0 0 0xffffffff>; 140 141 base_fpga_region { 142 #address-cells = <0x1>; 143 #size-cells = <0x1>; 144 compatible = "fpga-region"; 145 fpga-mgr = <&fpga_mgr>; 146 }; 147 148 clkmgr: clock-controller@ffd10000 { 149 compatible = "intel,agilex-clkmgr"; 150 reg = <0xffd10000 0x1000>; 151 #clock-cells = <1>; 152 }; 153 154 gmac0: ethernet@ff800000 { 155 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 156 reg = <0xff800000 0x2000>; 157 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "macirq"; 159 mac-address = [00 00 00 00 00 00]; 160 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 161 reset-names = "stmmaceth", "stmmaceth-ocp"; 162 tx-fifo-depth = <16384>; 163 rx-fifo-depth = <16384>; 164 snps,multicast-filter-bins = <256>; 165 iommus = <&smmu 1>; 166 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 167 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 168 clock-names = "stmmaceth", "ptp_ref"; 169 status = "disabled"; 170 }; 171 172 gmac1: ethernet@ff802000 { 173 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 174 reg = <0xff802000 0x2000>; 175 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "macirq"; 177 mac-address = [00 00 00 00 00 00]; 178 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 179 reset-names = "stmmaceth", "stmmaceth-ocp"; 180 tx-fifo-depth = <16384>; 181 rx-fifo-depth = <16384>; 182 snps,multicast-filter-bins = <256>; 183 iommus = <&smmu 2>; 184 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 185 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 186 clock-names = "stmmaceth", "ptp_ref"; 187 status = "disabled"; 188 }; 189 190 gmac2: ethernet@ff804000 { 191 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 192 reg = <0xff804000 0x2000>; 193 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "macirq"; 195 mac-address = [00 00 00 00 00 00]; 196 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 197 reset-names = "stmmaceth", "stmmaceth-ocp"; 198 tx-fifo-depth = <16384>; 199 rx-fifo-depth = <16384>; 200 snps,multicast-filter-bins = <256>; 201 iommus = <&smmu 3>; 202 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 203 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 204 clock-names = "stmmaceth", "ptp_ref"; 205 status = "disabled"; 206 }; 207 208 gpio0: gpio@ffc03200 { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 compatible = "snps,dw-apb-gpio"; 212 reg = <0xffc03200 0x100>; 213 resets = <&rst GPIO0_RESET>; 214 status = "disabled"; 215 216 porta: gpio-controller@0 { 217 compatible = "snps,dw-apb-gpio-port"; 218 gpio-controller; 219 #gpio-cells = <2>; 220 snps,nr-gpios = <24>; 221 reg = <0>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 225 }; 226 }; 227 228 gpio1: gpio@ffc03300 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 compatible = "snps,dw-apb-gpio"; 232 reg = <0xffc03300 0x100>; 233 resets = <&rst GPIO1_RESET>; 234 status = "disabled"; 235 236 portb: gpio-controller@0 { 237 compatible = "snps,dw-apb-gpio-port"; 238 gpio-controller; 239 #gpio-cells = <2>; 240 snps,nr-gpios = <24>; 241 reg = <0>; 242 interrupt-controller; 243 #interrupt-cells = <2>; 244 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 245 }; 246 }; 247 248 i2c0: i2c@ffc02800 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "snps,designware-i2c"; 252 reg = <0xffc02800 0x100>; 253 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 254 resets = <&rst I2C0_RESET>; 255 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 256 status = "disabled"; 257 }; 258 259 i2c1: i2c@ffc02900 { 260 #address-cells = <1>; 261 #size-cells = <0>; 262 compatible = "snps,designware-i2c"; 263 reg = <0xffc02900 0x100>; 264 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 265 resets = <&rst I2C1_RESET>; 266 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 267 status = "disabled"; 268 }; 269 270 i2c2: i2c@ffc02a00 { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 compatible = "snps,designware-i2c"; 274 reg = <0xffc02a00 0x100>; 275 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 276 resets = <&rst I2C2_RESET>; 277 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 278 status = "disabled"; 279 }; 280 281 i2c3: i2c@ffc02b00 { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 compatible = "snps,designware-i2c"; 285 reg = <0xffc02b00 0x100>; 286 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 287 resets = <&rst I2C3_RESET>; 288 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 289 status = "disabled"; 290 }; 291 292 i2c4: i2c@ffc02c00 { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 compatible = "snps,designware-i2c"; 296 reg = <0xffc02c00 0x100>; 297 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 298 resets = <&rst I2C4_RESET>; 299 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 300 status = "disabled"; 301 }; 302 303 mmc: mmc@ff808000 { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 compatible = "altr,socfpga-dw-mshc"; 307 reg = <0xff808000 0x1000>; 308 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 309 fifo-depth = <0x400>; 310 resets = <&rst SDMMC_RESET>; 311 reset-names = "reset"; 312 clocks = <&clkmgr AGILEX_L4_MP_CLK>, 313 <&clkmgr AGILEX_SDMMC_CLK>; 314 clock-names = "biu", "ciu"; 315 iommus = <&smmu 5>; 316 altr,sysmgr-syscon = <&sysmgr 0x28 4>; 317 status = "disabled"; 318 }; 319 320 nand: nand-controller@ffb90000 { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 compatible = "altr,socfpga-denali-nand"; 324 reg = <0xffb90000 0x10000>, 325 <0xffb80000 0x1000>; 326 reg-names = "nand_data", "denali_reg"; 327 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&clkmgr AGILEX_NAND_CLK>, 329 <&clkmgr AGILEX_NAND_X_CLK>, 330 <&clkmgr AGILEX_NAND_ECC_CLK>; 331 clock-names = "nand", "nand_x", "ecc"; 332 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 333 status = "disabled"; 334 }; 335 336 ocram: sram@ffe00000 { 337 compatible = "mmio-sram"; 338 reg = <0xffe00000 0x40000>; 339 }; 340 341 pdma: dma-controller@ffda0000 { 342 compatible = "arm,pl330", "arm,primecell"; 343 reg = <0xffda0000 0x1000>; 344 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 353 #dma-cells = <1>; 354 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 355 reset-names = "dma", "dma-ocp"; 356 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 357 clock-names = "apb_pclk"; 358 }; 359 360 rst: rstmgr@ffd11000 { 361 #reset-cells = <1>; 362 compatible = "altr,stratix10-rst-mgr"; 363 reg = <0xffd11000 0x100>; 364 }; 365 366 smmu: iommu@fa000000 { 367 compatible = "arm,mmu-500", "arm,smmu-v2"; 368 reg = <0xfa000000 0x40000>; 369 #global-interrupts = <2>; 370 #iommu-cells = <1>; 371 interrupt-parent = <&intc>; 372 /* Global Secure Fault */ 373 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 374 /* Global Non-secure Fault */ 375 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 376 /* Non-secure Context Interrupts (32) */ 377 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 409 stream-match-mask = <0x7ff0>; 410 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, 411 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, 412 <&clkmgr AGILEX_L4_MAIN_CLK>; 413 status = "disabled"; 414 }; 415 416 spi0: spi@ffda4000 { 417 compatible = "snps,dw-apb-ssi"; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 reg = <0xffda4000 0x1000>; 421 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 422 resets = <&rst SPIM0_RESET>; 423 reset-names = "spi"; 424 reg-io-width = <4>; 425 num-cs = <4>; 426 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 427 status = "disabled"; 428 }; 429 430 spi1: spi@ffda5000 { 431 compatible = "snps,dw-apb-ssi"; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 reg = <0xffda5000 0x1000>; 435 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 436 resets = <&rst SPIM1_RESET>; 437 reset-names = "spi"; 438 reg-io-width = <4>; 439 num-cs = <4>; 440 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 441 status = "disabled"; 442 }; 443 444 sysmgr: sysmgr@ffd12000 { 445 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 446 reg = <0xffd12000 0x500>; 447 }; 448 449 timer0: timer0@ffc03000 { 450 compatible = "snps,dw-apb-timer"; 451 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 452 reg = <0xffc03000 0x100>; 453 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 454 clock-names = "timer"; 455 }; 456 457 timer1: timer1@ffc03100 { 458 compatible = "snps,dw-apb-timer"; 459 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 460 reg = <0xffc03100 0x100>; 461 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 462 clock-names = "timer"; 463 }; 464 465 timer2: timer2@ffd00000 { 466 compatible = "snps,dw-apb-timer"; 467 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 468 reg = <0xffd00000 0x100>; 469 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 470 clock-names = "timer"; 471 }; 472 473 timer3: timer3@ffd00100 { 474 compatible = "snps,dw-apb-timer"; 475 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 476 reg = <0xffd00100 0x100>; 477 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 478 clock-names = "timer"; 479 }; 480 481 uart0: serial@ffc02000 { 482 compatible = "snps,dw-apb-uart"; 483 reg = <0xffc02000 0x100>; 484 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 485 reg-shift = <2>; 486 reg-io-width = <4>; 487 resets = <&rst UART0_RESET>; 488 status = "disabled"; 489 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 490 }; 491 492 uart1: serial@ffc02100 { 493 compatible = "snps,dw-apb-uart"; 494 reg = <0xffc02100 0x100>; 495 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 496 reg-shift = <2>; 497 reg-io-width = <4>; 498 resets = <&rst UART1_RESET>; 499 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 500 status = "disabled"; 501 }; 502 503 usb0: usb@ffb00000 { 504 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 505 reg = <0xffb00000 0x40000>; 506 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 507 phys = <&usbphy0>; 508 phy-names = "usb2-phy"; 509 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 510 reset-names = "dwc2", "dwc2-ecc"; 511 clocks = <&clkmgr AGILEX_USB_CLK>; 512 clock-names = "otg"; 513 iommus = <&smmu 6>; 514 status = "disabled"; 515 }; 516 517 usb1: usb@ffb40000 { 518 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 519 reg = <0xffb40000 0x40000>; 520 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 521 phys = <&usbphy0>; 522 phy-names = "usb2-phy"; 523 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 524 reset-names = "dwc2", "dwc2-ecc"; 525 iommus = <&smmu 7>; 526 clocks = <&clkmgr AGILEX_USB_CLK>; 527 status = "disabled"; 528 }; 529 530 watchdog0: watchdog@ffd00200 { 531 compatible = "snps,dw-wdt"; 532 reg = <0xffd00200 0x100>; 533 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 534 resets = <&rst WATCHDOG0_RESET>; 535 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 536 status = "disabled"; 537 }; 538 539 watchdog1: watchdog@ffd00300 { 540 compatible = "snps,dw-wdt"; 541 reg = <0xffd00300 0x100>; 542 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 543 resets = <&rst WATCHDOG1_RESET>; 544 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 545 status = "disabled"; 546 }; 547 548 watchdog2: watchdog@ffd00400 { 549 compatible = "snps,dw-wdt"; 550 reg = <0xffd00400 0x100>; 551 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 552 resets = <&rst WATCHDOG2_RESET>; 553 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 554 status = "disabled"; 555 }; 556 557 watchdog3: watchdog@ffd00500 { 558 compatible = "snps,dw-wdt"; 559 reg = <0xffd00500 0x100>; 560 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 561 resets = <&rst WATCHDOG3_RESET>; 562 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 563 status = "disabled"; 564 }; 565 566 sdr: sdr@f8011100 { 567 compatible = "altr,sdr-ctl", "syscon"; 568 reg = <0xf8011100 0xc0>; 569 }; 570 571 eccmgr { 572 compatible = "altr,socfpga-s10-ecc-manager", 573 "altr,socfpga-a10-ecc-manager"; 574 altr,sysmgr-syscon = <&sysmgr>; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 ranges; 581 582 sdramedac { 583 compatible = "altr,sdram-edac-s10"; 584 altr,sdr-syscon = <&sdr>; 585 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 586 }; 587 588 ocram-ecc@ff8cc000 { 589 compatible = "altr,socfpga-s10-ocram-ecc", 590 "altr,socfpga-a10-ocram-ecc"; 591 reg = <0xff8cc000 0x100>; 592 altr,ecc-parent = <&ocram>; 593 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 594 }; 595 596 usb0-ecc@ff8c4000 { 597 compatible = "altr,socfpga-s10-usb-ecc", 598 "altr,socfpga-usb-ecc"; 599 reg = <0xff8c4000 0x100>; 600 altr,ecc-parent = <&usb0>; 601 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 602 }; 603 604 emac0-rx-ecc@ff8c0000 { 605 compatible = "altr,socfpga-s10-eth-mac-ecc", 606 "altr,socfpga-eth-mac-ecc"; 607 reg = <0xff8c0000 0x100>; 608 altr,ecc-parent = <&gmac0>; 609 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 610 }; 611 612 emac0-tx-ecc@ff8c0400 { 613 compatible = "altr,socfpga-s10-eth-mac-ecc", 614 "altr,socfpga-eth-mac-ecc"; 615 reg = <0xff8c0400 0x100>; 616 altr,ecc-parent = <&gmac0>; 617 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 618 }; 619 620 sdmmca-ecc@ff8c8c00 { 621 compatible = "altr,socfpga-s10-sdmmc-ecc", 622 "altr,socfpga-sdmmc-ecc"; 623 reg = <0xff8c8c00 0x100>; 624 altr,ecc-parent = <&mmc>; 625 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 626 <15 IRQ_TYPE_LEVEL_HIGH>; 627 }; 628 }; 629 630 qspi: spi@ff8d2000 { 631 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 reg = <0xff8d2000 0x100>, 635 <0xff900000 0x100000>; 636 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 637 cdns,fifo-depth = <128>; 638 cdns,fifo-width = <4>; 639 cdns,trigger-address = <0x00000000>; 640 clocks = <&qspi_clk>; 641 642 status = "disabled"; 643 }; 644 645 firmware { 646 svc { 647 compatible = "intel,agilex-svc"; 648 method = "smc"; 649 memory-region = <&service_reserved>; 650 651 fpga_mgr: fpga-mgr { 652 compatible = "intel,agilex-soc-fpga-mgr"; 653 }; 654 }; 655 }; 656 }; 657}; 658